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Questions and Answers
What is the Programmable Interval Timer (PIT)?
What is the Programmable Interval Timer (PIT)?
- A VLSI chip with three 16-bit counters (correct)
- A type of computer monitor
- A type of memory storage device
- A 16-bit computer processor
How many I/O ports are assigned to the PIT?
How many I/O ports are assigned to the PIT?
- Four (correct)
- Two
- One
- Three
What happens when the count value of a PIT counter reaches zero?
What happens when the count value of a PIT counter reaches zero?
- A memory read or write occurs
- The PIT enters a sleep mode
- An interrupt is generated (correct)
- The count value resets to its initial value
In what modes can the PIT be programmed?
In what modes can the PIT be programmed?
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What is the resolution of time intervals that the PIT can measure in MP4?
What is the resolution of time intervals that the PIT can measure in MP4?
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What clock does the PIT use to count?
What clock does the PIT use to count?
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How long does each count take for the PIT?
How long does each count take for the PIT?
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How many bus cycles are required for each main memory access?
How many bus cycles are required for each main memory access?
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What is cache memory?
What is cache memory?
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How is L1 cache implemented?
How is L1 cache implemented?
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Study Notes
- The Programmable Interval Timer (PIT) is a VLSI chip with three 16-bit counters.
- Each counter generates an interrupt when the count value reaches zero.
- The PIT has four I/O ports assigned to it, including Timer 0, Timer 1, Timer 2, and Control.
- The PIT can be programmed into different modes, including Mode 0, Mode 2, and Mode 3.
- The PIT is used to measure time intervals in MP4, with a resolution of microseconds.
- The PIT uses a 1.193 MHz clock to count, and each count takes 55 milliseconds.
- The count value can be read using the counter latch command without disturbing the count in progress.
- Main memory access requires one bus cycle per memory read or write.
- Cache memory is located between the CPU and main memory and holds a copy of the most recently accessed data.
- L1 cache is implemented with hidden registers, while L2 cache is implemented with SRAM memory.
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