Logical vs Physical Address Space

Logical Address Space

• Generated by the CPU during program execution.
• Distinct from the physical address space, which indicates actual memory locations.

Physical Address Space

• Refers to the actual addresses in the RAM (main memory).

Memory Management Unit (MMU)

• It maps logical addresses to physical addresses.
• Uses address translation mechanisms.
• Translates logical addresses from the CPU to corresponding physical addresses in memory.

Compile-Time Binding

• Logical address is directly mapped to the physical address.
• Both addresses become identical.

Base and Limit Registers

• Define the range of addresses a process can access.
• Ensure processes don't access unauthorized memory locations.
• In a system, a process's memory access is confined to a specific range
• Help provides enhances security and isolation by ensuring a process can only access memory within its assigned range.
• Each segment table entry contains the base address and limit (size) of the segment.
• Used to define the segments size.

Static Loading

• Loads the entire program into memory before execution starts.
• Simple and suitable for programs that rarely change
• The entire program must be loaded at once.
• preferred when programs rarely change

Internal Fragmentation

• Occurs when allocated memory exceeds the memory required by the process.
• Leads to unused space inside a block.
• Can be caused by paging if the allocated page size is larger than the process needs

External Fragmentation

• Occurs when variable-sized partitions leave gaps between allocated memory blocks that are too small to be used.
• Is reduced by paging.
• Also reduced by segmentation

Dynamic Loading

• Improves memory utilization by loading modules only when needed.
• Requires OS support.
• Loads program modules only when required, improving memory efficiency and reducing load time.
• Improves memory utilization.

Address Binding

• Can occur at compile time, load time, or execution time, depending on system requirements.
• Is static binding when done at compile time, where the logical addresses are directly mapped to physical addresses.
• Requires dynamic address translation, where logical addresses are converted to physical addresses during program execution.

Paging

• Eliminates external fragmentation by dividing memory into fixed-size frames.
• Divides both logical and physical memory into fixed-sized blocks (pages and frames).

Segmentation

• Provides reduction of external fragmentation is achieved by allocating RAM to processes non-continuously.
• Is prone to external fragmentation because segments are variable-sized, leading to gaps between allocated memory areas.
• Divides memory into variable-sized segments, each representing a logical division of a program.

Effective Address Calculation in Segmentation

• The offset from the segment table is added to the base address.

Non-Contiguous Memory Allocation minimizes external fragmentation

• By allowing processes to be allocated in different memory segments.

Number of Pages Required

• Calculated by dividing the process size by the frame size, with any remainder rounded up.

Page Table

• Maps logical pages generated by the CPU to physical frames in the main memory.
• A page table entry includes the frame number, protection bits, and other control bits, facilitating address translation and access control.
• In a two-level paging, the first-level page table holds pointers to secondary page tables.
• A valid bit shows whether the page is currently loaded in physical memory or resides on disk.

Translation Lookaside Buffer (TLB)

• Speeds up logical to physical address translation.
• Caches recently accessed page table entries to speed up address translation.
• High hit ratio decreases the Effective Access Time (EAT) as more address translations are completed by the faster TLB
• Improves performance by caching page table entries, reducing the need for frequent memory accesses during address translation.
• During a context switch, the TLB is flushed, and the page table may need updating, along with saving the process state
• Page table size is dependent on B. Number of pages in logical memory
• TLB miss penalty can be reduced by:Increasing the TLB size

Page Offset

• Specifies the exact location within a page when added to the frame base address.

Page Fault

• Occurs when the CPU fails to find the required page table entry in the TLB, necessitating a full page table lookup.
• Occurs when a process tries to access a page not currently in memory, triggering a load from the disk.
• Occurs when the requested page is not present in main memory, requiring it to be loaded from secondary storage.

Multi-Level Paging

• Reduces individual page table sizes.
• Increases overall access time due to multiple memory accesses.