IBM PC Systems, Memory Map, Real-mode CPU

IBM PC (AT) Systems, MSDOS Memory Map, and Real-mode CPU Operation

• This lesson aims to teach the significance of IBM PCs in modern microprocessor-based systems.
• This lesson aims to identify the supporting components of IBM PCs and their functions.
• This lesson aims to describe the internal programming model of the CPU registers, and demonstrate how addresses can be accessed in each memory space.

MPU-Based Systems

• Newer chips are fundamentally based on the old Intel 8088 CPU, with significant modifications.
• Newer PCs are designed to be fully backward compatible with the old 1979 IBM design from a software perspective.
• Key components include the Memory System, Microprocessor, and I/O System.

Overview on IBM PC System

• The original IBM PC was a complex and advanced computer system.
• Additions to the CPU, contain other support chips for required functionality.
• There are three main communications paths in the computer system: memory bus, local I/O bus, and I/O bus for slower devices.
• Memory is divided into functional components like screen memory and operating system space.

Bus Configuration of IBM PC System

• The CPU uses three sets of wires called buses to communicate with components: address bus, data bus, and control bus.
• The Address Bus selects addresses in primary memory or I/O locations. Originally 20 bits were used, then 32-bit buses were introduced.
• The Data Bus is employed by the CPU to read / store values once a memory / I/O location is addressed.
• The Control Bus sends control signals to components (e.g., select between primary memory/I/O) and is used by support chips to interrupt the CPU.
• Various buses are accessed by support chips like DMA or interrupt controllers when not in use by the CPU.

Co-Processor & Support Chips

• The original IBM PC included the Intel 8088 CPU, 8087 math co-processor, 8284 clock generator, 8253 programmable timer, 8255 programmable peripheral interface (PPI), 8259 programmable interrupt controller (PIC), and 8237A direct memory access controller (DMAC).
• In modern PCs, many original support chips are replaced by more integrated chips that provide the same or greater functionality.

Co-Processor & Support Chips – Central Processing Unit (CPU)

• The CPU is the computer's brain, executing instructions and controlling support chips.
• In the original IBM PC, the CPU was an Intel 8088 running at 4.77 MHz (4×1.19 MHz).
• Intel CPU has progressed to today's i-series processors with clock speeds up to 2GHz and beyond.
• 80386 CPUs and above have a special "386 enhanced mode" that operates differently but remains compatible with 8088 programs.
• Every CPU contains registers, ALU (Arithmetic Logic Unit), shifters and rotators, and an address decoder.
• Newer CPUs have embedded cache memory and integrate math co-processors and advanced components like the MMX engine.

Co-Processor & Support Chips – Math Co-processor

• It is a specialized chip designed to execute floating point instructions.
• Utilizes a stack processor system, where operations are performed on the last two items put onto the stack.
• It employs a unique set of CPU instructions distinguished by an 'f' prefix.
• The co-processor executes advanced calculations such as sin, cos, tan, and log.
• Useful for 3D modeling, decoding multimedia images, and computer games.

Co-Processor & Support Chips – Direct Memory Access (DMA)

• It is used to transfer data to and from primary memory without CPU intervention.
• Employed for various tasks like loading/saving programs and data files to internal storage or loading sound data onto a sound card.
• It is capable of transferring data at notably higher rates than the CPU.
• The CPU can handle other processing during these memory transfers.
• Increases system performance.

Co-Processor & Support Chips – Clock Generator

• It synchronizes all system components.
• Utilized by the keyboard, DOS, BIOS, timers, and other components.
• Generates specifically, a 1.19 MHz clock signal (¼ of the original 8088 oscillator frequency).
• Used to maintain the time of day and generate sound waves from the internal speaker or tone tape drives.
• The fixed 1.19 MHz signal assures time-driven software runs at the same speed across machines, regardless of the CPU speed.
• Intel CPU speeds have increased from 4.77 MHz to 2.0+ GHz.

Co-Processor & Support Chips - Programmable Timer

• It generates accurate timed signals.
• The Programmable Timer contains 3 independent 16-bit channels, each with up to six modes of operation.
• Each channel can be programmed to operate up to 1.19 MHz.
• Channel 0 pulses 18.2 times a second, used by BIOS to maintain the time of day.
• Channel 1 produces pulses every 55 microseconds for dynamic random access memory (DRAM) refresh.
• Channel 2 is available for user, to create sound waves or signals for older tape storage.

Co-Processor & Support Chips – Programmable Peripheral Interface (PPI)

• The PPI is used to access certain devices in original IBM PCs.
• This chip commonly utilizes three main ports: A, B, and C.
• Port A is an input port that receives 8-bit codes from the keyboard.
• Port B is the output, and enables the speaker, Channel 2 of the timer or to a cassette tape.
• Port C is the input, used to set the amount of Random Access Memory (RAM) on the system.

Co-Processor & Support Chips - Programmable Interrupt Controller (PIC)

• It is another support chip, used to control up to 8 hardware interrupts.
• IBM XT PC systems had one, while AT and ATX PC systems have two.
• BIOS is used to program this device to carry out functions such as: enabling/disabling device interrupts.
• BIOS is used to program Arrange a priority system relating to each interrupt signal.
• BIOS is used to Store the position of the address vector in the interrupt vector table (IVT) relating to that particular interrupt.

Co-Processor & Support Chips – Keyboard Interface

• The keyboard acts as a link between the keyboard, and the CPU / software program.
• It receives an 8-bit serial code whenever a key is pressed or released.
• It converts this into an 8-bit parallel scan code and sends this to the PPI.
• It generates a hardware interrupt through the PIC to tell the CPU that a key has been pressed or released.

Co-Processor & Support Chips – Serial Interface

• It provides an RS232C interface.
• Used to send and receive serial data to and from external systems.
• It is also used to communicate directly with other computer systems.
• Used to interface with modems for distant communications.
• It is used as an input for a serial mouse or any other serial based peripheral.

Co-Processor & Support Chips – Video Adaptor/Interface

• The Video Adaptor controls output to a video display unit (VDU).
• It is connected to both primary memory and I/O memory.
• Screen modes include:
• MDA – Monochrome Display Adapter (2 Colors)
• CGA – Colored Display Adapter (4 Colors)
• EGA – Extended Graphics Adapter (8 Colors)
• VGA – Video Graphics Array (16 Colors)
• SVGA – Super Video Graphics Array (32 Colors)
• XGA – Extended Graphics Array (1M Colors)
• UXGA – Ultra Extended Graphics Array (16M Colors)

Co-Processor & Support Chips – Disk Drive Adaptor

• The Disk Drive Adaptor controls storage devices.
• It generally includes the Floppy drive interface, IDE, SCSI (for hard drives), ATAPI (newer PC), SATA (newer PC), and Zip drives.

Co-Processor & Support Chips – Printer Interface

• It provides an 8-bit parallel interface for printers.
• It sends data to the printer, reads its status, and controls printer operations.
• The interface can also be used with Zip drives, scanners, and other peripherals.

Co-Processor & Support Chips – Real-Time Clock

• It maintains the date and time even when the computer is switched off.
• It maintains system configuration information.
• A Motorola 6818 CMOS chip is used.
• It is powered by a battery.

MSDOS Memory Map

• IVT
• BIOS DATA
• DOS DATA
• RESIDENT DOS
• USER SPACE
• TRANSIENT DOS
• VIDEO RAM
• EXTENSION SPACE
• USER SPACE
• BASIC PROGRAM
• BIOS

IVT (Interrupt Vector Table)

• Contains 256 20-bit addresses
• Each address points to a hardware or software interrupt service routine (ISR)
• Used by USER, BIOS and DOS (MSDOS, BASIC)

BIOS Data

• Used by BIOS for its temporary space.
• BIOS is ROM based and data cannot be written in ROM.
• Information such as keyboard queue, screen mode and other temporary variables are stored here

DOS DATA

• Used by DOS to store temporary information like current file-name, directory name, etc.
• Very similar in operation to the BIOS data work space

Resident DOS

• Contains DOS commands like COPY, DIR, CD, MD, DEL, REN etc.
• Contains approximately 200 high level segments of code that manage the system.
• This code remains in memory while the machine is switched on.

User Memory Space

• About 500 KB of RAM in total, available for use by a user.
• Each program has CS, DS, SS and ES segments within the user space.
• Also includes a 256 byte area for passing system level parameters called Program Segment Prefix (PSP).

Transient DOS

• Used by DOS programs that is less frequently called.
• Usually reserved for these programs are format, print, chkdsk, scandsk, etc.

Screen (Video) RAM

• Primary memory set aside for use by the video display adaptor.
• Video RAM is physically located on the video adaptor but is mapped into primary memory.
• The full mapping of mono and CGA into RAM can be supported.
• Supports EGA, VGA, XGA, or UXGA by swapping blocks of memory between the display adaptor and primary memory.

Extension ROM Space

• Used for additional hardware devices.
• Provides space where routines can be supplied to initialize and control “unknown” hardware (any new device).

User ROM Space

• It is memory provided for users to install any ROM programs they would like.

BASIC ROM Space

• Early IBM PCs had a BASIC boot up.
• If a DOS system was not found on any drive, this ROM was invoked.

BIOS Space

• It is the space that is basic I/O system (BIOS) memory.
• They are used in routines to check the system hardware during "boot up" and by programs that load DOS system files.
• BIOS helps perform various functions through service routines, typically delivered via service interrupts; these can be used to control hardware directly (e.g., screen modes, disk access).
• It is Installed via ROM or flash chips that contains attached hardware information and initial drivers.

Internal Microprocessor Architecture

• Before a program is written or any instruction examined, the internal configuration of the microprocessor must be known.
• The Programming model of the 8086 throughout the Core 2 is considered program visible, because its registers are used during programming and specified by the instructions.
• Registers are not addressable directly during applications programming but may be used indirectly during system programming (operating system (OS)) are considered program invisible.
• Figure 1a and Figure 1b illustrate the programming model of the Intel 8086 through the Core 2 microprocessor.
• Some registers are general-purpose or multipurpose registers, while some have special purposes.

CPU Registers

• Registers hold various data sizes (bytes, words, double words, or quad words) and are used for almost any purpose as dictated by a program.
• Registers are classified into:
• Multi- or General-purpose registers
• Special-purpose registers
• Segment registers

Multi- or General-purpose Registers

• RAX (accumulator): It is referenced as a 64-bit register (RAX), a 32-bit register (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL).
• RBX(base index): RBX is addressable as RBX, EBX, BX, BH, or BL.
• RCX (count): RCX is addressable as RCX, ECX, CX, CH, or CL, is a general-purpose register that also holds the count for various instructions.
• RDX (data): RDX, which is addressable as RDX, EDX, DX, DH, or DL, is a general-purpose register that holds a part of the result from a multiplication or part of the dividend before a division.
• These registers are only found in the Pentium 4 and Core2 if 64-bit extensions are enabled: R8 through R15.
• These registers are only found in the Pentium 4 and Core2 if 64-bit extensions are enabled: RBP, RDI, RI

Special-Purpose Registers

• Special-purpose registers include the Instruction pointer (RIP, EIP, or IP), Stack pointer (RSP, ESP, or SP), and Status or flag registers (RFLAGS, EFLAG, or FLAG).
• RIP addresses the next instruction in a section of memory defined as a code segment.
• RSP addresses an area of memory called the stack, and stores data through this pointer.

Special-Purpose Registers – RFLAGS/EFLAGS/FLAGS

• These registers indicate the condition of the microprocessor and control its operation.
• Flags are upward-compatible from the 8086/8088 through the Core2 microprocessors.
• The 8086–80286 contain a FLAG register (16 bits).
• 80386 and above contain a EFLAG register (32-bit extended flag register).
• The 64-bit RFLAGS contain the EFLAG register, which is unchanged in the 64-bit version.
• The rightmost five flag bits and the overflow flag change after arithmetic and logic instructions execute.
• The flags never change for any data transfer or program control operation.
• Some of the flags are also used to control features found in the microprocessor.

Additional Info on the flag registers

• Carry Flag (C): Holds the carry after addition or the borrow after subtraction.
• Parity Flag (P): A logic 0 for odd parity and a logic 1 for even parity.
• Auxiliary Carry Flag (A): Holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result.
• Zero Flag (Z): Shows that the result of an arithmetic or logic operation is zero. If Z = 1, the result is zero; if Z = 0, the result is not zero.
• Sign Flag (S): Holds the arithmetic sign of the result after an arithmetic or logic instruction executes.

Segment Registers

• Used to generate memory addresses when combined with other registers in the microprocessor.
• There are either four or six segment registers in various versions of the microprocessor.
• A segment register functions differently in the real mode when compared to the protected mode operation of the microprocessor.
• In the 64-bit flat model, segment registers have little use in a program except for the code segment register

Specific Segment Registers

• CS (code): The code segment is a section of memory that holds the code (programs and procedures) used by the microprocessor.
• DS (data): The data segment is a section of memory that contains most data used by a program.
• ES (extra): The extra segment is an additional data segment that is used by some of the string instructions to hold destination data.
• SS (stack): The stack segment defines the area of memory used for the stack.
• FS and GS: Segments are supplemental segment registers available in the 80386–Core2 microprocessors to allow two additional memory segments for access by programs.

Real-mode Memory Addressing

• Real Mode operation allows the microprocessor to address only the first 1MB of memory space, even with the Pentium microprocessor.
• The first 1M byte of memory is called either the real memory or conventional memory system.
• Real mode operation allows application software written for the 8088/8086, which contain only 1M byte of memory, to function in the 80286 and above without changing the software.
• Each of these microprocessors begins operation in the real mode by default whenever power is applied or the microprocessor is Reset.

Segments and Offsets

• Combination of a segment address (SA) and an offset address (OA) access a memory location in the real-mode called segmentation mechanism.
• The A 20-bit real mode address allows one to access the start of a segment at any 16-byte boundary within the first 1MB of memory.
• Any real mode segments can only begin at a 16-byte boundary in the memory system, called a paragraph.
• In the 80286 and later a 64 KB minus 16 bytes of memory is addressable when the segment address is FFFFh, and the himem.sys driver is installed in the system, called high memory (himem)

Default Segment and Offset Registers

• Microprocessors have a set of rules that apply to segments whenever memory is addressed.
• These rules define the segment register and offset register combination used by certain addressing modes.
• When generating the next instruction address (NIA), the code segment (CS) register defines the start of the memory space of the code, and the instruction pointer (IP) locates the next instruction within the code segment.
• In stack data memory addresses, it is reference through the stack segment (SS) at the memory location addressed by either the stack pointer (SP/ESP) or base pointer (BP/EBP).
• A program can have many segments, but can only access four (in 8086-80286) or six (in 80386 and above) segments at a time

Relocation Issues

• Segment and Offset addressing scheme allows relocation
• Relocatable program - program that can be placed into any area of memory and executed without change
• Relocatable data - data that can be placed in any area of memory and used without any change to the program