Gate-to-GDS Flow Overview

• Book copyright is 2007 by Lee Eng Han
• Reproduction of this book is prohibited without the author's written consent
• Contact Eng Han at [email protected] for reproduction permissions
• More information about this book can be found at www.eda-utilities.com

Gate-to-GDS flow

• This chapter presents a high-level overview of the Gate-to-GDS flow to bootstrap the reader into digital layout design and is recommended for those with no prior experience in Place and Route (P&R).
• The flow details are addressed in subsequent chapters
• P&R experienced readers may find this chapter useful to familiarize themselves with the technical aspects covered in the book

Key steps of a Gate to Layout flow:

• Load library
• Import gate netlist
• Specify design constraints
• Floor planning
• Power planning
• Physical synthesis
• Clock tree synthesis
• Routing
• Physical verification
• Post-layout verification

P&R projects execution

• Steps are not necessarily executed in the order listed
• Physical verification (step 9) of the pad ring is done possible during floor planning (step 4)
• Physical synthesis (step 6) can be used to assess floor plan feasibility (step 4) without power planning (step 5)
• Physical synthesis (step 6) and clock tree synthesis (step 7) are sometimes performed concurrently

Project requirements

• Not every step is necessary for every P&R project
• Logic design requirements and fabrication process technology determine which steps can be omitted or added
• Clock tree synthesis may not be needed at 0.6um process technology
• Crosstalk noise violation analysis and fixing is essential for layouts using 0.18um or smaller process technology

Load Library

• A P&R library contains:
  • Technology library
  • Cell library

Technology Library

• Wires must satisfy layout design rules
• The timer engine needs parasitic capacitances and resistances information for
  • Static timing analysis
  • Crosstalk analysis
  • Power analysis

Cell library contents

• Cell type (combinational, sequential, pad, timing model, etc.)
• Pin-to-Pin delay
• Slew for output pin
• Capacitive loading on input pin
• Leakage and dynamic power consumption
• Design rule (maximum input slew for input pins and maximum load for output pins)
• Maximum allowable noise for input pins, and holding resistance for output pins

Cell library information types

• Logical
• Physical
• Physical information is stored as a simplified layout version - "abstract"

An abstract must contain

• Cell name
• Cell size
• Allowable orientation
• Pin names and their layout geometries
• Routing blockages
• Process antenna areas for the pins
• Power and ground pins must be included in the abstract library

Layout Exchange Format (LEF)

• A popular format for abstract libraries
• Supports both technology and cell libraries
• Mandatory to load the technology library before the Cell library
• The technology defines the metal and via layers

Cell libraries exist in three types

• Standard cell library
• Pad cell library
• Macro library
• Standard cells must be placed in the "core" and on the "cell row"
• Pads and macros aren't restricted to the core and can be placed anywhere
• Pads are commonly placed on the layout peripherals
• Specific P&R tools can automate pad placement

Import Gate Netlist

• Verilog is the most popular gate-level netlist format, preferred by most P&R tools
• VHDL gate-level netlists are an alternative
• Logic gates in the design bind to their cell master in their libraries
• It is necessary to consider cases where cells from different libraries share a name

Cell/instance definitions

• Cell library is a collection of cells
• Standard cell refers to a logic gate
• I/O cells are usually I/O pads
• Hard macros refer to the layout of the IP
• IP without a layout is a soft macro
• An instance refers to a cell in the design
• “Instantiating the cell AND2D1 to the design” is more common term than "adding the cell AND2D1 to the design"
• Every instance in the same design hierarchy must have a unique instance name

Power/ground connections

• Global nets and wildcards are used by all P&R tools to define power and ground connections
• Design Exchange Format (DEF) statements are used to create two new nets named VDD and VSS
• Pins with the name "vdd" connect to the VDD net, and the pins with the name "vss" connect to the VSS net
• The * in the commands is a wildcard that matches an instance name

Define the power supply

• Sufficient with two commands if VDD and VSS are the design's only power nets, and all power pins of the cell instances are named "vdd" and "vss"
• Tie-high and tie-low refer to the connection of the input pins to the power supply
• Tie-high and tie-low are represented as 1'b1 and 1'b0 in the Verilog netlist
• Physically, tie-high and tie-low nets are connected by:
  • Directly to the power/ground nets
  • Tie-high and tie-low cells
• The pad/standard cell library design determines the type of connection

Instance naming

• Designs can have many layers of hierarchy
• Design name is the same as the top-level design hierarchy name
• Instantiation can be a cell or a sub-hierarchy

Netlists

• Can instantiate the same sub-hierarchy several times
• The sub-hierarchy must be "uniquified" to allow layout to be implemented differently for each instance
• Uniquification duplicates the sub-hierarchy with different hierarchy cell names while preserving instance names

Instance reference

• Full hierarchical name is required to refer to a particular instance
• Instance names remain unchanged after applying uniquification

Specify Design Constraint

• P&R is a constraint-driven process.
• P&R optimization is purely congestion-driven in the absence of constraints
• Timing constraints are an important part of the design constraint
• Timing constraints specify design timing goals
• Necessary for time-driven placement and/ or physical synthesis
• Timing constraints are likely specified in SDC format

Timing constraints

• Should be specified in the top-level design
• Necessary a complete top-level timing constraint for a timing-driven flow
• Unconstrained timing paths are not optimized for timing performance
• Logics that are slow or with large slew, typically implement unconstrained paths

Timing requirements

• Over-constraining the timing requirement is undesirable
• An over constrained design increases area size resulting in longer runtime

Non-timing constraints

• Constraints unrelated to timing performance
• No standardized naming convention- "non-timing constraints" is used

Types of non-timing constraints

• Design rules, including maximum fan-out, maximum slew, and maximum capacitance loading
• Scan-chain re-ordering and re-partitioning
• Selective hierarchy flattening
• Buffering of inputs and outputs with user-specified cells
• Identification of cells that the tool can/cannot modify or resize
• Identification of nets that must be preserved during logic optimization
• Disallowing certain cells
• Assigning higher priority to achieve shorter wiring length
• Restriction in the area that certain cells can be placed
• Among others

Non-timing constraints can be used to

• Ensure the physical implementation meets the design requirements
• Improve layout quality
• Turn-around time
• To work-around the limitations of the P&R tools

Floor Planning

• The first step of physical layout implementation
• A floor plan should include the following decisions:
  • Size of the layout
  • Core area
  • Placement of I/O pads and I/O pins
  • Placement of hard macros

Standard layout

• A floor plan should include the placement of all the pads (or pins) and the hard macros
• Standard cells are not placed yet and no routing is performed at this stage

Layout planning

• Defining the layout's outline is the first step
• If the layout is rectangular, only the length and the width are required
• More co-ordinates are required to define the outline of a rectilinear layout, such as an L-shape layout
• P&R tools do not typically alter the size of the layout specified by the user

Floor planning area

• Defined by specifying the distance between the edge of the layout and the core

All standard cells requirement

• Must be placed in the core area
• Placement not restricted for I/O pads and macros - commonly placed in the core
• The area outside the core is used to place the I/O pads, the I/O pins, and the core power rings

Standard cell placement

• Placed in rows inside the core area
• Placed similar to books on a shelf - "cell rows"
• Cell rows have the same height
• Three common cell row arrangements exist

Cell row arrangement

• The most common approach for layout with more than three metal layers to flip every other cell row which does not leave a gap between the cell rows.
• The second configuration is to flip every other cell row, but leave a gap between every two cell rows. The purpose of the gaps is to allocate more resources for the inter-connect routings.
• The last configuration is to leave a gap between every cell row, and not flip the cell rows. This configuration is useful when only two or three metal layers are available for routing

Cell row orientation

• It is denoted by "slanting lines" on the right of the cell rows
• Modern P&R tools fill the core area automatically adjusting cell rows
• Certain P&R tools require the user to specify the areas in the core where the cell-row should be created

Power domain

• Only one core area needed, if all standard cells are in the same power domain
• In a multiple core power P&R flow, more than one core area must be defined
• Every core area must associate with a power domain

Chip-level layout

• The next step is to place the IO pads for chip-level layouts only
• Pad filler cells and corner cells can fill the gaps between the pads
• Block-level layouts required the user to define the location and geometries (size and metal layer) of every IO pin

Macro placement

• Macro placement is the next step when the design contains hard macros
• A good macro placement has the following qualities:
  • Compact layout
  • No routing congestion
  • Does not make timing closure difficult
  • Allows robust power routing between the power pads and the macros
• Assessing floor plan quality is the biggest challenge in placing the macros
• Floor planning is iterative and time consuming
• The trick in performing floor planning is to shorten the turn-around time of the iterations, and to reduce the number of iterations

Power Planning

• Power and ground nets connections are routed during power planning
• The exception is tie-high and tie-low nets
• Dedicated routers connect power nets in modern P&R tools
• Power routings created by the power router are considered pre-routes, and are not modified by the detailed router during signal routings

Key power planning considerations

• An acceptable IR-drop from the power pads to all power pins
• Meeting electro-migration requirements
• No routing congestion
• Compact layout

Power structure planning

• Core power rings are routed first
• Core power pads are connected to the core power rings
• Power rings are added around the macros where necessary
• Vertical and horizontal stripes are added to reduce the IR-drop at the power rails of the standard cells and the macros
• The power pins of the hard macros are tapped to the core rings or the power stripes
• Tie-high and tie-low inputs to the hard macros and IO pads are tapped to the power structures, if tie-high and tie-low cells aren’t used
• The power rails for the standard cell are added to the power plan
• The cell power rails can tap the power from the:
  • Core power rings
  • Power stripes
  • Macro power rings

Physical Synthesis

• Placement of standard cells and the optimization of the layout based on design constraints

Physical synthesis typical phases

• Global placement
• Global routing
• Physical optimization
• Detailed placement
• Further physical optimization
• Standard cells get placed on the cell rows (after physical synthesis)
• Placement needs to be legalized- standard cells must be:
  • On the cell row
  • On the placement grid
  • Non-overlapping
• Power pins must be properly connected

Optimized netlist

• A tool might need to optimize to meet timing goals
• Different tools have different capabilities
• Users can configure the optimization type the tool can utilize

Optimization techniques

• Gate sizing
• Buffer insertion and removal
• Pin swapping
• Cloning
• Logic restructuring
• Architecture retargeting

Modern Integrated Circuit (IC) Optimization

• Physical synthesis becomes essential when the IC industry started to adopt process technologies that are 0.25um and smaller
• For Process Technology 0.6um and larger, Placement is congestion driven, Manual insertion of buffers to long nets after routing
• Process Technology 0.35um, Placement is timing driven, Physical optimization is restricted to gate sizing and buffer insertion
• Process Technology 0.25um and smaller, Physical synthesis is fully adopted

Clock Networks

• Most P&R flows will not attempt to restructure the logic in the clock network
• Certain P&R tools can size the cells in the clock network during physical synthesis

Interconnect

• Global routing is performed during physical synthesis to estimate inter-connect parasitics well
• Detailed routing assumption- matches global routing closely Physical synthesis optimizes to meet the real critical paths

Congestion

• The routing congestion map is derived from global routing
• Any routing congestion should be resolved by:
  • Reiterate placement with additional controls
  • Improve the floor plan and power plan
• Before layout design, the layout is ready to perform IR-drop analysis to:
  • Ensure all power pins of the hard macros and the standard cells are connected to the power structures
  • Ensure voltage drops in the power structures are within acceptable limit

Clock Tree Synthesis

• Clock nets are buffered following the placement of all standard cells

High fan-out non-clock nets for synthesizing clock trees

• Clock latency
• Clock skew
• Restriction on the type of buffer and inverter the clock tree can use
• Stricter signal slew requirements on the clock nets

Timing delays

• Clock latency is the delay of the clock signal from the clock source to the clock pin
• Clock skew is the difference between clock latencies and the two clock pins

Routing

• Detailed routing" is the process of routing the non-power signals
• Empty space exists in the cell rows after clock tree synthesis
• These empty spaces between the standard cells are filled by filler cells
• Filler cells can be inserted before or after detailed routing

Filler cells with metal routing

• The fillers should be inserted before routing if they contain metal routing other than the power rail
• Insert after routing if it is better

Detailed and Global routing

• Routing is performed throughout P&R flow
• Powers are routed during power planning by a dedicated router
• Signal nets are "globally routed" during physical synthesis using the global router- global routes
• Global routes allow the P&R tool to resolve routing congestion and estimate the routing parasitics
• The clock trunks are routed with actual metal geometries after clock trees are synthesized before they are re-optimized
• Followed by detailed routing

Detailed routing stages

• Track routing: Global routing uses a very coarse routing grid, Track routing assigns the global routes to real routing tracks
• Detailed routing with only metal one: Connections between cells that are placed side-by-side
• Connecting the rest of the signal nets by following the result of track routing- Connect the routings to eliminate "Open" routing resulting in short or design rule violations (ex: metal spacing violations).
• Resolve routing violations iteratively- divide the layout into regions and clean up the routing violations, repeat while adjusting sizes and aspect ratios ending when limit reached on number of iterations.
• Iterating between fixing antenna violations and cleaning up routing violations- Fixing introduced new routing violations
• Optimizing the detailed routes- the types of optimization to be performed will depend on the user's specifications and the tool's capability, including minimizing wire jog and switching of routing layers, or even out the spacing between the routes, and replacing single via with redundant via

Physical Verification

• Checks the layout after routing the design
• P&R tools perform cell-level DRC and LVS on routed designs - mandatory to perform a full-layer (or sometimes called full-GDS) physical verification

Types of physical verification

• Design Rule Check (DRC)
• Layout Versus Schematic (LVS)
• Electrical Rule Check (ERC)

DRC

• Checks the layout geometries for the manufacturing process
• A full DRC deck contains hundreds of DRC rules

Common DRC rules

• Spacing between geometries
• Minimum and maximum width of the geometries
• Density of the metals, the poly and the diffusion
• Antenna violation
• Via reliability

LVS

• Checks the layout for correct connectivity between devices in the circuit

Circuit devices

• Transistor
• Resistor
• Capacitor
• Diode

The verification process

• Circuit devices and the inter-connections are extracted from the layout and saved as a layout netlist in spice format
• The layout netlist is compared with the post-layout design netlist - can exist in Verilog format

ERC

• Identifies errors in layout related to electrical connections

Electrical connections

• Latch-up protection
• Floating substrate
• Floating well
• Bad device connections
• ERC rules are typically embedded in the DRC and LVS rules

Post-Layout Verification

• Sign-off tools perform the final design check
• P&R tools utilize simplified models during parasitics extraction, static timing analysis, and other analyses due to run-time and memory usage considerations
• Requires sign-off tools

P&R tool parasitics extraction

• It should be within a few percentage points from a sign-off parasitics extraction tool result, on average
• Some nets can exhibit a large difference, of over 100%

Tool differences

• Static timing engine in the P&R tool and the sign-off static timing tool might show differences regarding:
  • Design constraints
  • Delay calculation
  • Tracing of the timing path
• The sign-off tools may find violations that were missed previously
• Essential to correlate the interpretation of the design constraints by the P&R tool and the sign-off tools early in the P&R project
• Design usually contains an over-constrain to avoid differences among the tools from concern

Parasitics storage

• Stored in SPEF or SPDF format
• Extracted parasitics must be back-annotated into the sign-off static timing analyzer (STA) tool
• STA performs delay calculations and verifies timing performance
• The STA tool generates a standard delay format (SDF) file for the logic simulator to simulate post-layout

Timing goal achieved

• If timing goal not achieved, an attempt to close the timing is initiated
• Typically to correct by manual gate sizing and buffer insertion
• Post-layout verification is repeated