Podcast
Questions and Answers
What component should be used to drive the CPU bus when implementing LC3 on an FPGA?
What component should be used to drive the CPU bus when implementing LC3 on an FPGA?
A multiplexer
In what relevant case will the synthesis tool utilize a physical tristate on the FPGA?
In what relevant case will the synthesis tool utilize a physical tristate on the FPGA?
When building a connection to external SRAM
Why do modern FPGAs not contain internal tristates?
Why do modern FPGAs not contain internal tristates?
Tristates result in floating signals inside the chip
What are the dimensions of the external SRAM on the DE2-115 board?
What are the dimensions of the external SRAM on the DE2-115 board?
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What are the SRAM UB/LB signals responsible for?
What are the SRAM UB/LB signals responsible for?
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What is an inherent challenge of implementing a design that uses the SRAM?
What is an inherent challenge of implementing a design that uses the SRAM?
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What is the access time for the external SRAM?
What is the access time for the external SRAM?
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How many cycles are needed to complete a read operation?
How many cycles are needed to complete a read operation?
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Test memory simulates SRAM perfectly, but not DRAM.
Test memory simulates SRAM perfectly, but not DRAM.
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Both read and write operations must be synchronized when dealing with external SRAM.
Both read and write operations must be synchronized when dealing with external SRAM.
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What are the 3 general steps in the LC3 instruction cycle?
What are the 3 general steps in the LC3 instruction cycle?
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What actions are expected to take place during the FETCH phase?
What actions are expected to take place during the FETCH phase?
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Study Notes
FPGA Implementation of LC3
- Use a multiplexer to drive the CPU bus on an FPGA, as it does not support internal tristate buffers.
- Synthesis tools will utilize a physical tristate for external SRAM connections.
Tristate Buffers in Modern FPGAs
- Modern FPGAs lack internal tristate buffers due to the potential for floating signals, which can negatively impact power consumption and reliability.
DE2-115 Board External SRAM
- The external SRAM on the DE2-115 board has dimensions of 1Mx16, equating to 2 Mbytes of storage.
- Upper Bit (UB) and Lower Bit (LB) signals control read operations in SRAM.
SRAM Characteristics
- Asynchronous nature of SRAM presents challenges during design implementation.
- Access time for external SRAM is specified at 10 nanoseconds.
- A read operation requires 2 cycles due to synchronization involving an internal flip-flop.
Memory Simulation
- Test memory can simulate SRAM reasonably well but does not replicate DRAM perfectly.
- Synchronization is required for both read and write operations with external SRAM.
LC3 Instruction Cycle
- The LC3 instruction cycle comprises three general steps: Fetch, Decode, and Execute.
- During the FETCH phase, the Memory Address Register (MAR) is involved in retrieving the instruction.
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Description
Explore the intricacies of implementing the LC3 CPU model on FPGAs, focusing on multiplexers and the handling of external SRAM connections. This quiz covers the characteristics, operational challenges, and simulation techniques related to SRAM in modern FPGA environments.