FPGA LC3 Implementation and SRAM Overview

Questions and Answers

What component should be used to drive the CPU bus when implementing LC3 on an FPGA?

A multiplexer

In what relevant case will the synthesis tool utilize a physical tristate on the FPGA?

When building a connection to external SRAM

Why do modern FPGAs not contain internal tristates?

Tristates result in floating signals inside the chip

What are the dimensions of the external SRAM on the DE2-115 board?

1Mx16 (2Mbyte) Signup and view all the answers

What are the SRAM UB/LB signals responsible for?

Upper Bit and Lower Bit control Signup and view all the answers

What is an inherent challenge of implementing a design that uses the SRAM?

The SRAM is asynchronous Signup and view all the answers

What is the access time for the external SRAM?

10ns Signup and view all the answers

How many cycles are needed to complete a read operation?

2 cycles Signup and view all the answers

Test memory simulates SRAM perfectly, but not DRAM.

False Signup and view all the answers

Both read and write operations must be synchronized when dealing with external SRAM.

True Signup and view all the answers

What are the 3 general steps in the LC3 instruction cycle?

Fetch, Decode, Execute Signup and view all the answers

What actions are expected to take place during the FETCH phase?

State 1) MAR Signup and view all the answers

Study Notes

FPGA Implementation of LC3

Use a multiplexer to drive the CPU bus on an FPGA, as it does not support internal tristate buffers.
Synthesis tools will utilize a physical tristate for external SRAM connections.

Tristate Buffers in Modern FPGAs

Modern FPGAs lack internal tristate buffers due to the potential for floating signals, which can negatively impact power consumption and reliability.

DE2-115 Board External SRAM

The external SRAM on the DE2-115 board has dimensions of 1Mx16, equating to 2 Mbytes of storage.
Upper Bit (UB) and Lower Bit (LB) signals control read operations in SRAM.

SRAM Characteristics

Asynchronous nature of SRAM presents challenges during design implementation.
Access time for external SRAM is specified at 10 nanoseconds.
A read operation requires 2 cycles due to synchronization involving an internal flip-flop.

Memory Simulation

Test memory can simulate SRAM reasonably well but does not replicate DRAM perfectly.
Synchronization is required for both read and write operations with external SRAM.

LC3 Instruction Cycle

The LC3 instruction cycle comprises three general steps: Fetch, Decode, and Execute.
During the FETCH phase, the Memory Address Register (MAR) is involved in retrieving the instruction.

Description

Explore the intricacies of implementing the LC3 CPU model on FPGAs, focusing on multiplexers and the handling of external SRAM connections. This quiz covers the characteristics, operational challenges, and simulation techniques related to SRAM in modern FPGA environments.