FPGA Fundamentals and Verilog Basics

FPGA Overview

• Field-Programmable Gate Array (FPGA) is a type of sequential programmable logic device
• FPGAs include both logic gates and flip-flops
• It's a VLSI (Very Large Scale Integration) circuit
• Programmable at the user's location
• A typical FPGA consists of millions of logic blocks surrounded by programmable I/O blocks
• These blocks are connected via programmable interconnections
• Logic blocks contain lookup tables
• Logic gates used in implementation
• Multiplexers
• Flip-flops

FPGA Design Flow

• Sequential steps to design and implement
• Initial Specifications of FPGA: high-level behavior descriptions
• Functional Design: high-level architecture, block diagrams of inputs/outputs, behavior descriptions 
• Synthesis: using logic synthesis processes (like K-maps or automated CAD tools) creating the gate-level connections
• Technology Mapping: choosing the appropriate technology to create implementation (e.g., 74HC family, 32nm CMOS ASIC) 
• Place and Route: designing the spatial relationships and minimizing interconnect length. Designing connections between components to minimize the chip area/board space required.
• Verification: assessing if the final design meets timing and power requirements
• Fabrication: implementing the design in different forms (ASIC, a programmable device, board-level, parts).

FPGA vs Microcontroller

• FPGAs are programmable on hardware level
• Microcontrollers are primarily software configurable.
• FPGAs are more power-consuming than microcontrollers
• Microcontrollers are suited for low-power applications (like battery-operated devices)
• FPGAs handle parallel inputs simultaneously
• Microcontrollers can only handle one line of code at a time.

HDL

• Hardware description language (HDL) is used for describing digital systems 
• Used to describe circuitry using text-based language
• Allows modelling of complex systems without needing circuit schematics
• Modern HDLS enable automated synthesis, converting functional descriptions into gate-level descriptions
• Verilog and VHDL are common types of HDLs

HDL Abstraction

• HDLs define multiple levels of abstraction
• The highest is system level
• HDLs designed to encompass modeling from system behavior down to material level.

Verilog Constructs - Vectors

• A one-dimensional array of elements, considered as a bus
• All net data types used to form vectors
• Syntax: [MSB_index:LSB_index] vector_name.
  e.g., wire [7:0] Sum;
• Syntax for accessing the vector: Sum[0], Sum[7:4]

Verilog Constructs- Arrays

• An array is a multi-dimensional array of elements, a similar structure to a vector
• To declare an array, need to define Element type , dimensions and array name. Syntax: <element_type> [MSB_index:LSB_index] array_name [array_start_index:array_end_index];

Verilog Constructs - Numbers

• Numbers entered into Verilog are treated as integers
• Verilog supports optional bit size and number sign
• Syntax for specifying the base of a number: <size_in_bits>'

Verilog Constructs - Module

• A Verilog design describes a single system within a single file. The filename usually ends with '.v'
• Modules include the interface of system (inputs/outputs), and the description of behavior.
• Modules often include instantiations of lower-level modules to model hierarchical designs.

Verilog Constructs - Parameters

• A parameter (or constant) is used for multiple times in an architecture
• The parameter can be used for variables in the architecture.

Verilog Constructs - Compiler Directives

• Provide extra information to simulation tools to interpret the Verilog model
• Placed before a module definition, preceded by `'
• e.g., timescale <unit>, <precision> , include ,`define <macro_name>

Verilog Operators - Arithmetic, shift, Relational

• Arithmetic operators: +,-,*,/,% , **
• Shift operators: >>, <<, >>>, <<<

Verilog Operators - Bitwise Reduction

• Bitwise operators:  ~, &,|, ^, ^ ,&
• Reduction operators: & (and), | (or), ^ (XOR), ~^ (~XOR) 

Verilog Operators - Concatenation and Replication

• Concatenation operator ({}) - combines small array elements to build large arrays
• Replication operator (n{}) - repeats the enclosed value 'n' times 

Verilog Operators - Conditional and Relational

• Verilog uses the operators : ===, !==, ==, !=
• Relational operators: > < >= <=

Modelling Concurrent Functionality and Structural Design

• Verilog's assign keyword for continuous signal assignments that define combinational logic
• Procedural blocks (always) can model both sequential (like finite state machines) and combinational logic.
• Procedural blocks can have begin...end and fork...join statement groups.

Verilog Constructs- Procedural Blocks

• always blocks: designed for modeling sequential or combinational behavior.
• initial blocks: executes only once at the start of simulation
• Procedural blocks contain statements like: if-else, case, loops, blocking and non-blocking assignments

Verilog Constructs - Blocking/Non-Blocking Assignments

• Blocking assignments (=) compute expressions in sequence from each statement; useful for combinational logic
• Non-blocking assignments (<=) compute expressions all at once, suitable for sequential logic

Verilog Constructs - Initial Block

• Executes once at the start of simulation
• Useful to set initial values in tests

Verilog Constructs - Always Block

• Executed repeatedly during simulation
• Responsive to sensor changes and assigns new values
• Used for modeling sequential and combinational circuits

IF statements

• Boolean expression is evaluated and matching branch statements are executed
• Latches might be inferred if outputs a combinational circuit block does not have assigned values for all input conditions.

Sequential Circuit Code

• Defining and using D-FFs
• Includes code example for a D flip-flop without asynchronous reset

Sequential Circuit Design & Hierarchy

• Combining lower-level subsystems using module definitions 

Software Tools

• CAD tools for implementing digital designs
• Vivado (Xilinx):  tool for implementing, testing, downloading, and debugging HDL designs

New Vivado Project

• Steps to creating a new Vivado project on a specific FPGA device
• This includes, specifying project name, directory, selecting the HDL language

Add Verilog Design Source

• Instructions on adding and creating new Verilog files for design source within the software environment.
• Create new files with name syntax .v. Add these files as a design source in the project.

Add Constraint File

• Instructions on creating a constraints file for a specific FPGA board
• Specify the I/O constraints, e.g., pins for inputs/outputs (switches, LEDs, buttons).

Program Basys 3 Board

• Connections and procedures to connect FPGA board to the computer.
• Utilizing the Hardware Manager tool for loading design onto a Basys 3 board.

Sample Projects

• List of projects that can be designed on a Basys 3 FPGA board using Verilog.

Projects Titles

• Titles of example projects that have functionality using various HDL methods.

Test bench

• Describing what a test bench is and its purpose

Sequential Circuit Testbench Code - JK FF

• Example Verilog code for a JK flip-flop test bench

References

• Listing academic and internet resources that have relevant FPGA and Verilog information.

This quiz covers essential concepts related to Field-Programmable Gate Arrays (FPGAs) and Verilog programming. Explore topics such as FPGA logic blocks, advantages over microcontrollers, and the significance of various Verilog operators. Test your knowledge on rapid prototyping and FPGA development workflows.