FET Polarity and MOS Physics

FET Polarity

• The polarity of a Field Effect Transistor (FET), whether n-channel or p-channel, relies on the polarity of its drain and source regions.
• In nFETs, the drain and source regions are labeled "n+" due to heavy doping.
• In pFETs, the source and drain regions are labeled "p+" and are embedded in an n-type well layer.
• PN junctions are employed to impede current flow between adjacent layers in FETs.

MOS Physics

• MOSFETs use applied voltage to move electrical current, specifically charge, from the source to the drain.
• For MOSFETs to conduct electrical current requires a conduction path, or channel.
• The drain current, IDn, is controlled by the voltage applied to the device.

Field Effect

• Silicon dioxide (SiO₂) functions as an insulator between the gate and the substrate in a MOS structure.
• Cox = εox / tox (F/cm²) which defines the relationship between oxide capacitance (Cox), oxide thickness (tox),
• εox = 3.9ε₀, where ε₀ = 8.854×10⁻¹⁴ F/cm.
• Field effect: The electric field induces charge into the semiconductor, allowing control over current flow via the gate voltage, VG.
• Qs = -CoxVG Coulombs/cm², determining the surface charge density.

Field Effect at Circuit Level

• At the circuit level, the threshold voltage (Vₜₕ) is obtained by applying Kirchhoff's Voltage Law (KVL).
• VG = Vox + Φs, defines the relationship between gate voltage (VG), voltage drop across the oxide layer (Vox), surface potential (Φs).
• The oxide voltage, Vox, is the voltage difference between gate voltage (VG) and surface potential (Φs)
• A potential decrease is the result of an oxide voltage decrease in electric potential inside the oxide.

Electric Fields of MOS

• Lorentz Law states an electric field exerts a force on a charged particle.
• F = Qparticle * E (6.5)
• positively charged holes: Fₕ = +qE (6.6)
• negatively charged electrons: Fₑ = -qE (6.7)
• bulk charge: QB = −√2qεSiNaΦs (6.8)
• Where εsi = 11.8ε₀
• The oxide voltage related to the bulk charge is QB = -CoxVox (6.9)
• For proper device operation, a depleted MOS structure cannot support the flow of electrical current.

Electric Fields of MOS (cont.)

• With VG < VT , the charge is considered immobile bulk charge, and QS = QB.
• With VG > VT, the charge consists of two distinct components, given as: QS = QB + Qe < 0 (6.10).
• Qe represents the electron charge layer, where electrons move laterally, forming a channel region.
• When VG = VT, then Qe = 0.
• When VG > VT, then Qe = -Cox(VG - VT) (6.11).

nFET Current-Voltage Equations: Dimensionless Quantity

• The aspect ratio (W/L), which is dimensionless, is used to specify the relative size of a transistor
• L = L' - ΔL and W = W' - ΔW, where L' and W' are drawn channel lengths and ΔL and ΔW are channel length and width reductions.
• Controlling the electron charge layer, Qₑ, can be achieved using the gate-source voltage, VGSn

nFET Current-Voltage Equations: Cutoff and Active Modes

• Cutoff mode: as Figure 6.10 (a), If VGSn <VTn then Qe = 0 and IDn = 0, acts like an open switch.
• Active mode: as Figure 6.10 (b), If VGSn >VTn then Qe ≠ 0 and IDn = F(VGSn, VDSn), acts like a closed switch

I-V Characteristics-nFET

• Three regions of operation for nFETs are cutoff, linear, and saturation.
• To achieve Saturation:
  • VGS > VTn, VDS ≥ VGS - VTn
  • ID = 1/2 βn (VGS - VTn)²
  • ID = 1/2 βn (VGS - VTn) [1 + λ(VDS - Vsat)] is channel-length modulation

nFET Current-Voltage Equations: Derivation

• The current equation comes from the channel region using charge density QₑC/cm² applied by gate-source voltage 𝑉GSn>𝑉Tn.

nFET Current-Voltage Equations: Channel Equation

• The drain current (IDn) is obtained by evaluating a channel segment with length dy
• As current (IDn) flows through the segment, a voltage drop (dV) occurs, where dR represents differential resistance

nFET Current-Voltage Equations: Electromagnetics

• Following Electromagnetic Theory yields: E(y) = −dV/dy, where V(0) = 0 and V(L) = VDS .
• Channel voltage affects charge in the channel altering Qe, which becomes a function of coordinate y, the equation is Qe(y) = -Cox[VGS - VTn - V(y)].
• The channel has a minimum value on the drain given as Qe(L) = -Cox[VGS - VTn - VDSn]

nFET Current-Voltage Equations: Maximum Charge

• Maximum charge density is found at the source,
• Determined with the equation Qe(0) = -Cox[VGS - VTn].
• The functional dependence Qₑ(y) means the charge density distribution is non-uniform.
• Non-linear charge density implies the I-V relationship is non-linear.

nFET Current-Voltage Equations: Equations

• Channel charge density:
  • Qe = -qnexe
• Resulting differential voltage equation:
  • dV = IDdy / μnWCox(VGS−VTn−V)
• Further resulting current Equation:
  • ID = μnCox * W/L [(VGS - VTn)VDs - ½ VDs²]

nFET Current-Voltage Equations: Equations (cont.)

• Process transconductance parameter:
  • k'n = µnCox
• Device transconductance parameter formula:
  • βn = k'n (W/L)
• Final drain current equation: ID = (k'n * W/L) * [(VGS - VTn)VDS - ½ VDS²] ID = βn [2(VGS - VTn)VDS - VDS²]

nFET Current-Voltage Equations: Region Current

• Active region current as a function of voltage between the gate and source, VGSn, and drain-source voltage, VDSn:
  • IDn = B/2 * [2(VGSn - VTn)VDSn - VDSn²]
• Derivative of current with respect to voltage (VDSn) results in the saturation voltage:
  • If d/dV DSn=0, the saturation voltage is Vsat Vsat =VGSn - Vu IDn = β/2 *(VGSn - VT)² IDn=β/2 *Vsat²

I-V Characteristics-nFET Summary

• The three regions of operation for an nFET are Cutoff, Active, and Saturation. -VGS V₁, no current I, where =1.45 x 10¹º 𝑐𝑚⁻³ represents intrinsic semiconductor effects. -Calculate the value of the body bias coefficient. -In problem 3c when the voltage V₃ₒ is 3V calculate the new bias current. -A CMOS gate oxide process of thickness t is 100A", where the carrier mobility's are Mn" of 550cm²/V-s; Mp" of 210Cm²/V-s. Calculate the oxide capacitance for this problem.
• The dimensionless quantity (W/L) is the aspect ratio that is used to specify the relative size of a transistor with respect to others.
• The equation of IDn can be obtained by taking a differential channel segment that has a length dy as shown. Source (S) - Gate (G) Drain (D) Oxide (SiO₂) Metal (thickness = fox) Channel region L p-type substrate (Body) VGS, VT VD' For VG > VT, MOSFETs conduct electrical current by using an applied voltage to move charge from the source to drain of the device. . For VG < VT, we say the transistor is said to be in cutoff. . Silicon dioxide (SiO₂) acts as an insulator between the gate and substrate. Field Effect.
• Lorentzs law: an electric field exerts a force on a charged particle F = Qparticle E
• Silicon: q, Ɛsi V_G > V_Tn and V_DG < V_GTn

FET RC Model

• In FETs, circuit specialists deal with the non-linearities found in devices
• In FETs, designers simplify linear models with digital logic architectures

FET RC Model (cont.)

• Rn varies with VDS
• a: Rn = 1/(Bn(VGs-VTn)
• b: Rn = 1/(Bn((VGs-VTn)-0.5Vds
  • c: Rn = 2VDs/ Bn/ (VGS - VTn)) For range 1-6, Rn = n(VDD-VTn)

FET RC Model: FET Capacitances – MOS and Junction Capacitance

• The switching speed of CMOS circuit determined by the capacitances through which C=C, where A is the area
• The value of the capacitance when equals to C and is nonlinear.

FET Capacitances – Junction Capacitance: Formula Application

• Applies formula for nFET
• Varies w/voltage C=C(V) -C= C_0/(1+VR/Q0) ^m, where C denotes capacitance -C=CjApn
• Φo = (kT/q) In [N_a N_d)/(ni)² ], where a and d represent zero, while i represents bias capacitance

FET RC Model: Calculations

• Calculating the pn junction capacitance is geometry of the pn junctions. Calculations include: -Zero bias (VR=0)
• Reverse (VR≠0), and (sidewall perimeter
• SW and BOT, which is the C=CSB=CDB

Construction of FET RC Model: Parasitics

• Parasitics cause resistance and capacitance of MOS -Parasitics follow these relationships C=CGS+CSB C=CGD+CDB It is important to note that 𝑅_𝑛 is, inversely proportional to capacitances (W/L) while capacitance increases with the channel width W

Numerical: RC Switch Model

• Construct the RC switch model for the FET layout with a power supply voltage 5V
• Drawn channel length = 0.5 micrometers w electrical channel length
• C+ =0.86µm², C+ 2 (0.05) = 0.4 A g = = 3 µm² the gate
  1=0.6µA/², C= µm
• 150 V =2.0 2 =2.7
• =101 ohm

Summary- nFET and pFET: Regions

• Considers the regions using N and PMOS
• VTn with the linear equation, the region that contains the drain
• n =1.22 VGS, VTp with (resistive) equation in summary

MOSFET Scaling: Why Scale

• Improve complex systems.
• Reduce the cost per Transistor and reduce the Size of System. -Achieve exponential growth of Transistors w/scale Predictions.

MOSFET Scaling: Key Facts

• W is inversely proportional to L' = Ls S>1 between 1.2 to 1.5. The transistor (W/L) increase with scale which increase performance and power over-all. Cox = Oxide capacitance-
• Constant: The scale reduces physical quantities with voltages scale.
  • L: Length in scaling (L') -VT0: Voltages
    • VTG/ VDS. Ɛo/ A
  • Full/ Physical Quantity and increase also the scaling voltages.
    • W/ L Tox XJ,