CPU Design and Microarchitecture

• Computer organization and architecture are related but distinct fields
• Computer architecture deals with the conceptual structure and functional behavior of a computer system
• Computer organization deals with the physical components and how they interconnect to realize the architecture

CPU Design

• CPU design involves defining the functional units, their interconnection, and their operation to execute instructions
• Key stages include instruction fetch, decode, execute, and write back
• CPUs are designed to execute instructions from an instruction set architecture (ISA) like x86, ARM, or RISC-V
• CPUs contain an arithmetic logic unit (ALU) that performs arithmetic and logical operations
• CPUs contain registers for storing data and addresses for quick access
• CPUs contain a control unit that manages the execution of instructions

Microarchitecture

• Microarchitecture is the implementation of the architecture
• It involves techniques to improve performance, power efficiency, and cost
• Instruction pipelining overlaps the execution of multiple instructions
• Branch prediction attempts to predict the outcome of branch instructions
• Caching stores frequently accessed data closer to the CPU
• Superscalar execution allows multiple instructions to be executed in parallel

Instruction Set Architecture (ISA)

• ISA defines the instructions a CPU can execute
• It includes the instruction format, addressing modes, and data types
• Common ISAs include x86, ARM, and RISC-V
• CISC (Complex Instruction Set Computing) ISAs have a large number of complex instructions (e.g., x86)
• RISC (Reduced Instruction Set Computing) ISAs have a smaller number of simpler instructions (e.g., ARM, RISC-V)

Pipelining

• Pipelining divides instruction execution into stages (fetch, decode, execute, write back)
• Each stage operates concurrently on different instructions
• Pipelining increases throughput but introduces hazards such as data hazards, control hazards, and structural hazards.
• Data hazards occur when an instruction depends on the result of a previous instruction
• Control hazards occur during branch instructions as the pipeline may fetch instructions from the wrong path
• Structural hazards occur when two instructions need the same resource at the same time

Branch Prediction

• Branch prediction attempts to predict the outcome of branch instructions (taken or not taken).
• Static branch prediction always predicts the same outcome (e.g., always not taken)
• Dynamic branch prediction uses past behavior to predict future outcomes

Caching

• Caching stores frequently accessed data closer to the CPU to reduce access latency
• Cache levels include L1, L2, and L3 caches, with L1 being the fastest and smallest
• Cache memory is typically made of SRAM, which is faster but more expensive than DRAM
• Cache replacement policies (LRU, FIFO) determine which data to evict when the cache is full

Superscalar Execution

• Superscalar execution allows multiple instructions to be executed in parallel
• It requires multiple execution units (ALUs, FPUs)
• Instructions are dispatched to available execution units if there are no dependencies

Memory Hierarchy

• Memory hierarchy consists of multiple levels of memory with different speeds and costs
• Registers are the fastest and most expensive
• Cache is faster and more expensive than main memory
• Main memory (DRAM) is faster and more expensive than secondary storage
• Secondary storage (disk, SSD) is the slowest and cheapest

Multicore Processors

• Multicore processors have multiple CPU cores on a single chip.
• Each core can execute instructions independently
• Multicore processors improve performance through parallel processing

GPU Architecture

• GPUs (Graphics Processing Units) are designed for parallel processing, especially for graphics and image processing
• GPUs have many cores, but each core is simpler than a CPU core
• GPUs excel at data-parallel tasks

Instruction Fetch Unit

• Fetches instructions from memory
• May include a branch predictor to predict the next instruction to fetch
• Often prefetches instructions to keep the pipeline full

Instruction Decode Unit

• Decodes the fetched instructions
• Identifies the opcode and operands
• May involve register renaming to avoid hazards

Execution Unit

• Executes the decoded instructions
• Contains functional units like ALU, FPU, load/store units
• May involve out-of-order execution

Memory Management Unit (MMU)

• Manages memory access and protection
• Translates virtual addresses to physical addresses
• Enforces memory access permissions

Control Unit

• Coordinates the activities of all other units
• Generates control signals to control data flow and execution

Interrupt Handling

• Interrupts are signals that cause the CPU to suspend its current execution and handle a specific event
• Interrupts can be generated by hardware or software
• The CPU saves the current state and jumps to an interrupt handler routine
• After handling the interrupt, the CPU restores the saved state and resumes execution

Power Consumption

• Power consumption is a major concern in CPU design
• Techniques to reduce power consumption include clock gating, voltage scaling, and power gating

Clock Gating

• Clock gating disables the clock signal to inactive units
• It reduces dynamic power consumption

Voltage Scaling

• Voltage scaling reduces the supply voltage to reduce power consumption
• But, it may also reduce the maximum clock frequency

Power Gating

• Power gating completely shuts off power to inactive units
• It reduces static power consumption