CPU Architecture Quiz

Microprocessor Architecture Overview

• The slides cover microprocessor architecture, specifically focusing on CISC (Complex Instruction Set Computer) general-purpose processors.
• The presenter, Horia Cucu, from the Speech & Dialogue Research Laboratory at the University Politehnica of Bucharest, details the Von Neumann architecture.
• The Von Neumann architecture, a fundamental computer design, emphasizes that both instructions and data are stored in the same memory space.

Microcomputer Block Diagram

• A diagram shows the CPU, memory, and I/O ports interconnected by buses:
  • Control Bus: Carries control signals (e.g., MEM-READ, MEM-WRITE, ACK).
  • Data Bus: Transmits data between components.
  • Address Bus: Specifies memory locations.
• The CPU executes instructions and controls the system.
• Memory stores data and instructions.
• I/O devices connect the microcomputer with the outside world.

Instruction Execution Example

• The CPU initially resets and begins execution from memory address 100h.
• The CPU sends the address (100h) via the address bus.
• The CPU requests data from memory (MEM-READ) via the control bus.
• Memory reads the data at address 100h and places the instruction on the data bus.
• Memory sends an acknowledgement (ACK) via the control bus.
• The CPU receives the instruction from the data bus.
• The CPU decodes the instruction (e.g., add 50h to the value at address 2000h).
• The CPU sends the address (2000h) to memory.
• Memory responds with the data at address 2000h (e.g., 85h).
• Memory sends an acknowledgement (ACK) to the CPU.
• The CPU reads the data from the data bus.
• The CPU adds 50h to 85h (result is D5h) and stores the result in a register.
• The CPU sends the address (2000h) and the new value (D5h) to memory (MEM-WRITE) to update the data.
• The CPU continues to the next instruction.

CPU Registers

• Registers are storage locations inside the CPU.
• Registers are implemented as synchronized bistables.
• They have the fastest access speed compared to other storage types.
• Different types of registers exist:
  • General purpose: used for various tasks.
  • Special purpose: dedicated to specific functions (e.g., data register (DR), address register (AR)).
  • Physical: physical hardware entities.
  • Logical: virtual registers.
  • User-accessible: accessible by programmers.
  • Non-user-accessible: not directly addressable by programmers.

General Purpose Registers (GPRs)

• GPRs are equally sized registers used to store temporary data (operands/results).
• They're user-accessible and implemented as physical or logical registers.
• Their size is equal to the internal data bus size.
• A larger number of GPRs generally leads to faster and more compact programs, and easier programming.

Special Purpose Registers

• Special purpose registers are used for specific tasks.
• Their sizes depend on their intended function.
• Some are user-accessible, others aren't.
• Examples include data registers (DR), address registers (AR), accumulators, status registers, instruction pointers (IP), and stack pointers (SP).

The Arithmetic and Logic Unit (ALU)

• The ALU is a digital circuit that performs arithmetic (addition, subtraction, etc.) and logical (AND, OR, XOR, etc.) operations.
• Inputs include data to be processed, and the operation type (from control unit).
• Results are stored in the accumulator or on the internal data bus. Status flags are updated after each operation.

The Status Register

• The status register (or flags register) holds bits representing the outcome of arithmetic and logic operations.
• Flag bits indicate conditions such as zero result, overflow, carry, parity, etc.

The Accumulator and Shift Register

• The accumulator is a special purpose register that stores one of the operands before an operation and the result afterward.
• Size is equivalent to general-purpose registers.
• It's user-accessible.
• The shift register performs shift and rotation operations, has double the size of general-purpose registers, and isn't user-accessible.

The Memory Addressing Control Unit (MACU)

• The MACU computes the physical memory address needed to access information.
• Input comes from internal data bus, and output (physical address) is placed in the address register.
• Functionality classifications include sequential and non-sequential addressing and data addressing methods (elemental, stack based, array based).

Sequential Instruction Addressing, Non-sequential Addressing, Elementary Data Addressing, Stack Addressing, Data Arrays Addressing

• Sequential addressing processes instructions in a linear order using the program counter.
• Non-sequential addressing includes jumps, loops, and subroutines. Jump addresses can be absolute (memory addresses) or relative (offsets from the current instruction).
• Elementary data addressing involves accessing data at specific memory locations. Absolute or relative offsets are used.
• Stack addressing uses a LIFO (Last-In, First-Out) structure accessed by a Stack Pointer (SP).
• Data arrays addressing involves accessing elements within arrays by adding offsets to the index register.

The Timing and Control Unit (TCU)

• The TCU fetches, decodes, and manages the execution of instructions and controls data flow.
• Its design can be hardwired or microprogrammed.
• Inputs to the TCU include instructions from the instruction register and internal control signals (e.g., status flags).
• Outputs are internal control signals for internal blocks and external control signals for external blocks.

The Instruction Register and Instruction Decoder

• The IR holds the instruction code being processed.
• Instruction decoding is accomplished by the instruction decoder, which converts instruction codes into control signals.

The Typical CISC Instruction Format

• Instructions are stored in memory locations and may be one or more bytes long.
• Instruction formats include an instruction code and other information to be processed.

Instruction Execution Timing

• Instruction execution typically involves multiple stages (fetch, decode, fetch operands, execute, write).
• Each stage may take multiple clock cycles.

Instruction Execution Timing Example: Premises

• The example uses 8-bit internal and external data buses, a 16-bit external address bus, linear memory organization, 16-bit physical addresses, and 8-bit memory locations. 8-bit general-purpose registers, special-function registers (data, instruction register, auxiliary, etc.), and 16-bit special function registers are also defined.

CISC CPU Block Diagram

• The diagram illustrates a typical CISC CPU's components, including the ALU, general purpose registers, memory data and address registers, and the timing and control unit.

Detailed Description of Specific Machine Cycles (1-6)

• Detailed diagrams and explanations are provided for each machine cycle (fetch, read address, read operand 1, read operand 2, execute, and write results) involved in executing an instruction in a CISC processor, such as an instruction to add one memory location to another.