CPE 302: 8085 Microprocessor Architecture

• CPE 302 is a course at Nile University of Nigeria, taught by Sadiq Abubakar Mohammed in 2024.
• The course is about Microprocessors, Systems, and Interfacing.
• The course will cover the 8085 Microprocessor

8085 Architecture Overview

• The 8085 features an 8-Bit Internal Data Bus, Accumulator, Temporary Registers, and Flags.
• Control is managed by the Timing and Control Circuit.
• Instructions are processed through the Instruction Register and Decoder.
• Serial I/O is managed with SID and SOD lines.

8085 Specifications

• The 8085 is an 8-bit processor in a 40-pin IC package, requiring +5V power.
• It has a maximum frequency of 3MHz.
• The data bus is 8-bit (D0-D7) and the address bus is 16-bit (A0-A15), addressing 64KB of memory.
• Key components include the ALU, registers, control unit, and bus structure.

Arithmetic & Logic Unit (ALU)

• The ALU performs numerical and logical operations like Addition (ADD), Subtraction (SUB), AND, OR, etc.
• It uses data from memory and the Accumulator.
• Results are stored in the accumulator.

Registers

• The 8085 has six general-purpose registers, two temporary registers, one accumulator, and one flag register.
• There are also two 16-bit registers: stack pointer and program counter.

Accumulator

• The accumulator is an 8-bit register and part of the ALU used to store data and perform arithmetic/logical operations, also known as register A.

Flag Register

• The ALU includes five flip-flops that are set/reset based on the data condition of the result in the accumulator and registers.
• Flags are used by the microprocessor to test data conditions.
• CY (Carry): D0 bit position used for Carry/borrow status.
• P (Parity): D2 bit position used for Even parity check.
• AC (Aux Carry): D4 bit position used for BCD carry tracking.
• Z (Zero): D6 bit position used for Zero result check.
• S (Sign): D7 bit position used for Sign bit.

Program Counter (PC)

• A 16-bit register stores the address of the next instruction.
• PC auto-increments after fetching each instruction byte.
• Critical for sequential program execution.

Stack Pointer (SP)

• 16-bit register points to the stack top in memory.
• Requires manual initialization (e.g., LXI SP, FFFFH).
• Decrements on PUSH/CALL and increments on POP/RET.

General Purpose Registers

• B & C are often used together as the BC register pair.
• D & E can form the DE register pair for 16-bit operations.
• H & L are typically paired as HL and frequently serve as a memory pointer.
• These registers can be used individually or as pairs for arithmetic, logic, and data transfer operations.

Temporary Registers (W & Z)

• Two 8-bit non-programmable registers.
• Used exclusively for internal operations like storing intermediate results during ALU operations.
• Hidden from programmers and cannot be accessed directly.

Instruction Register (IR) & Decoder

• The Instruction Register (8-bit) stores the opcode of the fetched instruction or first byte of multi-byte instructions.
• The Instruction Decoder translates the opcode into control signals and activates relevant components (ALU, registers, buses).

Decoding Process

• Opcode fetched is stored in IR and the decoder analyzes bit patterns.
• Generates timing/control signals for execution.

Control Unit

• Generates control signals on the data, address, and control buses to execute decoded instructions.
• Data Bus: 8-bit wide for transferring data between the microprocessor and external devices. Its limited width means larger numbers may require multiple parts.
• Address Bus: 16-bit wide, transmits memory addresses, lower 8 bits (A0-A7) are multiplexed with data and higher 8 bits (A8–A15) are solely addressing.
• Control Bus: Carries specific control signals to manage operations.

Control Signals

• ALE (Address Latch Enable) indicates when the lower address/data lines carry a valid address.
• RD (Read signal): Active low for reading data from memory/I-O devices.
• WR (Write signal): Active low for writing data to memory/I-O devices.
• IO/M distinguishes between I/O (1) and memory (0) operations.
• S1 & S0: Status signals that specify the current operation type.

Status Signals

• S1=0, S0=0: Halt
• S1=0, S0=1: Write
• S1=1, S0=0: Read
• S1=1, S0=1: Fetch

8085 Instruction Set

• A collection of binary commands controls the 8085's operations.
• Each instruction consists of: Opcode which specifies the operation (e.g., ADD, MOV). and Operand which is the data or address (register, memory, or immediate value).
• Execution time for instructions is measured in machine cycles, where each cycle consists of multiple clock periods.
• The microprocessor fetches, decodes, and executes each instruction in sequential steps and some will alter program flow by modifying program counter.

Instruction Set Functionality

• Data Transfer which includes MOV, MVI, LDA, STA, copies data between registers/memory. Example: MOV B, C (Copy C to B).
• Arithmetic includes ADD, SUB, INR, DCR, affects flags (CY, Z, AC). Example: ADD M (Add memory to Acc).
• Logical includes ANA, ORA, XRA, RLC, performs bitwise operations. Example: ANI OFH (AND Acc with 0F).
• Branching includes JMP, CALL, RET, supports Conditional (JZ, JC). Example: JNZ LOOP.
• Machine Control includes HLT, NOP, EI, DI, manages processor states and interrupts.

Instruction Length

• Instructions can be categorized by length (number of bytes): 1-byte, 2-byte, and 3-byte instructions.

Addressing Modes

• Addressing Modes is the process of specifying the data to be operated on by an instruction.
• The 8085 retrieves data from various locations using predefined data access strategies that determine where the operand (data) is located and how it is fetched.
• Instructions can directly or indirectly reference data.
• Operands may reside in registers, memory, or be embedded in the instruction itself.

Immediate Addressing

• Data is specified in the instruction itself. It is part of the program instruction itself.
• Example: MVI B, 3EH (Move the data 3EH to B register), LXI D, FFFOH (Load the data FFF0H to registers D-E), resulting in (B) = 3EH, (D)(E) = FFFOH.

Memory Direct Addressing

• The address of the data is specified in the instruction itself.
• Data is stored in memory and in this mode, program instructions and data can reside in different memory locations.
• Example: LDA 240FH (Load register A with the contents of memory location 240FH).

Register Direct Addressing

• The instruction specifies the name of the register in which data is available.
• Example: MOV B, D moves the contents of register D to register B. INX H increments the contents of H-L register pair.

Register Indirect Addressing

• The instruction specifies the name of the register with the address of the data
• The actual data resides in memory, and its address is held by a register pair.
• Example: MOV B, M moves the contents of memory location addressed by register pair H-L to register B.

Implied Addressing

• The instruction itself specifies the data to be operated on.
• Example: CMA is the content of accumulator (A), RRC rotates the content (A) right by one bit.

8085 Addressing Modes Summary

• Immediate: Data specified in the instruction (MVI B, 3E).
• Memory Direct: The address of the data is specified directly (LDA 240F).
• Register Direct: Uses specified register contents (MOV B, D).
• Register Indirect: Register contains the address of the data (MOV B, M).
• Implied: Operand is implicit in the instruction (CMA).

Interrupts

• An interrupt is an event that temporarily halts program execution to service an urgent task via an ISR.
• I/O device signals the processor when data is ready, which pauses the main program, inputs data from the ISR, and resumes the main program.

Interrupt Handling Steps

• Interrupt Request: An external device/internal condition sends a signal, and the microprocessor checks if interrupts are enabled (EI or DI).
• Interrupt Acknowledgment: The microprocessor acknowledges and saves the current state by pushing Program Counter (PC) and Flags onto the stack.
• Fetch Interrupt Vector: The microprocessor identifies the interrupt type and fetches the vector address: (TRAP: 0024H, RST 7.5: 003CH, RST 6.5: 0034H, RST 5.5: 002CH, INTR: No fixed vector).
• Execute Interrupt Service Routine (ISR): Jumps to the vector address and executes the ISR. Maskable interrupts are automatically disabled during ISR execution.
• Return from Interrupt: At the end of the ISR, the RET instruction is executed and the microprocessor restores the saved state (Flags register and Program Counter (PC)), resuming normal program execution.

Types of Interrupts

• Vectored vs. Non-Vectored Interrupts
• Vectored jumps to predefined ISR address (e.g., RST 7.5, RST 6.5, RST 5.5).
• Non-Vectored needs ISR address externally (e.g., INTR).
• Maskable vs. Non-Maskable Interrupts
• Maskable is enabled/disabled by CPU (e.g., RST 7.5, RST 6.5, RST 5.5, INTR).
• Non-Maskable is serviced immediately and cannot be disabled (e.g., TRAP).
• Hardware vs. Software Interrupts
• Hardware is triggered by external signals (e.g., TRAP, RST 7.5, INTR).
• Software is generated by specific instructions within a program (e.g., RST 0 to RST 7).

Hardware Interrupt Vector Table

• TRAP: 0024H (Non-maskable, highest priority)
• RST 7.5: 003CH (Maskable, high priority)
• RST 6.5: 0034H (Maskable, medium priority)
• RST 5.5: 002CH (Maskable, low priority)
• INTR: No fixed vector (lowest priority, requires external hardware)
• All maskable ones can be enabled/disabled using EI and DI instructions, while RST5.5, RST6.5, and RST7.5 can be individually enabled or disabled using SIM instruction.

Software Interrupts

• The 8085 instruction set includes eight software interrupt instructions called Restart (RST) instructions.
• The concept of priority does not apply to software interrupts and inserted into the program as instructions by the programmer processed when lines are read.
• Software interrupt address locations: RST0-C7-0000H, RST1-CF-0008H, RST2-D7-0010H, RST3-DF-0018H, RST4-E7-0020H, RST5-EF-0028H, RST6-F7-0030H, RST7-FF-0038H.

Direct Memory Access (DMA)

• DMA allows hardware devices direct access to the system's memory without CPU intervention, which enables high-speed data transfer between peripherals (e.g., disk drives, network cards) and memory.
• DMA reduces CPU overhead by bypassing the need for the CPU to handle data transfers, freeing up the CPU and provides faster data rates for time-sensitive applications.
• DMA Components: DMA Controller manages data transfers, Memory is the source or destination, and Peripheral Device initiates the DMA request.

DMA Operation

• Request is when a Peripheral device sends a DMA request (DRQ) to the DMA controller
• Acknowledgment is when a DMA controller sends a Hold Request (HOLD) to the CPU which grants control by asserting Hold Acknowledge (HLDA).
• Data Transfer is when a DMA controller takes control of the address and data buses and transfers data directly between memory and the peripheral.
• Completion is when a DMA controller releases the buses and notifies the CPU.

DMA Transfer Modes

• Burst Mode transfers a block of data in one go. Although it has high speed but monopolizes the bus.
• Cycle Stealing Mode transfers one data unit at a time, pausing between transfers (slower but allows CPU to access the bus intermittently.)
• Transparent Mode transfers data only when the CPU is idle making it the Least intrusive but slowest.