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Questions and Answers
What is the conclusion drawn from the results of the work mentioned?
What is the conclusion drawn from the results of the work mentioned?
It is not possible to estimate a range of K values for routable netlists due to congestion depending on netlist structure and available routing resources.
What methodology is proposed in the paper for congestion minimization during technology mapping?
What methodology is proposed in the paper for congestion minimization during technology mapping?
A new approach for congestion-aware logic synthesis integrated with a technology mapping algorithm.
Which statement best describes the proposed methodology's impact on timing and congestion?
Which statement best describes the proposed methodology's impact on timing and congestion?
The methodology suggests that a mapped netlist can be efficiently obtained by further increasing K if the congestion map indicates that the netlist is within the _______ region.
The methodology suggests that a mapped netlist can be efficiently obtained by further increasing K if the congestion map indicates that the netlist is within the _______ region.
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What does Static Timing Analysis (STA) help verify?
What does Static Timing Analysis (STA) help verify?
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What happens to the cell area utilization as the value of K increases?
What happens to the cell area utilization as the value of K increases?
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Increasing K in congestion minimization significantly alters the structure of the mapped netlist.
Increasing K in congestion minimization significantly alters the structure of the mapped netlist.
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In the experiments, the mapped netlists were routed without violations with Silicon ____.
In the experiments, the mapped netlists were routed without violations with Silicon ____.
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What is the objective of logic synthesis?
What is the objective of logic synthesis?
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What are the two phases modern logic synthesis systems divide the task into?
What are the two phases modern logic synthesis systems divide the task into?
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Excessive efforts in area minimization during logic synthesis can lead to higher congestion.
Excessive efforts in area minimization during logic synthesis can lead to higher congestion.
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The ______ cost at vertex v for match m can be expressed by $AREA(m, v) = \text{______}(m) + \sum \text{______Cost}(v_i)$, where $v_i \in \text{fanins}(m, v)$.
The ______ cost at vertex v for match m can be expressed by $AREA(m, v) = \text{______}(m) + \sum \text{______Cost}(v_i)$, where $v_i \in \text{fanins}(m, v)$.
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What was forecasted by Sylvester and Keutzer regarding the impact of DSM interconnect effects on block sizes within 50k gates?
What was forecasted by Sylvester and Keutzer regarding the impact of DSM interconnect effects on block sizes within 50k gates?
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What did Sylvester and Keutzer suggest could still be used for blocks of 50k gate size with a sufficient cell sizing capability?
What did Sylvester and Keutzer suggest could still be used for blocks of 50k gate size with a sufficient cell sizing capability?
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Pi-leggi speculated that as DSM technologies advance, the number of blocks and global interconnect wires are bound to increase, leading to an increase in the global __________ distribution spread.
Pi-leggi speculated that as DSM technologies advance, the number of blocks and global interconnect wires are bound to increase, leading to an increase in the global __________ distribution spread.
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What is the expression used to represent the wire contribution for match m at vertex v?
What is the expression used to represent the wire contribution for match m at vertex v?
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Traditional synthesis addresses routability for all circuits.
Traditional synthesis addresses routability for all circuits.
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What does the function WIRE(m,v) include?
What does the function WIRE(m,v) include?
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The wire cost is uniform across all fanins of the match under consideration.
The wire cost is uniform across all fanins of the match under consideration.
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What is the main focus of the proposed methodology in this paper?
What is the main focus of the proposed methodology in this paper?
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Why is wiring congestion considered an extremely important design factor?
Why is wiring congestion considered an extremely important design factor?
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In the optimization factor equation COST(m, v) = AREA(m, v) + K $\cdot$ WIRE(m, v), K is used to control the impact of _______ minimization with respect to cell area minimization.
In the optimization factor equation COST(m, v) = AREA(m, v) + K $\cdot$ WIRE(m, v), K is used to control the impact of _______ minimization with respect to cell area minimization.
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It is practical to assume that minimizing cell area will also minimize the overall size of the logic block.
It is practical to assume that minimizing cell area will also minimize the overall size of the logic block.
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The impact of interconnects on performances has to be carefully evaluated to satisfy the design constraints during all phases of the traditional ASIC top-down design flow, which broadly consists of: logic synthesis and physical design (placement and routing). Constraints on timing are defined together with the logic description of the circuit and must be considered during all stages of the top-down flow to ensure ______ closure.
The impact of interconnects on performances has to be carefully evaluated to satisfy the design constraints during all phases of the traditional ASIC top-down design flow, which broadly consists of: logic synthesis and physical design (placement and routing). Constraints on timing are defined together with the logic description of the circuit and must be considered during all stages of the top-down flow to ensure ______ closure.
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Study Notes
Congestion-Aware Logic Synthesis
- In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the overall performance of VLSI systems.
- Interconnect capacitance becomes dominant with respect to gate capacitance, rapidly increasing the interconnect delay.
- Wireload models used in timing-driven layout tools are inaccurate, and estimation based on fanout and design legacy statistics can be highly inaccurate.
- Wiring congestion is an extremely important design factor and should be considered at the earliest possible stages of the design flow.
Limitations of Wireload Models
- Wireload models often yield results that are significantly different from actual post-layout values.
- Many iterations between logic synthesis and physical design are necessary to achieve timing closure.
- Commercial approaches from EDA vendors have attempted to combine logic synthesis and placement in an iterative procedure or apply resynthesis during physical design.
Problem of Congestion Minimization
- Congestion minimization is a difficult problem since it depends on the structure of the gate-level netlist and the amount of routing resources available.
- Traditional synthesis does not address routability, and the problem of predicting the impact of interconnect on delay and area prior to physical design remains unsolved.
Approach to Congestion-Aware Logic Synthesis
- The objective is to synthesize structurally routable netlists that satisfy the constraints on total block area and meet other performance constraints such as timing.
- The approach involves exploring trade-offs between area (and/or delay) and congestion minimization when a fixed amount of routing resources are available.
Previous Work
- Significant progress has been made to provide logic synthesis with physical information to overcome the limitations of the wireload model.
- Previous work integrates technology mapping with a companion placement to generate trade-offs for area (and/or delay) minimization.### TOO_LARGE Benchmark
- TOO_LARGE is a benchmark used for phase partitioning
- It consists of 27,977 base gates (two-input NANDs and inverters)
- The Register-Transfer-Level (RTL) description of the circuit was synthesized by the logic synthesis tool SIS
- The RTL description was then mapped onto the CORELIB8DHS 2.0 technology independent representation
Placement-Driven DAG Partitioning
- The network DAG is partitioned into a forest of trees
- A matching algorithm identifies all possible matches corresponding to instances of a cell library for each tree
- During the covering phase, an optimal choice is selected according to some cost factor
- Physical information is included in the DAG partitioning and covering steps
- Technology independent network is placed to capture the connectivity on a chip layout image
Placement Results
- The results show that SIS yields the best result in terms of area minimization
- DAGON, which is a technology mapping program, is limited by the initial structure of the technology independent netlist
- The netlist obtained with SIS has less area utilization with respect to the netlist obtained with DAGON
- However, the netlist mapped with DAGON can be routed successfully in the same block area
Our Approach: Congestion-Aware Technology Mapping
- The objective is to produce a circuit which implements a set of logic equations, occupies minimum Si area, and satisfies performance constraints
- Modern logic synthesis systems divide this task into two phases: technology independent optimization and technology mapping
- The first phase is based on the RTL description of the circuit
- The second phase is based on the mapped gate level netlist
Placement-Driven DAG Partitioning Algorithm
- The algorithm is based on a Depth First Search (DFS) traversal from the circuit primary outputs to the primary inputs
- It takes into account physical location of the corresponding base gates obtained from the technology independent placement
- Partitioning is based on the property that the father of every internal vertex is always the nearest vertex on the chip layout image according to some distance metric
Congestion-Aware Tree Covering
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The tree covering step can be optimally solved in linear time with the size of the tree by means of a dynamic programming algorithm
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The basic structure of the covering algorithm does not significantly change, and the main difference lies in the optimization objective expressed by the cost function
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By modifying the cost function, different optimization targets can be addressed### Congestion Minimization in Technology Mapping
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The goal of congestion minimization is to reduce the number of routing violations and improve the overall routability of a circuit.
Dynamic Programming Algorithm
- The algorithm performs its choices based on a cost function that minimizes area.
- The cost function can be modified to include interconnection length for congestion minimization, but this may lead to sub-optimal solutions with respect to minimum cell area.
Impact of Wires on Cost Function
- The impact of wires on the cost function depends directly on their length, which is influenced by initial floorplan constraints, such as chip or block size.
- The absolute length of interconnections changes when the size of the layout image changes, affecting the wire cost during technology mapping.
Technology Mapping Tool
- A prototype technology mapping tool was implemented, which addresses typical optimization objectives, such as area and/or delay.
- The tool includes congestion minimization as an objective, controlled by the congestion minimization factor K.
Experimental Results
- The experimental results show that as K increases, the impact of congestion minimization on the cost function becomes more significant, leading to a trade-off between cell area and routability.
- The results also demonstrate that congestion minimization can improve timing, as it reduces the total wire length.
Benchmark Circuits
- The benchmark circuits used in the experiments were SPLA and PDC, with sizes of 22,834 and 23,058 base gates, respectively.
- The results show that even with a block size limit of 50,000 gates, wire congestion cannot be neglected.
Comparison with Other Methods
- The results were compared with DAGON (K = 0.0) and SIS, showing that the proposed approach can improve congestion and routability while reducing the total chip area.
Proposed Methodology
- The approach can be integrated into the traditional design flow, starting with a technology-independent netlist and its initial placement.
- The congestion minimization factor K is increased until a congestion map is acceptable, and then physical design can be carried out.
Advantages of the Approach
- The approach can efficiently generate solutions with less congestion, reducing the need for detailed place&route, which is computationally expensive.
- The congestion map can be quickly evaluated, and the final placement and routing can be executed when the designer is satisfied with the congestion map.
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Description
This quiz is about congestion-aware logic synthesis, a technique used in digital circuit design. It involves optimizing digital circuits to minimize congestion and improve performance. The quiz covers the concepts and methods of congestion-aware logic synthesis.
