Computer Systems Memory Characteristics

• Computer systems memory characteristics include location, capacity, unit of transfer, method of accessing, performance, physical type, physical characteristics, and organization

Memory Location

• Internal memory examples: Main memory, registers, control unit, cache
• External memory includes peripheral storage devices

Capacity

• Internal memory capacity is measured in bytes or words (1 byte=8 bits)
• External memory capacity is measured in bytes

Unit of Transfer

• The number of electrical lines into and out of the memory module (internal memory)

Method of Accessing

• Sequential access requires accessing data in a specific linear sequence, starting at the beginning until the required memory is accessed. Addressing information separates records, and access time depends on memory location.
  • Example: Magnetic tapes, magnetic disks, and optical memory
• Random access allows data access at random with consistent access time across all locations, independent of previous access, and is physically wired in addressing mechanism
  • Example: RAM
• Direct access is a combination of random and sequential access methods
  • Individual blocks have unique addresses and access time depends on memory organization and storage technology
  • Example: Magnetic hard disk
• Associative access is a random access type of memory using tags or metadata to describe content
  • Desired bit locations are compared within a word for a specified match, and the word retrieved is based on its contents rather than address
  • Each location has its own addressing mechanism with constant access time
  • Example: Cache memory

Performance Parameters

• Access Time (Latency)
  • For random-access memory: time to perform read or write operation
  • For non-random-access memory: time to position the read-write mechanism at desired location
• Memory Cycle Time
  • Applies to the system bus, not the processor
  • Access time plus additional time before a second access can commence
• Transfer Time
  • Data rate transferred into or out of a memory unit

Physical Type

• Semiconductor memory
• Magnetic surface memory

Physical Characteristics

• Volatile Memory (System RAM (DRAM)) requires power to maintain stored information
• Nonvolatile Memory (Magnetic-surface memories)
• Non-erasable Memory (Read-Only Memory (ROM))

Organization

• Physical arrangement of bits forming words

Memory Hierarchy

• Key characteristics of memory: capacity, access time, cost
• Key Characteristics Relationship
  • Faster access time = greater cost per bit
  • Greater capacity = smaller cost per bit
  • Greater capacity = slower access time
• Smaller, more expensive, faster memories are supplemented by larger, cheaper, slower memories
• Decreasing cost per bit, increasing capacity, increasing access time, decreasing frequency of access of the memory by the processor

Memory Types

• Registers internal to the processor: fastest, smallest, most expensive memory
• Cache memory stages data movement between main memory and processor registers to improve performance
• External mass storage devices: permanent data storage
  • Hard disk and removable media like magnetic disk, tape, and optical storage
• External, nonvolatile, secondary, or auxiliary memory stores program and data files
• Disk provides main memory extension known as virtual memory

Cache Memory

• Cache memory satisfies a single memory reference because of the Locality of Reference
  • Computer programs/processors tend to access the same set of memory locations for a particular time period

Cache Memory Principles

• Cache contains a copy of portions of the main memory
• CPU checks if the accessed word of memory is in the cache
• If not, a block of main memory with a fixed number of words, is read into the cache and then the word is delivered to the processor
• Cache is intended to give memory speed approaching and large memory size at a less expensive cost

Cache Read Operation

• RA = read address
  • If the CPU finds the required data or instruction in the cache, it will directly fetch the data from the cache and it is known as a cache hit (no system bus traffic)
  • If the required data or instructions are not found in the cache, it is known as a cache miss (desired address is loaded and data is returned)

Multi Level Cache

• Improves performance by reducing the "Miss Penalty" which is the extra time taken to load data into the cache from main memory during a cache miss
• Increase the size and decrease the speed

Cache Organization

• Includes Address buffer, processor, cache, system bus and data buffer

Cache Memory vs Main Memory

• Cache consists of m blocks (lines), while main memory consists of M blocks
• Each line in the cache contains K words and a tag
• Line size is the length of a line without the tag and control bits
• Main memory consists of 2^n addressable words, there are K of words in one block

Cache Memory Details

• Each word in the line is a single byte.
• A subset of the blocks of memory exists in lines in the cache
• If a word in a block of memory is read, that block transfers to one of the lines of the cache
• Each unique line includes a tag to identifies the block being stored
• Tag = Portion of the main memory address

Elements of Cache Design

• Cache Addresses
  • Virtual Memory allows programs to address memory from a logical point of view, without regard to the amount of main memory available
    • Address fields of the machine instruction contain virtual addresses
  • Memory Management Unit (MMU) translates virtual address into a physical address in the main memory
    • Two possible ways to place the cache in the computer when virtual addresses are used; Physical cache or Logical cache

Physical vs Virtual Cache

• Physical Cache stores data using main memory physical addresses
• Logical Cache (Virtual Cache) stores data using virtual addresses
  • Processor accesses the cache directly, without going through the MMU
  • Access speed is faster than physical cache
  • Virtual memory systems supply each application with the same virtual memory address space

Cache Size

• Small enough so that the overall average cost per bit is close to that of the main memory
• Large enough so that the overall average access time is close to that of the cache
• Limited by available chip and board area

Mapping Function

• Algorithm is needed for mapping main memory blocks into cache lines.
• A means is needed for determining which main memory block currently occupies a cache line.
• Techniques:
  • Direct mapping
  • Associative Mapping
  • Set Associative Mapping

Direct Mapping

• Maps each block of main memory into only one unique line of the cache
• Expressed as i = j modulo m
  • i = Cache line
  • j = Main memory block number
  • m = No: of cache lines
• Taking the least k bits of a binary value is the same as computing that value mod 2k
• Least significant bits provide the relevant line number

Direct Mapping cont.

• The least significant w bits identify a unique word
• the remaining s bits specify one of the 2s blocks of main memory
• Tag of (s - r) bits (most significant portion) and a line field of r bits
• latter field identifies one of the lines of the cache
  • Address length = (s + w) bits
  • Number of addressable units = 2(s+w) words or bytes
  • Block size = Line size = 2^w words or bytes
  • Number of blocks in main memory = words or bytes
  • Number of lines in cache =2 =m

Direct Mapping Advantages/Disadvantages

• A portion of the address is used as a line number providing a unique mapping of each block of main memory into the cache
• When a block is read into its assigned line, it is necessary to tag the data to distinguish it from other blocks that can fit into that line.
• The most significant (s - r) bits serve this purpose
• Simple and inexpensive to implement
• Main disadvantage = a fixed cache location exists for any given block

Associative Mapping

• Overcomes the disadvantage of direct mapping by permitting each main memory block to be loaded into any line of the cache
• Cache control logic interprets a memory address simply as a Tag and a Word field
• The Tag field uniquely identifies a block of main memory
• Determines whether a block is in the cache, the cache control logic must simultaneously examines every line's tag for a match
• Lacks any field in the address corresponding to the line number (therefore, the number of lines in the cache is not determined by the address format)

Associative Mapping cont.

• Complex circuitry is required to examine the tags of all cache lines in parallel
  • Address length = (s + w)
  • Number of addressable units = 2s+w words or bytes
  • Block size = line size = 2^w words or bytes
  • Number of blocks in main memory = 2s
  • Number of lines in cache undetermined
  • Size of tag = s bits

Set Associative Mapping

• Combination of both the direct and associative approaches while reducing their disadvantages
• Cache consists of a number sets, each of which consists of a number of lines.
• i = Cache set number
• j = Main memory block number
• m = Number of lines in the cache
• v = Number of sets
• k = Number of lines in each set
• m = v · k
• i = j modulo v

Set Associative Mapping cont.

• Cache lines are grouped into sets, and each set contains a certain number of lines, say k
• A particular block of main memory can map to only one particular set of the cache
• Within that set, the memory block can map to any freely available cache line