Computer Organisation Chapter 6
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Questions and Answers

What is the primary issue with the lower bits address indexing in the example provided?

  • Two distinct branch instructions may end up with the same index (correct)
  • The indexing is too slow
  • The indexing is not compatible with all memory types
  • The indexing is not scalable

    • What is the limitation of the 1-bit prediction scheme in the context of a loop?

  • It is not suitable for conditional branches
  • It is not efficient in terms of memory usage
  • It is too complex to implement
  • It is likely to mispredict twice when a branch is not taken (correct)

    • What is the main purpose of the example shown in Listing 6.2?

  • To illustrate the 1-bit prediction scheme
  • To show how to optimize memory usage
  • To explain the concept of dynamic branch prediction
  • To demonstrate the limitation of the lower bits address indexing (correct)

    • What is the consequence of the misprediction in the 1-bit prediction scheme?

    <p>The prediction bit is flipped</p> Signup and view all the answers

    What is the primary issue with the indexing scheme shown in Listing 6.3?

    <p>Two distinct branch instructions may end up with the same index</p> Signup and view all the answers

    What is the purpose of the code shown in Listing 6.4?

    <p>To illustrate the limitation of the 1-bit prediction scheme in a loop</p> Signup and view all the answers

    What is the main reason why speculative execution is required in certain types of loops?

    <p>To handle conditional branch instructions with RAW dependence on the loop iteration</p> Signup and view all the answers

    What is the consequence of not having efficient branch prediction in speculative superscalar execution?

    <p>Decreased performance due to unrecovered hardware cost</p> Signup and view all the answers

    What is the main advantage of dynamic branch prediction over static branch prediction?

    <p>It considers the fact that branch instructions can be executed many times during program execution</p> Signup and view all the answers

    What is the result of increasing the number of executed instructions per clock cycle?

    <p>Decreased CPI and increased performance</p> Signup and view all the answers

    What is the maximum number of times the branch prediction will miss in the given code snippet?

    <p>5000</p> Signup and view all the answers

    What is the purpose of reservation stations in speculative superscalar execution?

    <p>To hold instructions waiting for their operands to be available</p> Signup and view all the answers

    What is the primary function of branch-prediction buffers?

    <p>To relate one bit to each branch decision</p> Signup and view all the answers

    What is the main challenge in controlling dependencies in speculative superscalar execution?

    <p>Detecting control dependencies</p> Signup and view all the answers

    What is the consequence of a branch outcome misprediction in speculative superscalar execution?

    <p>The incorrect branch is executed, but the correct branch is eventually recovered</p> Signup and view all the answers

    What is the limitation of the 1-bit branch-prediction buffer?

    <p>The prediction is a hint assumed to be correct, but may not be</p> Signup and view all the answers

    What is the main reason why speculative execution is necessary in certain types of loops?

    <p>To handle conditional branch instructions with RAW dependence on the loop iteration</p> Signup and view all the answers

    What is the purpose of using the low-order address bits in the branch-prediction buffer?

    <p>To have variations, i.e., different addresses considering the use of just the low-order bits</p> Signup and view all the answers

    What is the state of the 1-bit branch-prediction buffer when the prediction is correct?

    <p>TAKEN</p> Signup and view all the answers

    What happens when the branch prediction is incorrect in the 1-bit branch-prediction buffer?

    <p>The prediction bit is inverted and stored back</p> Signup and view all the answers

    What is the name of the approach that considers the aid of a small memory indexed by the lower portion of the branch instruction address?

    <p>Branch History Table</p> Signup and view all the answers

    What is the primary goal of using branch prediction in the given code snippet?

    <p>To improve the accuracy of the branch predictions</p> Signup and view all the answers

    What is the issue with the addresses in Listing 6.3?

    <p>Two distinct branch instructions end up with the same index.</p> Signup and view all the answers

    What happens to the prediction bit in the 1-bit prediction scheme when a branch is mispredicted?

    <p>The prediction bit is flipped.</p> Signup and view all the answers

    What is the purpose of the example in Listing 6.2?

    <p>To demonstrate the use of lower bits addresses in indexing small memory.</p> Signup and view all the answers

    What is the consequence of the 1-bit prediction scheme's shortcoming in a loop?

    <p>The scheme will mispredict twice, rather than once when the branch is not taken.</p> Signup and view all the answers

    What is the relationship between the branch instruction address and the small memory address in Listing 6.2?

    <p>The small memory address is the lower bits of the branch instruction address.</p> Signup and view all the answers

    What is the effect of the misprediction on the branch prediction bit in the 1-bit prediction scheme?

    <p>The branch prediction bit is flipped.</p> Signup and view all the answers

    What is the primary reason why speculative execution is required in certain types of loops?

    <p>To handle the RAW dependence on the loop iteration</p> Signup and view all the answers

    What is the main challenge in controlling dependencies in speculative superscalar execution?

    <p>Detecting dependencies between instructions</p> Signup and view all the answers

    What is the primary benefit of dynamic branch prediction over static branch prediction?

    <p>It considers the fact that branch instructions can be executed many times</p> Signup and view all the answers

    What is the main purpose of additional memory in speculative superscalar execution?

    <p>To guarantee an eventual correction in case of a prediction error</p> Signup and view all the answers

    What is the result of increasing the number of executed instructions per clock cycle?

    <p>The potential instructions flow increases</p> Signup and view all the answers

    What is the main advantage of using speculative execution in certain types of loops?

    <p>It minimizes the delays caused by branches</p> Signup and view all the answers

    What is the primary function of reservation stations in speculative superscalar execution?

    <p>To schedule instructions in the correct order</p> Signup and view all the answers

    What is the consequence of not having efficient branch prediction in speculative superscalar execution?

    <p>The performance does not pay off the new hardware cost</p> Signup and view all the answers

    What is the primary objective of using a branch-prediction buffer?

    <p>To reduce the number of mispredictions</p> Signup and view all the answers

    What is the main characteristic of a 1-bit branch-prediction buffer?

    <p>It is a 2-state finite-state machine with states: TAKEN and UNTAKEN</p> Signup and view all the answers

    What is the role of the low-order address bits in the branch-prediction buffer?

    <p>To index the branch-prediction buffer</p> Signup and view all the answers

    What happens when the branch prediction is incorrect in the 1-bit branch-prediction buffer?

    <p>The prediction bit is inverted and stored back</p> Signup and view all the answers

    What is the primary benefit of using dynamic branch prediction over static branch prediction?

    <p>It can adapt to changing branch behavior</p> Signup and view all the answers

    What is the main limitation of the 1-bit branch-prediction buffer?

    <p>It can only store a single bit of information</p> Signup and view all the answers

    What is the purpose of the branch history table?

    <p>To provide a hint about the branch direction</p> Signup and view all the answers

    What is the consequence of a misprediction in the 1-bit branch-prediction buffer?

    <p>The instruction pipeline is flushed</p> Signup and view all the answers

    Study Notes

    Speculative Execution

    • Speculative execution is required when unrolling loops with conditional branch instructions that have a RAW dependence on the loop iteration.
    • It requires more hardware, such as reservation stations and functional units, as well as more complex control and dependencies detection.
    • Additional memory is needed to guarantee an eventual correction in case of a prediction error.
    • The architecture needs more efficient branch prediction to pay off the new hardware cost with performance.

    Control Dependencies

    • As the number of executed instructions per clock cycle increases, the potential instructions flow also increases, reducing CPI.
    • Delays caused by branches can seriously impact performance.
    • A "simple" strategy to minimize this problem is to not stop or reduce speed in branches.

    Dynamic Branch Prediction

    • Dynamic branch prediction considers the fact that branch instructions can be executed many times during program execution, e.g., inside loops.
    • This approach is different from static branch prediction strategies, such as predicted-not-taken and predicted-taken.
    • The predicted-not-taken approach may be inefficient in loops, leading to many mispredictions.

    Branch-Prediction Buffers

    • A possible solution to the problem is to use branch-prediction buffers, which relate one bit to each branch decision.
    • The buffer is a small memory indexed by the lower portion of the branch instruction address.
    • The memory contains a bit that indicates whether a branch was recently taken or untaken.
    • This approach is a hint assumed to be correct, and the next instruction fetch begins in the predicted direction.
    • If the hint is wrong, the prediction bit is inverted and stored back.

    1-Bit Prediction

    • The 1-bit prediction scheme is a simple dynamic branch-prediction scheme.
    • It is a 2-state finite-state machine (FSM) with states: TAKEN and UNTAKEN.
    • The scheme uses just the low-order address bits to have variations, i.e., different addresses considering the use of just the low-order bits.
    • However, there may be an inconvenient or even problematic case regarding these low-order address bits, where two distinct branch instructions end up with the same index.
    • The 1-bit prediction scheme has the shortcoming that it may mispredict twice, rather than once, when a branch is not taken in a loop.

    Speculative Execution

    • Speculative execution is required when unrolling loops with conditional branch instructions that have a RAW dependence on the loop iteration.
    • It requires more hardware, such as reservation stations and functional units, as well as more complex control and dependencies detection.
    • Additional memory is needed to guarantee an eventual correction in case of a prediction error.
    • The architecture needs more efficient branch prediction to pay off the new hardware cost with performance.

    Control Dependencies

    • As the number of executed instructions per clock cycle increases, the potential instructions flow also increases, reducing CPI.
    • Delays caused by branches can seriously impact performance.
    • A "simple" strategy to minimize this problem is to not stop or reduce speed in branches.

    Dynamic Branch Prediction

    • Dynamic branch prediction considers the fact that branch instructions can be executed many times during program execution, e.g., inside loops.
    • This approach is different from static branch prediction strategies, such as predicted-not-taken and predicted-taken.
    • The predicted-not-taken approach may be inefficient in loops, leading to many mispredictions.

    Branch-Prediction Buffers

    • A possible solution to the problem is to use branch-prediction buffers, which relate one bit to each branch decision.
    • The buffer is a small memory indexed by the lower portion of the branch instruction address.
    • The memory contains a bit that indicates whether a branch was recently taken or untaken.
    • This approach is a hint assumed to be correct, and the next instruction fetch begins in the predicted direction.
    • If the hint is wrong, the prediction bit is inverted and stored back.

    1-Bit Prediction

    • The 1-bit prediction scheme is a simple dynamic branch-prediction scheme.
    • It is a 2-state finite-state machine (FSM) with states: TAKEN and UNTAKEN.
    • The scheme uses just the low-order address bits to have variations, i.e., different addresses considering the use of just the low-order bits.
    • However, there may be an inconvenient or even problematic case regarding these low-order address bits, where two distinct branch instructions end up with the same index.
    • The 1-bit prediction scheme has the shortcoming that it may mispredict twice, rather than once, when a branch is not taken in a loop.

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    Description

    This quiz covers branch prediction and speculative superscalar processors in computer organisation, focusing on loop unrolling and speculative execution.

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