Computer Architecture: Speculative Execution and Control Dependencies

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Questions and Answers

What is the main goal of speculative execution?

To detect and correct branch prediction errors

To reduce RAW dependence/hazards

To reduce the number of iterations in a loop

To increase instruction-level parallelism (correct)

What type of processor architecture is closely related to speculative execution?

Asynchronous processor

Vector processor

Superscalar processor (correct)

Pipelined processor

What is the primary function of a branch-prediction buffer?

To handle RAW dependence/hazards

To predict the outcome of a branch (correct)

To store the instructions in a loop

To store the target address of a branch

What is the main advantage of correlating predictors in dynamic branch prediction?

Improving the accuracy of branch prediction Signup and view all the answers

What is an alternative to Tomasulo's algorithm for managing out-of-order execution?

Scoresboard algorithm Signup and view all the answers

What is the main purpose of loop unrolling?

To increase the instruction-level parallelism in a loop Signup and view all the answers

What is the main characteristic of a multiple-issue superscalar processor?

Ability to execute multiple instructions per clock cycle Signup and view all the answers

What is the primary benefit of hardware-based speculation?

Increasing the instruction-level parallelism in a program Signup and view all the answers

What is a key requirement for speculative superscalar execution?

More hardware is needed, e.g., reservation stations, functional units. Signup and view all the answers

What is the primary goal of speculative execution?

To increase the potential instructions flow and minimize delays caused by branches. Signup and view all the answers

What is a limitation of static branch prediction?

It does not account for branches that are executed multiple times during a program execution. Signup and view all the answers

What is the impact of more parallel instructions on branch delays?

It increases the impact of branch delays. Signup and view all the answers

Why is the predicted-not-taken approach potentially inefficient?

It can lead to inefficiencies in certain scenarios, such as loops. Signup and view all the answers

What is the purpose of a branch-prediction buffer?

To minimize the impact of branch delays. Signup and view all the answers

What is a characteristic of dynamic branch prediction?

It can adapt to branches that are executed multiple times during a program execution. Signup and view all the answers

What is a potential consequence of misprediction in speculative execution?

It leads to an increase in CPI. Signup and view all the answers

What is the criterion for predicting a branch as taken or untaken in dynamic branch prediction?

The lower portion of the branch instruction address Signup and view all the answers

What happens when the prediction bit is incorrect in dynamic branch prediction?

The prediction bit is inverted and stored back Signup and view all the answers

Why is using just the low-order address bits in branch-prediction buffers a problem?

It causes aliasing and reduces prediction accuracy Signup and view all the answers

What is a shortcoming of the 1-bit prediction scheme?

It mispredicts twice when a branch is almost always taken Signup and view all the answers

What is the purpose of the branch-prediction buffer?

To predict whether a branch is taken or untaken Signup and view all the answers

What is an advantage of dynamic branch prediction over static branch prediction?

It can adapt to changing branch behavior Signup and view all the answers

What happens when the branch-prediction buffer is indexed using the lower portion of the branch instruction address?

The branch-prediction buffer returns the associated prediction bit Signup and view all the answers

What is the purpose of fetching in the predicted direction?

To reduce the branch misprediction penalty Signup and view all the answers

Study Notes

Speculative Execution

Speculative execution is required when unrolling loops with RAW dependence/hazards with an iteration.
It needs more hardware, such as reservation stations and functional units, and more complex control and dependencies detection.
It also requires additional memory to guarantee correction in case of prediction error (misprediction).
Efficient branch prediction is necessary to pay the new hardware cost with performance.

Control Dependencies

As the number of executed instructions per clock cycle increases, the potential instructions flow also increases, reducing CPI.
Delays caused by branches can seriously impact performance, and a solution is to not stop or reduce speed in branches.

Dynamic Branch Prediction

Dynamic branch prediction is necessary when branches are executed many times during a program execution, such as in loops.
Predicted-not-taken approach may be inefficient, and more parallel instructions mean greater impact due to branch delays.

Branch-Prediction Buffers

Branch-prediction buffers are a possible solution to the problem, relating one bit to each branch decision.
The prediction is based on the last iteration's outcome (taken or untaken).
The target branch address still needs to be computed.
Branch-prediction buffers are a simple dynamic branch-prediction scheme, also known as a branch history table.
They are a small memory indexed by the lower portion of the branch instruction address.
The memory contains a bit associated with each branch, indicating whether it was recently taken or untaken.
The prediction is a hint assumed to be correct, and fetching begins in the predicted direction.
If the hint is wrong, the prediction bit is inverted and stored back.

Branch-Prediction Buffers Limitations

Using only the low-order address bits can be a problem, as different branches may have the same low-order address bits.
The 1-bit prediction scheme has a shortcoming, as it may mispredict twice when a branch is not taken, causing the prediction bit to be flipped.

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Description

This quiz covers the concepts of speculative execution and control dependencies in computer architecture, including RAW dependence, branch prediction, and hardware requirements.