Computer Memory and Error Correction

• The resource is about computer hardware, specifically memory.
• It is an introduction to computer systems.
• It is presented by Ing. Otto Mejia

Memory Basics

• Adding memory is a popular, easy, and economical way to upgrade computers.
• Computer CPUs store data and instructions in the memory while operating.
• Memory upgrades provide a significant performance boost, however, motherboards, operating systems, and CPUs have memory limits.
• When only one memory card is installed, it will be near empty slots.
• Figures illustrates memory location in a system, and in the example, it is displayed with all four banks full.

Technical Terms and Functions

• Parity Checking
• Error Correction Code (ECC)
• Single and Double-sided memory
• Single, Double, Triple, and Quad channel memory

Memory Parity Check

• RAM parity is an error detection mechanism used in memory modules to identify data corruption with the primary purpose of verifying data integrity and alerting errors.
• Each byte of stored data is made up of 8 bits.
• Parity memory adds a ninth bit called a parity bit.
• Parity bits are calculated based on the 8 data bits using two methods: even parity and odd parity.
• Even Parity adjusts so the total number of "1" bits is even, including the parity bit.
• Odd Parity adjusts the parity bit so the total number of "1" bits is odd.
• During RAM data reads, the parity bit is checked again to detect memory errors.
• In an 8-bit system with even parity, the total "1" bits including the parity bit, must be even.
• If the data byte is 1010 0110 (four "1" bits, even), with even parity, the parity bit would be "0", making the parity byte 1010 0110 0.
• If the data byte is 1101 0110 (five "1" bits, odd), with even parity, the parity bit would be "1," making the parity byte 1101 0110 1.
• In an odd parity system, the total number of "1" bits must be odd.
• With the 1010 0110 data byte (four "1" bits, even) the parity bit must be "1", turning the parity byte into 1 1010 0110.
• With the 1101 0110 data byte (five "1" bits, odd), no parity bit is needed turning the parity byte into 0 1101 0110.
• Non-parity memory stores data without verifying integrity.
• Parity memory adds parity bits to detect single-bit errors.
• Error Correction Code/ ECC memory is an advanced version that detects and automatically corrects single-bit errors.
• Several features differentiate memory types including Parity, Non Parity and ECC memory.
• Parity Memory detects errors and is typically used for critical workstations.
• Non Parity Memory does not detect errors and is typically used for standard laptops and pcs.
• Error Correction Code (ECC) Memory corrects errors and is typically used for critical mission systems.

Error Checking and Correction

• Error Correction Code/ ECC is considered an advanced version of memory error detection.
• With ECC, verification bits are generated and stored with the data.
• Each time the memory is accessed, an algorithm is run on the data and its verification bits.
• When the algorithm results come out all zeros, the data is considered valid and processing will proceed.
• ECC both detects one and two-bit errors, but also corrects single-bit errors.
• If a single bit is wrong in a particular byte (8-bit group), ECC recognizes and corrects it. If two bits are wrong, ECC can only recognize the error.

One and Two-sided Memory

• One and two-sided memory refers to how memory modules have chips on one or both sides.
• The system treats a double-sided memory card as two separate memory modules.
• Motherboards supporting double-sided memory have memory controllers that switch between module "sides." Can only access the side commutated to at a given moment.
• Double-sided memory allows adding more memory to a computer, using half the physical space of one-sided memory, that needs no switching by the memory controller

Single, Double, Triple, and Quad Channel Memory

• Standard Memory controllers manage memory access in chunks that are the data width of system bus.
• This is considered single-channel communication.
• Modern processors typically have a system data bus of 64 bits.
• Standard memory controller can transfer exactly 64 bits of information at once.
• Communication through a single channel is a bottleneck where CPUs and memory are faster than the connection between them.
• Adding parallel channels between CPU and RAM reduces restrictions.
• Memory controllers support double channel implementation and greater memory to reduce CPU and RAM bottlenecks.
• Double channel memory is the coordination of two memory banks controlled to work as a synchronised set, doubling the specified system bus width from memory point of view during CPU communications.
• Triple channel memory requires coordinating three memory modules at once.
• Quad-channel memory requires four memory modules coordination.
• Multi-channel memory are known as implementations.
• Due to modern CPUs having largely 64-bit external data buses which a memory unit satisfies, there is a 1:1 relationship between modules and banks.
• Currently, multi-channel memory implementation requires installing two, three, or four memory modules.
• Motherboards, not memory, implements multi-channel memory.
• Single-channel memory is the classic memory model, requiring a complete bank be satisfied each time memory is added or installed initially.
• A single bank supplies half the effective bus width created by dual-channel support.
• By definition, dual channel pairs two banks. In nearly all instances, multi-channel implementations enables single-channel installation, but reduced performance should be expected.
• Multi-channel motherboards typically include different colored slots, usually one color for each slot set.
• Use same-color slots for a single channel.
• Fill adjacent slots on a dual-channel motherboard to use its dual-channel capability.
• Take caution when installing different memory modules because of special system memory subsystems “tricks” used for better overall system performance.
• At worst, a computer will stop working by modules of varying speeds, capacities, or amounts of sides situated in the same channel slots.
• The best practice for preventing issues is modules with identical parameters in matching is best.
• Problems can still occur when modules of two different and/or incompatible manufacturers are installed.
• Multi-channel support comes from the technology in the motherboard, not from memory composition.
• Some memory manufacturers package and sell memory pairs and triplets, to provide peace of mind when buying memory for multi-channel architecture systems.
• Motherboard memory slots, not memory modules, feature color-coding.

Memory Types

• Memory comes in a lot of formats where each has a set of traits that makes it a suitable application:
  • DRAM (dynamic random access memory).
  • ADRAM (asynchronous DRAM).
  • FPM DRAM (fast page mode DRAM).
  • EDO DRAM (extended data out DRAM).
  • BEDO DRAM (burst EDO DRAM).
  • SDRAM (synchronous DRAM).
  • SDR SDRAM (single data rate SDRAM).
  • DDR SDRAM (double data rate SDRAM).
  • DDR2 SDRAM (double data rate, version two SDRAM).
  • DDR3 SDRAM (double data rate, version three SDRAM).
  • DDR4 SDRAM (double data rate, version four SDRAM).
  • DDR5 SDRAM (double data rate, version five SDRAM).
  • SRAM (static random access memory).
  • ROM (read-only memory).

DDR Memory

• DDR1 (DDR): has 184 pins in the standard DIMM module.
• DDR2: introduced 240 pins to improve transfer capacity and performance over DDR1.
• DDR3: uses 240 pins, with improvements to transfer speed and energy efficiency.
• DDR4: also has 288 pins, with a more efficient design and higher transfer capacities and frequency.
• DDR5: keeps the DDR4 288 pins, with enhancements to bandwidth and density capacity.

DDR4 Speed

• Some terms used when considering DDR4 speeds include, clock speed.
• Clock Speed (MHz) is the frequency of the DDR4 memory clock.
• Bandwidth (GB/s) is the memory bandwidth, calculated as Clock Speed x 2 (for being DDR) x 8 (per byte).
• Speed Rating is the DDR4 memory nominal speed.
• PC Speed ​​Rating is the theoretical maximum performance value, calculated as Clock Speed ​​x 2 x 8.
• The "n" in Prefetch 8n represents the internal cycles in which grouped data words are sent to the external bus.
• In DDR4, this is 8, meaning the memory extracts 8 words in a single access to cells, optimizing transmission speed.
• If a DDR4-3200 memory works with a 1600 MHz data bus, its real internal frequency is 1600 MHz ÷ 8 (Prefetch 8n) = 200 MHz.
• Due to the Prefetch of 8n, each internal cycle extracts 8 data words, ensuring the effective transfer rate reaches 3200MT/s.
• Internal access to DDR memory cells is slower than bus transfer.
• DDR memory extracts several words of data in a single internal cycle and stores them in a prefetch buffer from where they are sent to the external bus at a higher speed.
• The "n" value indicates the number of grouped data words in each access cycle to the memory cells.
  • DDR → Prefetch 2n → 2 words are read in a single internal cycle.
  • DDR2 → Prefetch 4n → 4 words are read in a single internal cycle.
  • DDR3 → Prefetch 8n → 8 words are read in a single internal cycle.
  • DDR4 → Prefetch 8n → Same as DDR3, but more energy efficient and uses less power.
  • DDR5 → Prefetch 16n → 16 words are read in a single internal cycle, doubling DDR4.