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Questions and Answers
What is the maximum clock speed of DDR3?
What is the maximum clock speed of DDR3?
How many DRAM chips can a DIMM contain?
How many DRAM chips can a DIMM contain?
What is the voltage reduction from DDR1 to DDR2?
What is the voltage reduction from DDR1 to DDR2?
What is the primary concern in the design of SRAM?
What is the primary concern in the design of SRAM?
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How is the address multiplexing managed in DRAM?
How is the address multiplexing managed in DRAM?
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What is the main difference between DRAM and SDRAM?
What is the main difference between DRAM and SDRAM?
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What is the benefit of using memory interleaving?
What is the benefit of using memory interleaving?
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What is the purpose of the activate command (ACT) in DRAM?
What is the purpose of the activate command (ACT) in DRAM?
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What is the maximum expected clock rate of DDR4?
What is the maximum expected clock rate of DDR4?
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What is the characteristic that distinguishes ROM from EEPROM?
What is the characteristic that distinguishes ROM from EEPROM?
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How are commands and block transfers synchronized in DRAM?
How are commands and block transfers synchronized in DRAM?
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What is the effect of quadrupling the memory bus width on performance?
What is the effect of quadrupling the memory bus width on performance?
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What is the organization of modern DRAM?
What is the organization of modern DRAM?
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What is the purpose of refreshing data in DRAM?
What is the purpose of refreshing data in DRAM?
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What is the primary advantage of using SRAM for cache?
What is the primary advantage of using SRAM for cache?
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What is the formula to calculate the effective cycle time (EC) in memory interleaving?
What is the formula to calculate the effective cycle time (EC) in memory interleaving?
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What is the primary reason for a longer access time in a memory system?
What is the primary reason for a longer access time in a memory system?
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What is the typical form factor of a memory module?
What is the typical form factor of a memory module?
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What is the purpose of memory interleaving?
What is the purpose of memory interleaving?
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What is the calculation for the DRAM clock rate of DDR1?
What is the calculation for the DRAM clock rate of DDR1?
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What is the main function of virtual memory?
What is the main function of virtual memory?
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What is the term for the process of translating virtual addresses to physical addresses?
What is the term for the process of translating virtual addresses to physical addresses?
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What is the purpose of a page fault in virtual memory?
What is the purpose of a page fault in virtual memory?
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What is the benefit of memory space sharing in virtual memory?
What is the benefit of memory space sharing in virtual memory?
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What is a limitation of DRAM storage that requires periodic refreshes?
What is a limitation of DRAM storage that requires periodic refreshes?
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What is the primary reason for non-uniform access times in DRAM?
What is the primary reason for non-uniform access times in DRAM?
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How do bits in a row get updated in DRAM?
How do bits in a row get updated in DRAM?
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What is the function of the row buffer in DRAM?
What is the function of the row buffer in DRAM?
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Why do reads from DRAM require a write back?
Why do reads from DRAM require a write back?
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What is the primary advantage of using a single transistor in DRAM storage?
What is the primary advantage of using a single transistor in DRAM storage?
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What is the RAS precharge phase responsible for in DRAM?
What is the RAS precharge phase responsible for in DRAM?
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What is the CAS latency phase responsible for in DRAM?
What is the CAS latency phase responsible for in DRAM?
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What is the primary function of the RAS_L signal in a DRAM read cycle?
What is the primary function of the RAS_L signal in a DRAM read cycle?
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What is the significance of the 'L' in the signal names, such as RAS_L?
What is the significance of the 'L' in the signal names, such as RAS_L?
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What happens during the write access time in a DRAM write cycle?
What happens during the write access time in a DRAM write cycle?
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What is the purpose of the OE_L signal in a DRAM read cycle?
What is the purpose of the OE_L signal in a DRAM read cycle?
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What is the advantage of using memory interleaving?
What is the advantage of using memory interleaving?
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What is the relationship between the row address and column address in a DRAM?
What is the relationship between the row address and column address in a DRAM?
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What is the significance of the CAS_L signal in a DRAM read cycle?
What is the significance of the CAS_L signal in a DRAM read cycle?
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What is the purpose of Figure 4.14?
What is the purpose of Figure 4.14?
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The tag field in a cache block is used to indicate the block data validity and also to mark the memory address to which the cache block corresponds.
The tag field in a cache block is used to indicate the block data validity and also to mark the memory address to which the cache block corresponds.
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In a fully associative cache, only one block frame is checked for a hit, and only that block index can be replaced.
In a fully associative cache, only one block frame is checked for a hit, and only that block index can be replaced.
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The FIFO replacement strategy is a more complex and accurate method of predicting future block usage compared to the LRU strategy.
The FIFO replacement strategy is a more complex and accurate method of predicting future block usage compared to the LRU strategy.
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The random replacement strategy aims to reduce the chance of throwing out some data that is likely to be needed soon.
The random replacement strategy aims to reduce the chance of throwing out some data that is likely to be needed soon.
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The LRU replacement strategy is the simplest and most inexpensive method of cache replacement.
The LRU replacement strategy is the simplest and most inexpensive method of cache replacement.
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The direct mapped cache organization is the most flexible and adaptable method of cache organization.
The direct mapped cache organization is the most flexible and adaptable method of cache organization.
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In a k-way set associative cache, there are $k^2$ ways in the cache.
In a k-way set associative cache, there are $k^2$ ways in the cache.
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The random replacement strategy always has the lowest miss number in all cache sizes.
The random replacement strategy always has the lowest miss number in all cache sizes.
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The strategy of reading the tag and the block simultaneously can be applied to writes.
The strategy of reading the tag and the block simultaneously can be applied to writes.
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Writes dominate processor cache accesses.
Writes dominate processor cache accesses.
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A cache miss always results in a benefit.
A cache miss always results in a benefit.
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The LRU replacement strategy is the best in all cache sizes.
The LRU replacement strategy is the best in all cache sizes.
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Cache replacement policies are only used in virtual memory.
Cache replacement policies are only used in virtual memory.
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The main difference between cache memory and virtual memory is the cache size.
The main difference between cache memory and virtual memory is the cache size.
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In a fully associative cache, a block has only one place it can appear in the cache.
In a fully associative cache, a block has only one place it can appear in the cache.
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In a direct mapped cache, a block can be placed in a restricted set in the cache.
In a direct mapped cache, a block can be placed in a restricted set in the cache.
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A two-way set associative cache with eight blocks means that each set has two blocks.
A two-way set associative cache with eight blocks means that each set has two blocks.
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In a set associative cache, the block address is mapped onto a set using the equation (Block Address) mod (# of Blocks in Cache).
In a set associative cache, the block address is mapped onto a set using the equation (Block Address) mod (# of Blocks in Cache).
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Fully associative caches are simpler to implement than direct mapped caches.
Fully associative caches are simpler to implement than direct mapped caches.
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Direct mapped caches have full flexibility in terms of block placement.
Direct mapped caches have full flexibility in terms of block placement.
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Study Notes
Memory Systems
- The cost of quadrupling the memory bus may become prohibitive and would not yield that much performance improvement.
- A 256-bit bus without interleaving would give an effective cycle of 2.92, resulting in a speedup of just 1.06 with respect to the memory interleaving configuration of 4 banks.
RAM Construction Technology
- ROM is a non-volatile memory that can be written just once, with some variations being electronically erased and reprogrammed at slow speed (EEPROM).
- SRAM prioritizes speed and capacity, with data not needing to be refreshed periodically, and is about 8 to 16 times more expensive than DRAM.
- DRAM prioritizes cost per bit and capacity, with data needing to be refreshed periodically, and has multiplexed address lines.
Memory Modules
- Memory modules are used in the form factor of DIMM with 4 to 16 memory chips in a 64-bit bus to facilitate handling and exploit memory interleaving.
- The number of pins varies among different DDRn.
Virtual Memory
- Virtual memory automatically manages the two levels in the memory hierarchy represented by the main memory and the secondary storage (disk or flash).
- Virtual memory provides memory space sharing and protection, and memory relocation.
- The focus on virtual memory is specific to the computer architecture point of view, with concepts analogous to caches.
DDR SDRAM
- DDR SDRAM was an innovation where memory data is transferred on both rising and falling edges of the SDRAM clock signal, thereby increasing the data transfer rate.
- DDR technology has evolved with increased clock rates and voltage reduction in chips, from DDR1 to DDR5.
DRAM Organization
- Modern DRAM is organized in banks with up to 16 banks in the DDR4, with each bank having a number of rows.
DRAM Operation
- The DRAM controller manages address multiplexing by sending bank and row numbers followed by the column address, and finally, the data is accessed for a reading or a writing process.
- The activate command (ACT) opens a bank and a row, and loads the entire row into the row buffer.
- The precharge command (PRE) closes the bank and row and prepares it for a new access.
DRAM Performance
- DRAM performance is affected by non-uniform access time due to data location and the refresh/write back requirement.
- The time is divided into: (i) RAS precharge, (ii) RAS-to-CAS delay, (iii) CAS latency, and (iv) cycle time.
Cache Memory Organization
- The tag field in a cache block includes an additional bit to indicate the block's data validity, also known as the valid bit.
- Tags are searched in parallel for speed purposes.
Block Replacement
- In the case of a cache miss, the cache controller selects a block to be replaced with the required new data.
- There are three main replacement strategies: random, least recently used (LRU), and first-in, first-out (FIFO).
- Random replacement aims to spread allocation uniformly by randomly selecting candidate blocks.
- LRU replacement keeps track of block accesses to reduce the chance of throwing out data likely to be needed soon.
- FIFO replacement determines the oldest block rather than the least recently used block.
Block Placement
- Cache organizations can be fully associative, direct mapped, or set associative.
- In fully associative caches, a block can be placed anywhere in the cache.
- In direct mapped caches, each block has only one place it can appear in the cache, determined by Equation (4.1).
- In set associative caches, a block can be placed in a restricted set in the cache, determined by Equation (4.2).
- A block is first mapped onto a set and then placed anywhere within that set.
Cache Organization Comparison
- Table 4.1 shows pros and cons of different cache organization aspects, including fully associative, direct mapped, and set associative caches.
- Fully associative caches offer full flexibility but have high complexity and implementation cost.
- Direct mapped caches are simple but may have possible inefficiency due to inflexibility.
- Set associative caches are a compromise between flexibility and complexity.
Write Strategy
- Writes are approximately 10% of the memory traffic.
- Reads dominate processor cache accesses, and enhancing read performance is crucial.
- Blocks can be read from the cache at the same time the tag is read and compared.
- In case of a hit, the requested part of the block is given to the processor immediately.
- The write strategy cannot be applied in the same way as the read strategy since the tag must be checked to confirm whether the address is a hit.
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Description
Calculate the effective cycle time for a 256-bit memory bus without interleaving, and discuss the cost and performance implications of increasing memory bus width.
