8086 Instruction Set Quiz

8086 Instruction Set

• 8086 instructions are categorized into the following main types:
  • Data copy /transfer instructions
  • Arithmetic and Logical instructions
  • Branch Instructions
  • Loop instructions
  • Machine control instructions
  • Flag manipulation instructions
  • Shift and Rotate instructions
  • String manipulation instructions

Data Transfer Instructions

• XCHG (Exchange): exchanges contents of specified source and destination operands which may be registers or a memory location
  • Syntax:
    • XCHG AX, reg 16 (e.g., XCHG AX, DX)
    • XCHG mem, reg (e.g., XCHG [BX], DX)
    • XCHG reg, reg (e.g., XCHG AL, CL, XCHG DX, BX)
• IN (Input the Port): reads an input port
  • AL and AX are allowed destinations for 8 and 16-bit input operations
  • DX register (implicit) carries the port address
  • Syntax:
    • IN AL, DX ([AL]  [PORT DX])
    • IN AX, DX ([AX]  [PORT DX])
    • IN AL, PORT ([AL] [PORT])
    • IN AX, PORT ([AX][PORT])
    • IN AL, 0300H (reads data from an 8-bit port whose address is 0300H and stores it in AL)
    • IN AX (reads data from a 16-bit port whose address is in DX and stores it in AX)
• OUT (Output to the Port): writes to an output port
  • DX register may carry the port address directly or implicitly
  • Contents of AX or AL are transferred to a directly or indirectly addressed port after execution
  • Syntax:
    • OUT DX, AL ([PORT DX]  [AL])
    • OUT DX, AX ([PORT DX]  [AX])
    • OUT PORT, AL ([PORT]  [AL])
    • OUT PORT, AX ([PORT]  [AX])
    • OUT 0300H, AL (writes the content of AL to an 8-bit port with address 0300H)
    • OUT AX (writes the content of AX to a 16-bit port whose address is in DX)

Arithmetic Instructions

• SUB (Subtract): subtracts the source operand from the destination operand
  • The result is stored in the destination operand
  • Syntax: SUB dest, src (e.g., SUB AL, CH)
• DAS (Decimal Adjust After Subtraction): adjusts the result of subtraction to produce a valid packed BCD (Binary Coded Decimal) value
  • Syntax: DAS
• NEG (Negate): forms the 2’s complement of the specified destination operand
  • Subtracts the contents of the destination from zero
  • The result is stored back in the operand
  • Affects all condition code flags
  • Syntax: NEG dest (e.g., NEG AX)
• CBW (Convert Signed Byte to Word): converts a signed byte to a signed word
  • Copies the sign bit of the byte to all the bits in the higher byte of the result word
  • The byte to be converted must be in AL
  • The result will be in AX
  • It does not affect any flag
  • Syntax: CBW
• CWD (Convert Signed Word to Double Word): copies the sign bit of AX to all the bits of DX register
  • Used before signed division
  • It does not affect any other flag
  • Syntax: CWD

Logical Instructions

• AND (Logical AND): performs a bit by bit AND operation on the source and destination operands
  • The result is stored in the destination operand
  • Syntax:
    • AND mem/reg1, mem/reg2 (e.g., AND BL, CH)
    • AND mem,data (e.g., AND start,05H)
    • AND A, data (e.g., XOR AX, 1021H) - where A: AL/AX
• OR (Inclusive OR): performs a bit by bit OR operation on the source and destination operands
  • The result is stored in the destination operand
  • Syntax:
    • OR mem/reg1, mem/reg2 (e.g., OR BL, CH)
    • OR mem,data (e.g., OR start,05H)
    • OR A, data (e.g., OR AX, 1021H) - where A: AL/AX
• NOT (Logical NOT): performs a bit by bit NOT operation on the destination operand
  • The result is stored in the designation operand
  • Syntax: NOT dest (e.g., NOT AX)
• XOR (Exclusive OR): performs a bit by bit XOR operation on the source and destination operands
  • The result is stored in the destination operand
  • Syntax:
    • XOR mem/reg1, mem/reg2 (e.g., XOR BL, CH)
    • XOR mem,data (e.g., XOR start,05H)
    • XOR A, data (e.g., XOR AX, 1021H) - where A: AL/AX
• CMP (Compare): subtracts the source operand from the destination operand without storing the result
  • Affects the flags based on the subtraction result
  • Syntax:
    • CMP mem/reg1, mem/reg2 (e.g., CMP CX, BX)
    • CMP mem/reg, data (e.g., CMP CH, 03H)
    • CMP A, data (e.g., CMP AX, 1301H) - where A: AL/AX
• TEST (Logical Compare Instruction): performs a bit by bit logical AND operation on the two operands
  • The result of the AND operation is not stored
  • Affects the flags based on the result
  • Syntax:
    • TEST mem/reg1, mem/reg2 (e.g., Test CX,BX)
    • TEST mem/reg, data (e.g., TEST CH, 03H)
    • TEST A, data (e.g., TEST AX, 1301H) - where A: AL/AX

Shift Instructions

• SHL/SAL (Shift Logical/Arithmetic Left): shifts the operand word or byte bit by bit to the left
  • Inserts zeros in the newly introduced least significant bits
  • The count is either 1 or specified by register CL
  • Syntax: SHL/SAL dest, count (e.g., SHL AX, 1)
• SHR (Shift Right): shifts the operand word or byte bit by bit to the right
  • Inserts zeros in the newly introduced most significant bits
  • The count is either 1 or specified by register CL
  • Syntax: SHR dest, count (e.g., SHR AX, 1)
• SAR (Shift Arithmetic Right): shifts the operand word or byte bit by bit to the right
  • Copies the sign bit to the newly introduced most significant bits
  • The count is either 1 or specified by register CL
  • Syntax: SAR dest, count (e.g., SAR AX, 1)

Branch Instructions

• Transfer execution control to specified address
• Short Jump: displacement must lie within – 80H to 7FH (or –128 to 127) bytes from the address of the branch instruction
• Conditional Branch Instructions:
  • JZ/JE (Transfer control if ZF=1 (Zero Flag))
  • JNZ/JNE (Transfer control if ZF=0)
  • JS (Transfer control if SF=1 (Sign Flag))
  • JNS (Transfer control if SF=0)
  • JO (Transfer control if OF=1 (Overflow Flag))
  • JNO (Transfer control if OF=0)
  • JP/JPE (Transfer control if PF=1 (Parity Flag))
  • JNP (Transfer control if PF=0)
  • JB/JNAE/JC (Transfer control if CF=1 (Carry Flag))
  • JNB/JNE/JNC (Transfer control if CF=0)
  • JBE/JNA (Transfer control if CF=1 or ZF=1)
  • JNBE/JA (Transfer control if CF=0 or ZF=0)
  • JL/JNGE (Transfer control if neither SF=1 nor OF=1)
  • JNL/JGE (Transfer control if neither SF=0 nor OF=0)
  • JNE/JNC (Transfer control if ZF=1 or neither SF nor OF is 1)
  • JNLE/JE (Transfer control if ZF=? or at least any are of SF & OF is 1)