80386 Microprocessor Initial States

• 80386 microprocessor, also known as the i386, is a popular x86-based microprocessor
• The processor state after reset is critical for both the processor and the entire system, affecting system configuration and operation

EAX Register

• Contents depend on power-up self-test results
• If the self-test is requested via the BUSY# signal, EAX holds a value of zero if the 80386 passes the test
• A non-zero value in EAX after the self-test indicates a faulty 80386 unit
• EAX contents are undefined if the self-test is not requested

DX Register

• Holds a component identifier and revision number after RESET
• DH contains the value 3, indicating the 80386
• DL contains a unique identifier of the revision level

CR0 Register

• Contains specific values after reset including the ET bit
• ET bit indicates if an 80387 coprocessor is present in the configuration
• If ET bit is reset, the configuration either contains an 80287 coprocessor or no coprocessor at all

Initial Register Values

• EFLAGS = 00000002H

• IP = 0000FFF0H

• CS selector = 0000H

• DS selector = 0000H

• ES selector = 0000H

• SS selector = 0000H

• FS selector = 0000H

• GS selector = 0000H

• IDTR: base = 0, limit = 03FFH

• The processor's state after reset, and specific register contents, are critical for system designers and software developers

Read Cycle with Non-Pipelined Address Timing

• Involves a series of steps starting with the processor requesting data from memory
• The processor sends the memory location address to the address lines
• The processor asserts the address strobe signal to confirm the address lines are valid
• The processor sets the Read/Write signal to "read"
• The processor asserts the data strobe signal so memory can read the data
• Memory decodes the address and sends the data to the data lines
• Memory sends the data acknowledge signal to the processor
• The processor latches in the data and negates the data strobe signal
• The processor negates the address strobe signal
• Memory negates the data acknowledge signal

Control Registers of 80386

• Intel386 DX has three 32-bit control registers: CR0, CR2, and CR3
• These registers hold the machine state in a global sense
• System Address Registers hold machine state affecting all tasks in the system
• Load and store instructions are used to access Control Registers

CR0: Machine Control Register

• Contains 6 defined bits for control and status purposes
• The low-order 16 bits of CR0 is defined as the Machine Status Word
• Can use MOV CR0, Reg instruction for 32-bit operations
• The 6 defined bits for control and status purposes are:
• PE (Protection Enable) bit: Enables Protected Mode when set
• MP (Monitor Coprocessor / Math Present) bit: If MP=1, assumes a real floating-point hardware
• EM (Emulate Coprocessor) bit: When set, causes coprocessor opcodes to generate a Coprocessor Not Available fault (exception 11)
• TS (Task Switched) bit: Set whenever a task switch operation is performed
• ET (Extension Type): Informs the 80386 whether the numeric coprocessor is an 80387

CR1, CR2, CR3

• CR1: Reserved and not used in 80386
• CR2: Page Fault Linear Address Register, stores the linear address that caused the most recent page fault
• Used for debugging and exception handling during invalid memory access
• The linear address is the address in virtual memory
• CR3: Page Directory Base Register, holds the physical address of the page directory.
• The page directory is part of the paging mechanism
• Contains 32-bit entries that point to page tables
• These page tables contain physical addresses of the memory pages
• Bit 31-12: Base address of the page directory
• Bit 11-0: Reserved

Control Register Usage Summary

• CR0: Controls the major modes of operation (paging, protected mode, and FPU behavior)
• CR1: Not used
• CR2: Stores the address that caused a page fault
• CR3: Contains the address of the page directory

Signals

• INTR (Interrupt Request): An active-low signal used by external devices to request an interrupt.
• ADS# (Address Strobe): An active-low signal indicating the address bus holds a valid address.
• READY#: An active-low signal indicating whether external devices are ready for data transfer.
• HOLD: An active-low signal used in Direct Memory Access (DMA) operations.
• NMI (Non-Maskable Interrupt): An active-low signal used for high-priority interrupts that cannot be disabled

Debug Registers

• The Intel 80386 microprocessor features Debug Registers
• Uses Debug Registers for controlling and monitoring the processor's behavior during debugging operations
• Contains 8 debug registers in the 80386, including DR0 to DR7
• Used for setting breakpoints, controlling the processor's behavior, and monitoring specific conditions during execution

Debug Registers List

• DR0 - DR3: Breakpoint Address Registers
• Hold the linear address where the processor will stop if a specific debug condition is met
• DR0 thru DR3 hold 32-bit linear addresses for the breakpoints
• A breakpoint is set when the contents of these registers match the address being executed
• DR4 and DR5: Reserved, and should not be used by software
• DR6: Debug Status Register
• Holds the status information regarding the last breakpoint or debug exception
• Provides details about which debug condition caused the exception
• Bit 0 (BD): Breakpoint Detect, 1: A breakpoint condition has been detected, 0: No breakpoint detected
• Bit 1 (BS): Single Step, 1: A single-step exception occurred, 0: No single-step exception
• Bits 2-3 (BT): Reserved, Bits 4-7: Reserved, Bits 8-31: Reserved for future use
• DR7: Debug Control Register
• DR7 controls the conditions under which the processor generates a debug exception
• Enables/disables breakpoints and specifies conditions under which a breakpoint should trigger
• Bits 0-3 (L0-L3): Enable or disable breakpoints for DR0 to DR3 (1: Enable, 0: Disable)
• Bits 4-7 (G0-G3): Specifies the condition under which the breakpoints will trigger
• 0: Trigger on an instruction execution
• 1: Trigger on a data access (read/write)
• 2: Trigger on write access
• 3: Trigger on read access
• Bits 8-11 (LE0-LE3): Defines memory access size (1-byte, 2-byte, 4-byte, etc.)
• Bit 13: Reserved Bits 14-15: Reserved

Debug Registers Summary

• DRO to DR3: Stores the addresses for breakpoints
• DR6: Provides the status of the last debug exception
• DR7: Controls enabling/disabling breakpoints and defines trigger conditions
• Usage: Debugging purposes, halt execution, analyze the processor or program state

Write Cycle

• In a non-pipelined write cycle, the CPU performs write operations sequentially
• Address Phase: CPU places the address of memory or I/O location on the address bus
• ADS# (Address Strobe) signal is activated when the address is valid
• Control Phase: MW (Memory Write) or IOW (I/O Write) signal is asserted
• Specifies the write operation type. Signals written data to memory or an I/O device
• Data Phase: The CPU places the data to be written on the data bus
• MW or IOW control signals ensure the data is correctly written
• Ready Signal: The READY# signal informs the CPU when the operation is complete
• The READY# is asserted when the device is ready

Signals Explained

• BEO# - BE3# (Byte Enable Signals)
• Function: Specify bytes in a word accessed during read or write operations.
• Behavior: Active-low signals for each byte (0-3) in a 32-bit word
• ADS# (Address Strobe)
• Function: Indicates a valid address on the address bus, and the CPU is ready for memory or I/O access
• Behavior: Active-low signal, triggers when asserted low, signals CPU has placed a valid address
• D/C# (Data/Control)
• Function: Differentiates between data and control operations
• Behavior: Low indicates a data operation. High indicates a control operation
• W/R# (Write/Read)
• Function: Indicates the direction of data transfer (write or read)
• Behavior: Low indicates a write operation. High indicates a read operation
• BS16# (Bus Size 16-bit)
• Function: Indicates the size of the data bus for a particular operation (16-bit or 32-bit)
• Behavior: Low indicates a 16-bit data bus. High indicates a 32-bit operation

System Flags

• NT (Nested Task Flag)
• Controls task switching by indicating if the current task is a nested task
• 1: NestedTask, 0: Not NestedTask
• IOPL (I/O Privilege Level)
• A 2-bit field that specifies the privilege level for I/O operations
• 00 is Highest, 11 is Lowest
• IF (Interrupt Enable Flag)
• Controls whether interrupts are being enabled or disabled
• Is 1 when Enabled and 0 when Disabled
• VM (Virtual Mode Flag)
• Enables/disables virtual 8086 mode for running real-mode programs in protected mode
• 1:Enabled 0:Disabled
• RF (Resume Flag)
• Controls whether the CPU can resume execution after a debug exception.
• 1 allows normal execution. 0 triggers a debug exception on the next instruction

EFLAGS Registers and Logical Addresses

• EFLAGS register, 32-bit register, functions as the flags register
• FLAGS is the name given to the low-order 16 bits of EFLAGS and can be treated as a unit for running 8086 and 80286 programs
• There are three categories of flags: status, control, and system

Status Flags

• Reflect the status of a particular program
• CF (Carry Flag): Generated by arithmetic instructions that result in a carry or borrow
• PF (Parity Flag): Set if the least significant 8-bit of the operation has an even number of ones
• AF (Auxiliary Carry Flag): Set when there is a carry or borrow after a nibble addition or subtraction
• ZF (Zero Flag): Set to 1 if result is 0
• SF (Sign Flag): The MSB indicates the sign of a number
• OF (Overflow Flag): It is set if a signed operation's result is too large

Control Flags

• Directly affects the operation of a few instructions
• DF (Direction Flag): Controls the direction of string operations, cleared processes strings from low to high

System Flags

• Reflect the current status of the machine, used by the operating systems
• VM (Virtual Memory) flag : Indicates the operating mode, set the 80386 switches to virtual 8086 modes
• R (Resume) flag/Restart : Allows selective masking of some exceptions during debugging
• NT (Nested) flag: Is set when one task invokes another
• IOPL (I/O Privilege) Level : Determines your application's to I/O facilities
• IF (Interrupt Flag): set that the 80386 handles external hardware interrupts
• TF (Trap Flag) : Allows users to single-step through programs

Address Translation

• 80386 transforms logical addresses into physical addresses using two steps
• Segment translation: a logical address is converted into a linear address
• Page translation: a linear address is converted into a physical address (optional)

Logical Address Structure

• Consists of a segment selector and an offset within that segment
• Used by the programmer
• Segment Translation:
• Segment selector is used to access a segment table entry with the base address of the segment
• Offset is added to the base address to create the linear address
• Linear Address:
• Intermediate address from segment translation
  • Page Translation:
• Linear address is divided into a page number and an offset within that page.
• Page number accesses a page table entry that contains the corresponding physical frame number

Physical Address

• The physical frame number is combined with the offset to form the final physical address
• Components Involved:
• Segment Table: Stores base addresses and info about each segment
• Page Directory: Points to individual page tables, hierarchical address translation
• Page Table: Maps individual page numbers to physical frame numbers
• Translation Lookaside Buffer (TLB): Cache that stores used page table entries to translated address