(The Morgan Kaufmann Series in Computer Architecture and Design) David A. Patterson, John L. Hennessy - Computer Organization and Design RISC-V Edition_ The Hardware Software Interface-Morgan Kaufmann-24-101-24-27.pdf

1.5 Technologies for Building Processors and Memory 25 Technologies for Building Processors 1.5 and Memory Processors and memory have improved at an incredible rate, because computer design...

1.5 Technologies for Building Processors and Memory 25 Technologies for Building Processors 1.5 and Memory Processors and memory have improved at an incredible rate, because computer designers have long embraced the latest in electronic technology to try to win the race to design a better computer. Figure 1.10 shows the technologies that have been used over time, with an estimate of the relative performance per unit cost for each technology. Since this technology shapes what computers will be able to do and how quickly they will evolve, we believe all computer professionals should be familiar with the basics of integrated circuits. transistor An on/off A transistor is simply an on/off switch controlled by electricity. The integrated circuit switch controlled by an (IC) combined dozens to hundreds of transistors into a single chip. When Gordon electric signal. Moore predicted the continuous doubling of resources, he was forecasting the growth very large-scale rate of the number of transistors per chip. To describe the tremendous increase in the integrated (VLSI) number of transistors from hundreds to millions, the adjective very large scale is added circuit A device to the term, creating the abbreviation VLSI, for very large-scale integrated circuit. containing hundreds of This rate of increasing integration has been remarkably stable. Figure 1.11 shows thousands to millions of the growth in DRAM capacity since 1977. For 35 years, the industry has consistently transistors. quadrupled capacity every 3 years, resulting in an increase in excess of 16,000 times! Figure 1.11 shows the slowdown due to the slowing of Moore’s Law; quadrupling capacity has taken six years recently. silicon A natural To understand how to manufacture integrated circuits, we start at the beginning. element that is a The manufacture of a chip begins with silicon, a substance found in sand. Because semiconductor. silicon does not conduct electricity well, it is called a semiconductor. With a special chemical process, it is possible to add materials to silicon that allow tiny areas to semiconductor transform into one of three devices: A substance that does not Excellent conductors of electricity (using either microscopic copper or conduct electricity well. aluminum wire) Excellent insulators from electricity (like plastic sheathing or glass) Areas that can conduct or insulate under specific conditions (as a switch) Transistors fall into the last category. A VLSI circuit, then, is just billions of combinations of conductors, insulators, and switches manufactured in a single small package. 1951 Vacuum tube 1 1965 Transistor 35 1975 Integrated circuit 900 1995 Very large-scale integrated circuit 2,400,000 2020 Ultra large-scale integrated circuit 500,000,000,000 FIGURE 1.10 Relative performance per unit cost of technologies used in computers over time. Source: Computer Museum, Boston, with 2013 extrapolated by the authors. See Section 1.13. 26 Chapter 1 Computer Abstractions and Technology 100,000,000 10,000,000 16G 8G 1,000,000 4G 1G 2G Kibibit capacity 100,000 256M 512M 16M 128M 64M 10,000 4M 1M 1000 256K 64K 100 16K 10 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 Year of introduction FIGURE 1.11 Growth of capacity per DRAM chip over time. The y-axis is measured in kibibits (210 bits). The DRAM industry quadrupled capacity almost every three years, a 60% increase per year, for 20 years. In recent years, the rate has slowed down and is somewhat closer to doubling every three years. With the slowing of Moore’s Law and difficulties in reliable manufacturing of smaller DRAM cells given the challenging aspect ratios of their three-dimensional structure. silicon crystal ingot The manufacturing process for integrated circuits is critical to the cost of the A rod composed of a chips and hence important to computer designers. Figure 1.12 shows that process. silicon crystal that is between 8 and 12 inches The process starts with a silicon crystal ingot, which looks like a giant sausage. in diameter and about 12 Today, ingots are 8–12 inches in diameter and about 12–24 inches long. An ingot to 24 inches long. is finely sliced into wafers no more than 0.1 inches thick. These wafers then go through a series of processing steps, during which patterns of chemicals are placed wafer A slice from a silicon ingot no more than on each wafer, creating the transistors, conductors, and insulators discussed earlier. 0.1 inches thick, used to Today’s integrated circuits contain only one layer of transistors but may have from create chips. two to eight levels of metal conductor, separated by layers of insulators. Blank Silicon ingot wafers 20 to 40 Slicer processing steps Tested dies Tested Patterned wafers wafer Bond die to Wafer Dicer package tester Packaged dies Tested packaged dies Part Ship to tester customers FIGURE 1.12 The chip manufacturing process. After being sliced from the silicon ingot, blank wafers are put through 20 to 40 steps to create patterned wafers (see Figure 1.13). These patterned wafers are then tested with a wafer tester, and a map of the good parts is made. Next, the wafers are diced into dies (see Figure 1.9). In this figure, one wafer produced 20 dies, of which 17 passed testing. (X means the die is bad.) The yield of good dies in this case was 17/20, or 85%. These good dies are then bonded into packages and tested one more time before shipping the packaged parts to customers. One bad packaged part was found in this final test.  1.5 Technologies for Building Processors and Memory 27 A single microscopic flaw in the wafer itself or in one of the dozens of patterning defect A microscopic steps can result in that area of the wafer failing. These defects, as they are called, flaw in a wafer or in make it virtually impossible to manufacture a perfect wafer. The simplest way to patterning steps that can result in the failure of the cope with imperfection is to place many independent components on a single die containing that defect. wafer. The patterned wafer is then chopped up, or diced, into these components, called dies and more informally known as chips. Figure 1.13 shows a photograph die The individual of a wafer containing microprocessors before they have been diced; earlier, Figure rectangular sections that 1.9 shows an individual microprocessor die. are cut from a wafer, more Dicing enables you to discard only those dies that were unlucky enough to informally known as contain the flaws, rather than the whole wafer. This concept is quantified by the chips. yield of a process, which is defined as the percentage of good dies from the total number of dies on the wafer. yield The percentage of good dies from the total The cost of an integrated circuit rises quickly as the die size increases, due both number of dies on the to the lower yield and to the fewer dies that fit on a wafer. To reduce the cost, wafer. using the next generation process shrinks a large die as it uses smaller sizes for both transistors and wires. This improves the yield and the die count per wafer. A 7-nanometer (nm) process was state-of-the-art in 2020, which means essentially that the smallest feature size on the die is 7 nm. FIGURE 1.13 A 12-inch (300mm) wafer this 10nm wafer contains 10th Gen Intel® Core™ processors, code-named “Ice Lake” (Courtesy Intel). The number of dies on this 300 mm (12 inch) wafer at 100% yield is 506. According to AnandTech1, each Ice Lake die is 11.4 by 10.7 mm. The several dozen partially rounded chips at the boundaries of the wafer are useless; they are included because it’s easier to create the masks used to pattern the silicon. This die uses a 10-nanometer technology, which means that the smallest features are approximately 10 nm in size, although they are typically somewhat smaller than the actual feature size, which refers to the size of the transistors as “drawn” versus the final manufactured size. 28 Chapter 1 Computer Abstractions and Technology Once you’ve found good dies, they are connected to the input/output pins of a package, using a process called bonding. These packaged parts are tested a final time, since mistakes can occur in packaging, and then they are shipped to customers. While we have talked about the cost of chips, there is a difference between cost and price. Companies charge as much as the market will bear to maximize return on investment, which must cover costs like a company’s research and development (R&D), marketing, sales, manufacturing equipment maintenance, building rental, cost of financing, pretax profits, and taxes. Margins can be higher on unique chips that come from only one company, like microprocessors, versus chips that are commodities supplied by several companies, like DRAMs. The price fluctuates based on the ratio of supply and demand, and it is easy for multiple companies to build more chips than the market demands. Elaboration: The cost of an integrated circuit can be expressed in three simple equations: Cost per wafer Cost per die Dies per wafer yield Wafer area Dies per waffer  Die area 1 Yield (1 (Defects per area Die area))N The first equation is straightforward to derive. The second is an approximation, since it does not subtract the area near the border of the round wafer that cannot accommodate the rectangular dies (see Figure 1.13). The final equation is based on empirical observations of yields at integrated circuit factories, with the exponent related to the number of critical processing steps. Hence, depending on the defect rate and the size of the die and wafer, costs are generally not linear in the die area. Check A key factor in determining the cost of an integrated circuit is volume. Which of Yourself the following are reasons why a chip made in high volume should cost less? 1. With high volumes, the manufacturing process can be tuned to a particular design, increasing the yield. 2. It is less work to design a high-volume part than a low-volume part. 3. The masks used to make the chip are expensive, so the cost per chip is lower for higher volumes. 4. Engineering development costs are high and largely independent of volume; thus, the development cost per die is lower with high-volume parts. 5. High-volume parts usually have smaller die sizes than low-volume parts and therefore, have higher yield per wafer.