SystemVerilog Introduction PDF

 Introduction Goal: Learn Verilog-based chip 1. 1995: Initial development design of Verilog began, integrating features from Verilog and other hardware description In particu...

 Introduction Goal: Learn Verilog-based chip 1. 1995: Initial development design of Verilog began, integrating features from Verilog and other hardware description In particular, we will talk about the languages. Hardware Description Language (HDL) SystemVerilog, which is a “superset” of Verilog: 2. 2005: IEEE 1800-2005 - The first – Verilog, IEEE standard (1364) in 1995 official standard for SystemVerilog was – SystemVerilog, extended in 2005, published, defining extensions to the current version is IEEE Standard 1800-2012 Verilog standard. The name “SystemVerilog” is 3. 2009: IEEE 1800-2009 - This revision confusing because it still describes included clarifications and enhancements hardware at the same level as to the language. “Verilog”, but SystemVerilog adds a number of enhancements and improved syntax. 4. 2012: IEEE 1800-2012 - Further updates were made to improve the SystemVerilog files have a “.sv” standard and address user feedback. extension so that the compiler knows that the file is in SystemVerilog 5. 2017: IEEE 1800-2017 - This version rather than Verilog. provided significant updates and was made available at no cost, enhancing the language's capabilities. 2  In Summary Learning SystemVerilog is highly beneficial for graduate students, especially those in electrical engineering, computer engineering, and related disciplines. Here are several compelling reasons to consider: Industry Relevance: SystemVerilog is widely used in the semiconductor and electronics industries for designing and verifying digital systems. Proficiency in this language can significantly enhance job prospects and career opportunities. Comprehensive Design and Verification: SystemVerilog combines the features of Verilog with advanced verification capabilities. This makes it a powerful tool for both designing hardware and verifying its functionality, which is crucial for developing reliable and efficient systems. Advanced Features: SystemVerilog includes features like object-oriented programming, assertions, and constrained random verification. These features enable more sophisticated and efficient design and verification processes. Academic and Research Applications: SystemVerilog is not only used in industry but also in academic research. It is essential for projects involving FPGA and ASIC implementations, making it a valuable skill for graduate students involved in research. Enhanced Learning Experience: Learning SystemVerilog provides a deeper understanding of digital system design and verification. It helps students grasp complex concepts and apply them in practical scenarios, enhancing their overall learning experience. Collaboration and Communication: Proficiency in SystemVerilog allows students to collaborate effectively with industry professionals and researchers. It also improves their ability to communicate technical ideas clearly and accurately. Future-Proofing Skills: As technology continues to evolve, the demand for skilled professionals in digital design and verification is expected to grow. Learning SystemVerilog ensures that students are well-prepared for future advancements in the field. These reasons highlight the importance of learning SystemVerilog for graduate students, providing them with valuable skills and knowledge that can significantly impact their academic and professional careers. References Advanced Digital System Design: A Practical Guide to Verilog... - Springer Free Classroom Resource: Introduction to SystemVerilog Getting Started with Verilog - GeeksforGeeks Let’s Get Started with SystemVerilog  Synthesis vs. Simulation Extremely important to understand that SystemVerilog is BOTH a “Synthesis” language and a “Simulation” language – Small subset of the language is “synthesizable”, meaning that it can be translated to logic gates and flip-flops. – SystemVerilog also includes many features for “simulation” or “verification”, features that have no meaning in hardware! Although SystemVerilog syntactically looks like “C”, it is a Hardware Description Language (HDL), NOT a software programming language – Every line of synthesizable SystemVerilog MUST have a direct translation into hardware (logic gates and flip flops). – Very important to think of the hardware that each line of SystemVerilog will produce. 5  SystemVerilog Modules SystemVerilog: module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Module Abstraction: a Verilog b y Module c de derived from slides by Harris & Harris from their book 6  HDL Synthesis SystemVerilog: module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Synthesis: translates into a netlist (i.e., a list of gates and flip-flops, and their wiring connections) b c y un5_y y * Schematic after a some logic optimization un8_y e derived from slides by Harris & Harris from their book 7  SystemVerilog Syntax Case sensitive – Example: reset and Reset are not the same signal. No names that start with numbers – Example: 2mux is an invalid name Whitespace ignored Comments: – // single line comment – de derived from slides by Harris & Harris from their book 8  Structural Modeling - Hierarchy module and3(input logic a, b, c, output logic y); assign y = a & b & c; endmodule module inv(input logic a, output logic y); assign y = ~a; endmodule module nand3(input logic a, b, c output logic y); logic n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverter endmodule de derived from slides by Harris & Harris from their book 9  Bitwise Operators module gates(input logic [3:0] a, b, output logic [3:0] y1, y2, y3, y4, y5); assign y1 = a & b; // AND assign y2 = a | b; // OR assign y3 = a ^ b; // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a | b); // NOR endmodule // single line comment multiline comment de derived from slides by Harris & Harris from their book 10  Reduction Operators module and8(input logic [7:0] a, output logic y); assign y = &a; // &a is much easier to write than // assign y = a & a & a & a & // a & a & a & a; endmodule de derived from slides by Harris & Harris from their book 11  Conditional Assignment module mux2(input logic [3:0] d0, d1, input logic s, output logic [3:0] y); assign y = s ? d1 : d0; endmodule ? : is also called a ternary operator because it operates on 3 inputs: s, d1, and d0. de derived from slides by Harris & Harris from their book 12  Precedence Order of operations Highest ~ NOT *, /, % mult, div, mod +, - add,sub shift arithmetic shift = comparison ==, != equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR |, ~| OR, NOR Lowest ?: ternary operator de derived from slides by Harris & Harris from their book 13  Adder Examples module fulladder(input logic a, b, cin, output logic s, cout); logic p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule s g s cin a cout b cout p un1_cout de derived from slides by Harris & Harris from their book 14  Adder Examples module h4ba(input logic [3:0] A, B, input logic carry_in, output logic [3:0] sum, output logic carry_out); logic carry_out_0, carry_out_1, carry_out_2; // internal signals fulladder fa0 (A, B, carry_in, sum, carry_out_0); fulladder fa1 (A, B, carry_out_0, sum, carry_out_1); fulladder fa2 (A, B, carry_out_1, sum, carry_out_2); fulladder fa3 (A, B, carry_out_2, sum, carry_out); endmodule each of these is an instantiation of “full_adder” 15  Adder Examples (Behavioral) module add4(input logic [3:0] A, B, output logic [3:0] sum); assign sum = A + B; endmodule Verilog compilers will replace arithmetic operators with default logic implementations (e.g. ripple carry adder) this expands into logic for a ripple carry adder 16  Numbers Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal) Number # Bits Base Decimal Stored Equivale nt 3'b101 3 binary 5 101 'b11 unsized binary 3 00…0011 8'b11 8 binary 3 00000011 8'b1010_1011 8 binary 171 10101011 3'd6 3 decimal 6 110 6'o42 6 octal 34 100010 8'hAB 8 hexadecimal 171 10101011 42 unsized decimal 42 00…0101010 de derived from slides by Harris & Harris from their book 17  DATA TYPES Possible L Data Synthesiza Example ogic Data Range Signed Type ble Values Bit bit a = 1'b0; 0, 1 0 to 1 Yes No Logic logic b = 1'bz; 0, 1, z, x 0 to 1, z, x Yes No Reg reg c; 0, 1, z, x 0 to 1, z, x Yes No - Integer integer d = 42; N/A 2^31 to 2^31 Yes Yes -1 Approx. ±1.7 * Real real e = 3.14; N/A No No 10^308 - Shortint shortint f = -12; N/A 2^15 to 2^15 Yes Yes -1 - longint g = Longint N/A 2^63 to 2^63 Yes Yes 100000; -1 byte h = Byte 0 to 255 0 to 255 Yes Yes 8'b10101100; Time time t = 10ns; N/A 0 to 2^63-1 No No string str = String N/A N/A No No "Hello";  DATA TYPES Possible Synthesiza Data Type Example Logic Data Range Signed ble Values Array N/A (depends int array1; N/A Yes Yes (Unpacked) on contents) Array logic [3:0] Depending on 0, 1, z, x Yes No (Packed) array2; size (e.g., 0-15) Signed logic signed [3:0] 0, 1, z, x -8 to 7 Yes Yes Logic signedLogic; struct { int a; logic Depends on Struct N/A Yes No b; } myStruct; fields union { int a; logic Depends on Union N/A Yes No b; } myUnion; fields enum {RED, 0 to 2 (or size of Enum GREEN, BLUE} N/A Yes No enum - 1) color; Logic No logic [3:0] vector; 0, 1, z, x 0 to 15 Yes Vector  Bit Manipulations: Example 1 assign y = {a[2:1], {3{b}}, a, 6'b100_010}; // if y is a 12-bit signal, the above statement produces: // y = a a b b b a 1 0 0 0 1 0 // underscores (_) are used for formatting only to make // it easier to read. SystemVerilog ignores them. concatenation de derived from slides by Harris & Harris from their book 20  Bit Manipulations: Example 2 module mux2_8(input logic [7:0] d0, d1, input logic s, output logic [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule mux2 s s [7:0] [3:0] [3:0] [7:0] d0[7:0] d0[3:0] y[3:0] y[7:0] [7:0] [3:0] d1[7:0] d1[3:0] lsbmux mux2 s [7:4] [7:4] d0[3:0] y[3:0] [7:4] d1[3:0] msbmux de derived from slides by Harris & Harris from their book 21  More Examples module ex1(input logic [3:0] X, Y, Z, input logic a, cin, output logic [3:0] R1, R2, R3, Q1, Q2, output logic [7:0] P1, P2, output logic t, cout); assign R1 = X | (Y & ~Z); use of bitwise Boolean operators assign t = &X; example reduction operator assign R2 = (a == 1’b0) ? X : Y; conditional operator assign P1 = 8’hff; example constants replication, same as {a, a, a, a} assign P2 = {4{a}, X[3:2], Y[1:0]}; example concatenation assign {cout, R3} = X + Y + cin; assign Q1 = X