Analog Electronic Circuits (UEC301) Lecture 3 & 4 Updated PDF

Analog Electronic Circuits (UEC301) By Dr. Jaswinder Kaur Assistant Professor-III, DECE,TIET,Patiala  Subject: Analog Electronic Circuits (UEC301) Topic of today’s Lecture : BJT Biasing-I Contents of...

Analog Electronic Circuits (UEC301) By Dr. Jaswinder Kaur Assistant Professor-III, DECE,TIET,Patiala  Subject: Analog Electronic Circuits (UEC301) Topic of today’s Lecture : BJT Biasing-I Contents of this lecture are based on the Key points following books:  Purpose of Transistor Biasing Jacob Milman & and C.C.Halkias, “Integrated  DC operating Points(i/p and o/p) Electronics Analog and Digital Circuit and Systems”Second Edition.  Effects of Bias point location on Adel S. Sedra & K. C. Smith, “MicroElectronic Allowable Signal Swing Circuits Theory and Application” Fifth Edition.  Stabilization against Variations in ICO Robert L. Boylestad & L. Nashelsky, “Electronic Devices and Circuit Theory” Eleventh Edition. and β  Methods of BJT DC Biasing- Fixed Bias Configuration  Q-POINT AND OUTPUT OF BIPOLAR JUNCTION TRANSISTOR The output signal of a transistor amplifier circuit depends on the Q-point in output characteristics. When the Q-point is located at the centre of the load line, the transistor amplifier circuit operates in linear zone and the undistorted signal will be output from the amplifier.  Q-POINT AND OUTPUT OF BIPOLAR JUNCTION TRANSISTOR When the Q-point is located near the saturation point, one peak of the output signal will be clipped. During the negative half-cycle of the input signal, the transistor is driven into saturation. Therefore, the negative peak of the input signal is clipped at the output signal as depicted.  Q-POINT AND OUTPUT OF BIPOLAR JUNCTION TRANSISTOR When the Q-point is located near the cut- off point, the transistor operates in cut-off region. Therefore, the positive peak of the input signal is clipped at the output as shown. Transistor Biasing The proper flow of zero signal collector current and the maintenance of proper collector-emitter voltage during the passage of signal is known as Transistor Biasing. The circuit which provides transistor biasing is called as Biasing Circuit. Need for DC biasing If a signal of very small voltage is given to the input of BJT, it cannot be amplified. Because, for a BJT, to amplify a signal, two conditions have to be met. The input voltage should exceed cut-in voltage for the transistor to be ON. The BJT should be in the active region, to be operated as an amplifier. If appropriate DC voltages and currents are given through BJT by external sources, so that BJT operates in active region and superimpose the AC signals to be amplified, then this problem can be avoided. The given DC voltage and currents are so chosen that the transistor remains in active region for entire input AC cycle. Hence DC biasing is needed. Factors affecting the operating point The main factor that affect the operating point is the temperature. The operating point shifts due to change in temperature. As temperature increases, the transistor parameters get affected. ICBO gets doubled (for every 10o rise) VBE decreases by 2.5mv (for every 1o rise) So the main problem which affects the operating point is temperature. Hence operating point should be made independent of the temperature so as to achieve stability. To achieve this, biasing circuits are introduced. Stabilization The process of making the operating point independent of temperature changes or variations in transistor parameters is known as Stabilization. Once the stabilization is achieved, the values of IC and VCE become independent of temperature variations.  Methods of BJT DC Biasing  Fixed Bias Configuration  Emitter Bias Configuration  Voltage Divider Bias Configuration  Collector Feedback Configuration  Emitter Follower Configuration  Fixed Bias Configuration The fixed-bias circuit is the simplest transistor dc bias configuration. Equations and calculations apply equally well to a pnp transistor configuration merely by changing all current directions and voltage polarities. For the dc analysis the network can be isolated from the indicated ac levels by replacing the capacitors with an open-circuit equivalent because the reactance of a capacitor is a function of the applied frequency.  Transistor Saturation The term saturation is applied to any system where levels have reached their maximum values For a transistor operating in the saturation region, the current is a maximum value for the particular design. Of course, the highest saturation level is defined by the maximum collector current Saturation conditions are normally avoided because the base–collector junction is no longer reverse-biased and the output amplified signal will be distorted Note that it is in a region where the characteristic curves join and the collector-to-emitter voltage is at or below VCE(sat). In addition, the collector current is relatively high on the characteristics Once saturation current is known, we have some idea of the maximum possible collector current for the chosen design and the level to stay below if we expect linear amplification  Load-Line analysis The load-line solution for a BJT has been found by superimposing the actual BJT characteristics on a plot of the network equation involving the same network variables. The intersection of the two plots defined the actual operating conditions for the network. It is referred to as load-line analysis because the load (network resistors) of the network defined the slope of the straight line connecting the points defined by the network parameters. The load resistor for the fixed-bias configuration will define the slope of the network equation and the resulting intersection between the two plots. The smaller the load resistance, the steeper the slope of the network load line.  Emitter Bias Configuration The dc bias network of Fig. 17 contains an emitter resistor to improve the stability level over that of the fixed-bias configuration. The more stable a configuration, the less its response will change due to undesirable changes in temperature and parameter variations. The analysis will be performed by first examining the base–emitter loop and then using the results to investigate the collector–emitter loop. The dc equivalent of Fig. 17 appears in Fig 18 with a separation of the source to create an input and output section. Base–Emitter Loop The base–emitter loop of the network of Fig. 18 can be redrawn as shown in Fig. 19. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction results in the following equation: Collector–Emitter Loop Writing Kirchhoff’s voltage law for the indicated loop in the clockwise direction results in Effect of 𝜷 variation on the response of the fixed-bias and emitter bias configuration The BJT collector current is seen to BJT collector current increases by about 81% due change by 100% due to the 100% to the 100% increase in 𝜷. change in the value of 𝜷. The change in VCE has dropped to about 35%. The value of base current is the same, The network of Fig. 23 is therefore more stable and collector to emitter voltage is than that of Fig. 7 for the same change in 𝜷. decreased by 76%.  Voltage Divider Bias Configuration  In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of the current gain β of the transistor. However, because β is temperature sensitive, especially for silicon transistors, and the actual value of β is usually not well defined, it would be desirable to develop a bias circuit that is less dependent on, or in fact is independent of, the transistor β. The voltage-divider bias configuration of Fig. 28 is such a network.  If the circuit parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally independent of β.  There are two methods that can be applied to analyze the voltage-divider configuration. The first is the exact method, which can be applied to any voltage-divider configuration. The second is referred to as the approximate method and can be applied only if specific conditions are satisfied.  The approximate approach permits a more direct analysis with a savings in time and energy. All in all, the approximate approach can be applied to the majority of situations. Thank You