Electronic Devices and Circuit Theory - 11th Edition.pdf

SIGNIFICANT EQUATIONS 1 Semiconductor Diodes W = QV, 1 eV = 1.6 * 10-19 J, ID = Is (eVD>nVT - 1), VT = kT>q, TK = TC + 273⬚, k = 1.38 * 10-23 J/K, VK ⬵ 0.7 V (Si), VK ⬵ 0.3 V(Ge), VK ⬵ 1.2 V (GaAs), RD = VD>ID, rd = 26 mV>ID, rav = ⌬Vd >⌬Id 兩 pt. to pt. , PD = VD ID, TC = (⌬VZ >VZ)>(T1 - T0) * 100%>⬚C 2 Diode Applications Silicon: VK ⬵ 0.7 V, germanium: VK ⬵ 0.3 V, GaAs: VK ⬵ 1.2 V; half-wave: Vdc = 0.318Vm; full-wave: Vdc = 0.636Vm 3 Bipolar Junction Transistors IE = IC + IB, IC = ICmajority + ICOminority, IC ⬵ IE, VBE = 0.7 V, adc = IC>IE, IC = aIE + ICBO, aac = ⌬IC >⌬IE, ICEO = ICBO >(1 - a), bdc = IC>IB, bac = ⌬IC >⌬IB, a = b>(b + 1), b = a>(1 - a), IC = bIB, IE = (b + 1)IB, PCmax = VCEIC 4 DC Biasing—BJTs In general: VBE = 0.7 V, IC ⬵ IE , IC = bIB; fixed-bias: IB = (VCC - VBE)>RB,VCE = VCC - ICRC, ICsat = VCC>RC; emitter-stabilized: IB = (VCC - VBE)>(RB + (b + 1)RE), Ri = (b + 1)RE , VCE = VCC - IC(RC + RE), ICsat = VCC >(RC + RE); voltage-divider: exact: RTh = R1 储 R2, ETh = R2VCC >(R1 + R2), IB = (ETh - VBE)>(RTh + (b + 1)RE), VCE = VCC - IC(RC + RE), approximate: bRE Ú 10R2, VB = R2VCC >(R1 + R2), VE = VB - VBE, IC ⬵ IE = VE >RE; voltage-feedback: IB = (VCC - VBE)>(RB + b(RC + RE)); common-base: IB = (VEE - VBE)>RE; switching transistors: ton = tr + td , toff = ts + tf ; stability: S(ICO) = ⌬IC >⌬ICO; fixed-bias: S(ICO) = b + 1; emitter-bias: S(ICO) = (b + 1)(1 + RB >RE)>(1 + b + RB >RE); voltage-divider: S(ICO) = (b + 1)(1 + RTh >RE)>(1 + b + RTh >RE); feedback-bias: S(ICO) = (b + 1)(1 + RB>RC)>(1 + b + RB>RC), S(VBE) = ⌬IC >⌬VBE; fixed-bias: S(VBE) = - b>RB; emitter-bias: S(VBE) = - b>(RB + (b + 1)RE); voltage-divider: S(VBE) = - b>(RTh + (b + 1)RE); feedback bias: S(VBE) = - b>(RB + (b + 1)RC), S(b) = ⌬IC >⌬b; fixed-bias: S(b) = IC1 >b1; emitter-bias: S(b) = IC1(1 + RB>RE)> (b1(1 + b2 + RB>RE)); voltage-divider: S(b) = IC1(1 + RTh >RE)>(b1(1 + b2 + RTh >RE)); feedback-bias: S(b) = IC1(1 + RB >RC)>(b1(1 + b2 + RB >RC)), ⌬IC = S(ICO) ⌬ICO + S(VBE) ⌬VBE + S(b) ⌬b 5 BJT AC Analysis re = 26 mV>IE; CE fixed-bias: Zi ⬵ bre, Zo ⬵ RC, Av = - RC>re; voltage-divider bias: Zi = R1 储 R2 储 bre, Zo ⬵ RC, Av = - RC>re; CE emitter-bias: Zi ⬵ RB 储 bRE, Zo ⬵ RC, Av ⬵ - RC>RE; emitter-follower: Zi ⬵ RB 储 bRE, Zo ⬵ re, Av ⬵ 1; common-base: Zi ⬵ RE 储 re, Zo ⬵ RC, Av ⬵ RC>re; collector feedback: Zi ⬵ re >(1>b + RC>RF), Zo ⬵ RC 储 RF, Av = - RC>re; collector dc feedback: Zi ⬵ RF1 储 bre, Zo ⬵ RC 储 RF2, Av = - (RF2 储 RC)>re; effect of load impedance: Av = RLAvNL >(RL + Ro), Ai = - Av Zi >RL; effect of source impedance: Vi = RiVs>(Ri + Rs), Avs = Ri AvNL >(Ri + Rs), Is = Vs>(Rs + Ri); combined effect of load and source impedance: Av = RLAv NL >(RL + Ro), Avs = (Ri >(Ri + Rs))(RL >(RL + Ro))AvNL, Ai = - Av Ri >RL, Ais = - Avs(Rs + Ri)>RL; cascode connection: Av = Av1Av2; Darlington connection: bD = b1b2; emitter-follower configuration: IB = (VCC - VBE)>(RB + bDRE), IC ⬵ IE ⬵ bDIB, Zi = RB 储 b1b2RE, Ai = bDRB >(RB + bDRE), Av ⬵ 1, Zo = re1>b2 + re2; basic amplifier configuration: Zi = R1 储 R2 储 Zi⬘, Zi⬘ = b1(re1 + b2re2), Ai = bD(R1 储 R2)>(R1 储 R2 + Zi⬘), Av = bDRC>Zi⬘, Zo = RC 储 ro2; feedback pair: IB1 = (VCC - VBE1)>(RB + b1b2RC), Zi = RB 储 Zi⬘, Zi⬘ = b1re1 + b1b2RC, Ai = - b1b2RB >(RB + b1b2RC) Av = b2RC >(re + b2RC) ⬵ 1, Zo ⬵ re1 >b2. 6 Field-Effect Transistors IG = 0 A, ID = IDSS(1 - VGS>VP)2, ID = IS , VGS = VP (1 - 2ID >IDSS), ID = IDSS >4 (if VGS = VP>2), ID = IDSS >2 (if VGS ⬵ 0.3 VP), PD = VDSID , rd = ro >(1 - VGS>VP)2; MOSFET: ID = k(VGS - VT)2, k = ID(on) >(VGS(on) - VT)2 7 FET Biasing Fixed-bias: VGS = - VGG, VDS = VDD - IDRD; self-bias: VGS = - IDRS, VDS = VDD - ID(RS + RD), VS = IDRS; voltage-divider: VG = R2VDD>(R1 + R2), VGS = VG - ID RS, VDS = VDD - ID(RD + RS); common-gate configuration: VGS = VSS - IDRS, VDS = VDD + VSS - ID(RD + RS); special case: VGSQ = 0 V: IIQ = IDSS, VDS = VDD - IDRD, VD = VDS, VS = 0 V. enhancement-type MOSFET: ID = k(VGS - VGS(Th))2, k = ID(on) >(VGS(on) - VGS(Th))2; feedback bias: VDS = VGS, VGS = VDD - IDRD; voltage-divider: VG = R2VDD >(R1 + R2), VGS = VG - IDRS; universal curve: m = 0 VP 0 >IDSSRS, M = m * VG > 0 VP 0 ,VG = R2VDD >(R1 + R2) 8 FET Amplifiers gm = yfs = ⌬ID>⌬VGS, gm0 = 2IDSS >兩VP 兩, gm = gm0(1 - VGS >VP), gm = gm0 1ID>IDSS, rd = 1>yos = ⌬VDS >⌬ID 0 VGS = constant; fixed-bias: Zi = RG, Zo ⬵ RD, Av = - gmRD; self-bias (bypassed Rs): Zi = RG, Zo ⬵ RD, Av = - gmRD; self-bias (unbypassed Rs): Zi = RG, Zo = RD, Av ⬵ - gmRD>(1 + gmRs); voltage-divider bias: Zi = R1 储 R2, Zo = RD, Av = - gmRD; source follower: Zi = RG, Zo = RS 储 1>gm , Av ⬵ gm RS >(1 + gm RS); common-gate: Zi = RS 储 1>gm, Zo ⬵ RD, Av = gm RD; enhancement-type MOSFETs: gm = 2k(VGSQ - VGS(Th)); drain-feedback configuration: Zi ⬵ RF >(1 + gmRD), Zo ⬵ RD, Av ⬵ - gmRD; voltage-divider bias: Zi = R1 储 R2, Zo ⬵ RD, Av ⬵ - gmRD. 9 BJT and JFET Frequency Response logea = 2.3 log10a, log101 = 0, log10 a>b = log10 a - log10 b, log101>b = - log10b, log10ab = log10 a + log10 b, GdB = 10 log10 P2 >P1, GdBm = 10 log10 P2 >1 mW兩 600 ⍀ , GdB = 20 log10 V2>V1, GdBT = GdB1 + GdB2 + g + GdBn PoHPF = 0.5Pomid , BW = f1 - f2; low frequency (BJT): fLS = 1>2p(Rs + Ri)Cs, fLC = 1>2p(Ro + RL)CC, fLE = 1>2pR eCE, Re = RE 储 (R⬘s >b + re), R⬘s = Rs 储 R1 储 R2, FET: fLG = 1>2p(Rsig + Ri)CG, fLC = 1>2p(Ro + RL)CC , fLS = 1>2pReqCS, Req = RS 储 1>gm(rd ⬵ ⬁ ⍀); Miller effect: CMi = (1 - Av)Cf , CMo = (1 - 1>Av)Cf ; high frequency (BJT): fHi = 1>2pRThi Ci, RThi = Rs 储 R1 储 R2 储 Ri, Ci = Cwi + Cbe + (1 - Av)Cbc, fHo = 1>2pRThoCo, RTho = RC 储 RL 储 ro, Co = CWo + Cce + CMo, fb ⬵ 1>2pbmidre(Cbe + Cbc), fT = bmid fb; FET: fHi = 1>2pRThiCi, RThi = Rsig 储 RG, Ci = CWi + Cgs + CMi, CMi = (1 - Av)Cgd fHo = 1>2pRThoCo, RTho = RD 储 RL 储 rd, Co = CWo + Cds + CMo; CMO = (1 - 1>Av)Cgd; multistage: f 1⬘ = f1 > 221>n - 1, f 2⬘ = ( 221>n - 1)f2; square-wave testing: fHi = 0.35>tr , % tilt = P% = ((V - V⬘)>V ) * 100%, fLo = (P>p)fs 10 Operational Amplifiers CMRR = Ad >Ac; CMRR(log) = 20 log10(Ad >Ac); constant-gain multiplier: Vo >V1 = - Rf >R1; noninverting amplifier: Vo >V1 = 1 + Rf >R1; unity follower: Vo = V1; summing amplifier: Vo = - [(Rf >R1)V1 + (Rf >R2)V2 + (Rf >R3)V3]; integrator: vo(t) = - (1>R1C1) 1v1dt 11 Op-Amp Applications Constant-gain multiplier: A = - Rf >R1; noninverting: A = 1 + Rf >R1: voltage summing: Vo = - [(Rf >R1)V1 + (Rf >R2)V2 + (Rf >R3)V3]; high-pass active filter: foL = 1>2pR1C1; low-pass active filter: foH = 1>2pR1C1 12 Power Amplifiers Power in: Pi = VCCICQ power out: Po = VCEIC = IC2RC = VCE 2 >RC rms = VCEIC >2 = (IC >2)RC = VCE 2 2 >(2RC) peak = VCEIC >8 = (IC >8)RC = VCE 2 2 >(8RC) peak@to@peak efﬁciency: %h = (Po >Pi) * 100%; maximum efﬁciency: Class A, series-fed ⫽ 25%; Class A, transformer-coupled ⫽ 50%; Class B, push-pull ⫽ 78.5%; transformer relations: V2 >V1 = N2 >N1 = I1 >I2, R2 = (N2 >N1)2R1; power output: Po = [(VCE max - VCE min ) (IC max - IC min )]>8; class B power ampliﬁer: Pi = VCC 3 (2>p)Ipeak 4 ; Po = VL2(peak)>(2RL); %h = (p>4) 3 VL(peak)>VCC 4 * 100%; PQ = P2Q >2 = (Pi - Po)>2; maximum Po = VCC 2 >2RL; maximum Pi = 2VCC 2 >pRL; maximum P2Q = 2VCC 2 >p 2RL; % total harmonic distortion (% THD) = 2D2 + D3 + D4 + g * 100%; heat-sink: TJ = PDuJA + TA, uJA = 40⬚C/W (free air); 2 2 2 PD = (TJ - TA)>(uJC + uCS + uSA) 13 Linear-Digital ICs Ladder network: Vo = [(D0 * 20 + D1 * 21 + D2 * 22 + g + Dn * 2n)>2n ]Vref; 555 oscillator: f = 1.44(RA + 2RB)C; 555 monostable: Thigh = 1.1RAC; VCO: fo = (2>R1C1)[(V + - VC)>V + ]; phase- locked loop (PLL): fo = 0.3>R1C1, fL = {8 fo >V, fC = {(1>2p) 22pfL >(3.6 * 103)C2 14 Feedback and Oscillator Circuits Af = A>(1 + bA); series feedback; Zif = Zi(1 + bA); shunt feedback: Zif = Zi >(1 + bA); voltage feedback: Zof = Zo>(1 + bA); current feedback; Zof = Zo(1 + bA); gain stability: dAf >Af = 1>(兩1 + bA兩)(dA>A); oscillator; bA = 1; phase shift: f = 1>2pRC 16, b = 1>29, A 7 29; FET phase shift: 兩A兩 = gm RL, RL = RDrd >(RD + rd); transistor phase shift: f = (1>2pRC)[1> 26 + 4(RC >R)], hfe 7 23 + 29(RC>R) + 4(R>RC); Wien bridge: R3 >R4 = R1 >R2 + C2 >C1, fo = 1>2p 1R1C1R2C2; tuned: fo = 1>2p 1LCeq, Ceq = C1C2 >(C1 + C2), Hartley: Leq = L1 + L2 + 2M, fo = 1>2p 1LeqC 15 Power Supplies (Voltage Regulators) Filters: r = Vr (rms)>Vdc * 100%, V.R. = (VNL - VFL)>VFL * 100%, Vdc = Vm - Vr(p@p)>2, Vr (rms) = Vr (p@p)>2 13, Vr (rms) ⬵ (Idc >4 13)(Vdc>Vm); full-wave, light load Vr (rms) = 2.4Idc>C, Vdc = Vm - 4.17Idc >C, r = (2.4IdcCVdc) * 100% = 2.4>RLC * 100%, Ipeak = T>T1 * Idc; RC filter: V⬘dc = RL Vdc > (R + RL), XC = 2.653>C(half@wave), XC = 1.326>C (full@wave), V⬘r (rms) = (XC> 2R2 + X2C); regulators: IR = (INL - IFL)>IFL * 100%, VL = VZ (1 + R1 >R2), Vo = Vref (1 + R2 >R1) + IadjR2 16 Other Two-Terminal Devices Varactor diode: CT = C(0)>(1 + 兩Vr >VT 兩)n, TCC = (⌬C>Co(T1 - T0)) * 100%; photodiode: W = hf, l = v>f, 1 lm = 1.496 * 10-10 W, 1 Å = 10-10 m, 1 fc = 1 lm>ft2 = 1.609 * 10-9 W>m2 17 pnpn and Other Devices Diac: VBR1 = VBR2 { 0.1 VBR2 UJT: RBB = (RB1 + RB2)兩 IE = 0 , VRB = hVBB 兩 IE = 0, 1 h = RB1>(RB1 + RB2)兩 IE = 0 , VP = hVBB + VD; phototransistor: IC ⬵ hfeIl; PUT: h = RB1>(RB1 + RB2),VP = hVBB + VD Electronic Devices and Circuit Theory Eleventh Edition Robert L. Boylestad Louis Nashelsky Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director: Vernon R. Anthony Senior Acquisitions Editor: Lindsey Prudhomme Development Editor: Dan Trudden Editorial Assistant: Yvette Schlarman Director of Marketing: David Gesell Marketing Manager: Harper Coles Senior Marketing Coordinator: Alicia Wozniak Marketing Assistant: Les Roberts Senior Managing Editor: JoEllen Gohr Senior Project Manager: Rex Davidson Senior Operations Supervisor: Pat Tonneman Creative Director: Andrea Nix Art Director: Diane Y. Ernsberger Cover Image: Hewlett-Packard Labs Media Project Manager: Karen Bretz Full-Service Project Management: Kelly Ricci, Aptara®, Inc. Composition: Aptara®, Inc. Printer/Binder: Edwards Brothers Cover Printer: Lehigh/Phoenix Color Hagerstown Text Font: Times Credits and acknowledgments for materials borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page within text. About the cover image: 17 : 17 cross-bar array of 50-nm thick TiO2 memristors defined by 50-nm wide platinum electrodes, spaced by 50-nm gaps. J. Joshua Yang, G. Medeiros-Ribeiro, and R. Stan Williams, Hewlett-Packard Labs. Copyright 2011, Hewlett-Packard Development Company, L. P. Reproduced with permission. Cadence, The Cadence logo, OrCAD, OrCAD Capture, and PSpice are registered trademarks of Cadence Design Systems, Inc. Multisim is a registered trademark of National Instruments. Copyright © 2013, 2009, 2006 by Pearson Education, Inc. All rights reserved. Manufactured in the United States of America. This publication is protected by Copyright, and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. To obtain permission(s) to use material from this work, please submit a written request to Pearson Education, Inc., Permissions Department, One Lake Street, Upper Saddle River, New Jersey 07458, or you may fax your request to 201-236-3290. Many of the designations by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed in initial caps or all caps. Library of Congress Cataloging-in-Publication Data Boylestad, Robert L. Electronic devices and circuit theory / Robert L. Boylestad, Louis Nashelsky.—11th ed. p. cm. ISBN 978-0-13-262226-4 1. Electronic circuits. 2. Electronic apparatus and appliances. I. Nashelsky, Louis. II. Title. TK7867.B66 2013 621.3815—dc23 2011052885 10 9 8 7 6 5 4 3 2 1 ISBN 10: 0-13-262226-2 ISBN 13: 978-0-13-262226-4 DEDICATION To Else Marie, Alison and Mark, Eric and Rachel, Stacey and Jonathan, and our eight granddaughters: Kelcy, Morgan, Codie, Samantha, Lindsey, Britt, Skylar, and Aspen. To Katrin, Kira and Thomas, Larren and Patricia, and our six grandsons: Justin, Brendan, Owen, Tyler, Colin, and Dillon. This page intentionally left blank PREFACE The preparation of the preface for the 11th edition resulted in a bit of reflection on the 40 years since the first edition was published in 1972 by two young educators eager to test their ability to improve on the available literature on electronic devices. Although one may prefer the term semiconductor devices rather than electronic devices, the first edition was almost exclusively a survey of vacuum-tube devices—a subject without a single section in the new Table of Contents. The change from tubes to predominantly semiconductor devices took almost five editions, but today it is simply referenced in some sections. It is interest- ing, however, that when field-effect transistor (FET) devices surfaced in earnest, a number of the analysis techniques used for tubes could be applied because of the similarities in the ac equivalent models of each device. We are often asked about the revision process and how the content of a new edition is defined. In some cases, it is quite obvious that the computer software has been updated, and the changes in application of the packages must be spelled out in detail. This text was the first to emphasize the use of computer software packages and provided a level of detail unavailable in other texts. With each new version of a software package, we have found that the supporting literature may still be in production, or the manuals lack the detail for new users of these packages. Sufficient detail in this text ensures that a student can apply each of the software packages covered without additional instruc- tional material. The next requirement with any new edition is the need to update the content reflecting changes in the available devices and in the characteristics of commercial devices. This can require extensive research in each area, followed by decisions regarding depth of coverage and whether the listed improvements in response are valid and deserve recog- nition. The classroom experience is probably one of the most important resources for defining areas that need expansion, deletion, or revision. The feedback from students results in marked-up copies of our texts with inserts creating a mushrooming copy of the material. Next, there is the input from our peers, faculty at other institutions using the text, and, of course, reviewers chosen by Pearson Education to review the text. One source of change that is less obvious is a simple rereading of the material following the passing of the years since the last edition. Rereading often reveals material that can be improved, deleted, or expanded. For this revision, the number of changes far outweighs our original expectations. How- ever, for someone who has used previous editions of the text, the changes will probably be less obvious. However, major sections have been moved and expanded, some 100-plus problems have been added, new devices have been introduced, the number of applications has been increased, and new material on recent developments has been added through- out the text. We believe that the current edition is a significant improvement over the previous editions. As instructors, we are all well aware of the importance of a high level of accuracy required for a text of this kind. There is nothing more frustrating for a student than to work a problem over from many different angles and still find that the answer differs from the solution at the back of the text or that the problem seems undoable. We were pleased to find that there were fewer than half a dozen errors or misprints reported since v vi PREFACE the last edition. When you consider the number of examples and problems in the text along with the length of the text material, this statistic clearly suggests that the text is as error-free as possible. Any contributions from users to this list were quickly acknowl- edged, and the sources were thanked for taking the time to send the changes to the pub- lisher and to us. Although the current edition now reflects all the changes we feel it should have, we expect that a revised edition will be required somewhere down the line. We invite you to respond to this edition so that we can start developing a package of ideas and thoughts that will help us improve the content for the next edition. We promise a quick response to your comments, whether positive or negative. NEW TO THIS EDITION Throughout the chapters, there are extensive changes in the problem sections. Over 100 new problems have been added, and a significant number of changes have been made to the existing problems. A significant number of computer programs were all rerun and the descriptions updated to include the effects of using OrCAD version 16.3 and Multisim version 11.1. In addi- tion, the introductory chapters are now assuming a broader understanding of computer methods, resulting in a revised introduction to the two programs. Throughout the text, photos and biographies of important contributors have been added. Included among these are Sidney Darlington, Walter Schottky, Harry Nyquist, Edwin Colpitts, and Ralph Hartley. New sections were added throughout the text. There is now a discussion on the impact of combined dc and ac sources on diode networks, of multiple BJT networks, VMOS and UMOS power FETs, Early voltage, frequency impact on the basic elements, effect of RS on an amplifier’s frequency response, gain-bandwidth product, and a number of other topics. A number of sections were completely rewritten due to reviewers’ comments or changing priorities. Some of the areas revised include bias stabilization, current sources, feedback in the dc and ac modes, mobility factors in diode and transistor response, transition and diffusion capacitive effects in diodes and transistor response characteristics, reverse-saturation current, breakdown regions (cause and effect), and the hybrid model. In addition to the revision of numerous sections described above, there are a number of sections that have been expanded to respond to changes in priorities for a text of this kind. The section on solar cells now includes a detailed examination of the materials employed, additional response curves, and a number of new practical applications. The coverage of the Darlington effect was totally rewritten and expanded to include detailed examination of the emitter-follower and collector gain configurations. The coverage of transistors now includes details on the cross-bar latch transistor and carbon nanotubes. The discussion of LEDs includes an expanded discussion of the materials employed, comparisons to today’s other lighting options, and examples of the products defining the future of this important semiconductor device. The data sheets commonly included in a text of this type are now discussed in detail to ensure a well-established link when the student enters the industrial community. Updated material appears throughout the text in the form of photos, artwork, data sheets, and so forth, to ensure that the devices included reflect the components avail- able today with the characteristics that have changed so rapidly in recent years. In addition, the parameters associated with the content and all the example problems are more in line with the device characteristics available today. Some devices, no longer available or used very infrequently, were dropped to ensure proper emphasis on the current trends. There are a number of important organizational changes throughout the text to ensure the best sequence of coverage in the learning process. This is readily apparent in the early dc chapters on diodes and transistors, in the discussion of current gain in the ac chapters for BJTs and JFETs, in the Darlington section, and in the frequency response chapters. It is particularly obvious in Chapter 16, where topics were dropped and the order of sections changed dramatically. INSTRUCTOR SUPPLEMENTS PREFACE vii To download the supplements listed below, please visit: http://www.pearsonhighered. com/irc and enter “Electronic Devices and Circuit Theory” in the search bar. From there, you will be able to register to receive an instructor’s access code. Within 48 hours after registering, you will receive a confirming email, including an instructor access code. Once you have received your code, return to the site and log on for full instructions on how to download the materials you wish to use. PowerPoint Presentation–(ISBN 0132783746). This supplement contains all figures from the text as well as a new set of lecture notes highlighting important concepts. TestGen® Computerized Test Bank–(ISBN 013278372X). This electronic bank of test questions can be used to develop customized quizzes, tests, and/or exams. Instructor’s Resource Manual–(ISBN 0132783738). This supplement contains the solu- tions to the problems in the text and lab manual. STUDENT SUPPLEMENTS Laboratory Manual–(ISBN 0132622459). This supplement contains over 35 class-tested experiments for students to use to demonstrate their comprehension of course material. Companion Website–Student study resources are available at www.pearsonhighered. com/boylestad ACKNOWLEDGMENTS The following individuals supplied new photographs for this edition. Sian Cummings International Rectifier Inc. Michele Drake Agilent Technologies Inc. Edward Eckert Alcatel-Lucent Inc. Amy Flores Agilent Technologies Inc. Ron Forbes B&K Precision Corporation Christopher Frank Siemens AG Amber Hall Hewlett-Packard Company Jonelle Hester National Semiconductor Inc. George Kapczak AT&T Inc. Patti Olson Fairchild Semiconductor Inc. Jordon Papanier LEDtronics Inc. Andrew W. Post Vishay Inc. Gilberto Ribeiro Hewlett-Packard Company Paul Ross Alcatel-Lucent Inc. Craig R. Schmidt Agilent Technologies, Inc. Mitch Segal Hewlett-Packard Company Jim Simon Agilent Technologies, Inc. Debbie Van Velkinburgh Tektronix, Inc. Steve West On Semiconductor Inc. Marcella Wilhite Agilent Technologies, Inc. Stan Williams Hewlett-Packard Company J. Joshua Wang Hewlett-Packard Company This page intentionally left blank BRIEF CONTENTS Preface v CHAPTER 1: Semiconductor Diodes 1 CHAPTER 2: Diode Applications 55 CHAPTER 3: Bipolar Junction Transistors 129 CHAPTER 4: DC Biasing—BJTs 160 CHAPTER 5: BJT AC Analysis 253 CHAPTER 6: Field-Effect Transistors 378 CHAPTER 7: FET Biasing 422 CHAPTER 8: FET Amplifiers 481 CHAPTER 9: BJT and JFET Frequency Response 545 CHAPTER 10: Operational Amplifiers 607 CHAPTER 11: Op-Amp Applications 653 CHAPTER 12: Power Amplifiers 683 CHAPTER 13: Linear-Digital ICs 722 CHAPTER 14: Feedback and Oscillator Circuits 751 CHAPTER 15: Power Supplies (Voltage Regulators) 783 CHAPTER 16: Other Two-Terminal Devices 811 CHAPTER 17: pnpn and Other Devices 841 Appendix A: Hybrid Parameters—Graphical Determinations and Conversion Equations (Exact and Approximate) 879 ix x BRIEF CONTENTS Appendix B: Ripple Factor and Voltage Calculations 885 Appendix C: Charts and Tables 891 Appendix D: Solutions to Selected Odd-Numbered Problems 893 Index 901 CONTENTS Preface v CHAPTER 1: Semiconductor Diodes 1 1.1 Introduction 1 1.2 Semiconductor Materials: Ge, Si, and GaAs 2 1.3 Covalent Bonding and Intrinsic Materials 3 1.4 Energy Levels 5 1.5 n-Type and p-Type Materials 7 1.6 Semiconductor Diode 10 1.7 Ideal Versus Practical 20 1.8 Resistance Levels 21 1.9 Diode Equivalent Circuits 27 1.10 Transition and Diffusion Capacitance 30 1.11 Reverse Recovery Time 31 1.12 Diode Specification Sheets 32 1.13 Semiconductor Diode Notation 35 1.14 Diode Testing 36 1.15 Zener Diodes 38 1.16 Light-Emitting Diodes 41 1.17 Summary 48 1.18 Computer Analysis 49 CHAPTER 2: Diode Applications 55 2.1 Introduction 55 2.2 Load-Line Analysis 56 2.3 Series Diode Configurations 61 2.4 Parallel and Series–Parallel Configurations 67 2.5 AND/OR Gates 70 2.6 Sinusoidal Inputs; Half-Wave Rectification 72 2.7 Full-Wave Rectification 75 2.8 Clippers 78 2.9 Clampers 85 2.10 Networks with a dc and ac Source 88 xi xii CONTENTS 2.11 Zener Diodes 91 2.12 Voltage-Multiplier Circuits 98 2.13 Practical Applications 101 2.14 Summary 111 2.15 Computer Analysis 112 CHAPTER 3: Bipolar Junction Transistors 129 3.1 Introduction 129 3.2 Transistor Construction 130 3.3 Transistor Operation 130 3.4 Common-Base Configuration 131 3.5 Common-Emitter Configuration 136 3.6 Common-Collector Configuration 143 3.7 Limits of Operation 144 3.8 Transistor Specification Sheet 145 3.9 Transistor Testing 149 3.10 Transistor Casing and Terminal Identification 151 3.11 Transistor Development 152 3.12 Summary 154 3.13 Computer Analysis 155 CHAPTER 4: DC Biasing—BJTs 160 4.1 Introduction 160 4.2 Operating Point 161 4.3 Fixed-Bias Configuration 163 4.4 Emitter-Bias Configuration 169 4.5 Voltage-Divider Bias Configuration 175 4.6 Collector Feedback Configuration 181 4.7 Emitter-Follower Configuration 186 4.8 Common-Base Configuration 187 4.9 Miscellaneous Bias Configurations 189 4.10 Summary Table 192 4.11 Design Operations 194 4.12 Multiple BJT Networks 199 4.13 Current Mirrors 205 4.14 Current Source Circuits 208 4.15 pnp Transistors 210 4.16 Transistor Switching Networks 211 4.17 Troubleshooting Techniques 215 4.18 Bias Stabilization 217 4.19 Practical Applications 226 4.20 Summary 233 4.21 Computer Analysis 235 CHAPTER 5: BJT AC Analysis 253 CONTENTS xiii 5.1 Introduction 253 5.2 Amplification in the AC Domain 253 5.3 BJT Transistor Modeling 254 5.4 The re Transistor Model 257 5.5 Common-Emitter Fixed-Bias Configuration 262 5.6 Voltage-Divider Bias 265 5.7 CE Emitter-Bias Configuration 267 5.8 Emitter-Follower Configuration 273 5.9 Common-Base Configuration 277 5.10 Collector Feedback Configuration 279 5.11 Collector DC Feedback Configuration 284 5.12 Effect of RL and Rs 286 5.13 Determining the Current Gain 291 5.14 Summary Tables 292 5.15 Two-Port Systems Approach 292 5.16 Cascaded Systems 300 5.17 Darlington Connection 305 5.18 Feedback Pair 314 5.19 The Hybrid Equivalent Model 319 5.20 Approximate Hybrid Equivalent Circuit 324 5.21 Complete Hybrid Equivalent Model 330 5.22 Hybrid p Model 337 5.23 Variations of Transistor Parameters 338 5.24 Troubleshooting 340 5.25 Practical Applications 342 5.26 Summary 349 5.27 Computer Analysis 352 CHAPTER 6: Field-Effect Transistors 378 6.1 Introduction 378 6.2 Construction and Characteristics of JFETs 379 6.3 Transfer Characteristics 386 6.4 Specification Sheets (JFETs) 390 6.5 Instrumentation 394 6.6 Important Relationships 395 6.7 Depletion-Type MOSFET 396 6.8 Enhancement-Type MOSFET 402 6.9 MOSFET Handling 409 6.10 VMOS and UMOS Power and MOSFETs 410 6.11 CMOS 411 6.12 MESFETs 412 6.13 Summary Table 414 xiv CONTENTS 6.14 Summary 414 6.15 Computer Analysis 416 CHAPTER 7: FET Biasing 422 7.1 Introduction 422 7.2 Fixed-Bias Configuration 423 7.3 Self-Bias Configuration 427 7.4 Voltage-Divider Biasing 431 7.5 Common-Gate Configuration 436 7.6 Special Case VGSQ ⴝ 0 V 439 7.7 Depletion-Type MOSFETs 439 7.8 Enhancement-Type MOSFETs 443 7.9 Summary Table 449 7.10 Combination Networks 449 7.11 Design 452 7.12 Troubleshooting 455 7.13 p-Channel FETs 455 7.14 Universal JFET Bias Curve 458 7.15 Practical Applications 461 7.16 Summary 470 7.17 Computer Analysis 471 CHAPTER 8: FET Amplifiers 481 8.1 Introduction 481 8.2 JFET Small-Signal Model 482 8.3 Fixed-Bias Configuration 489 8.4 Self-Bias Configuration 492 8.5 Voltage-Divider Configuration 497 8.6 Common-Gate Configuration 498 8.7 Source-Follower (Common-Drain) Configuration 501 8.8 Depletion-Type MOSFETs 505 8.9 Enhancement-Type MOSFETs 506 8.10 E-MOSFET Drain-Feedback Configuration 507 8.11 E-MOSFET Voltage-Divider Configuration 510 8.12 Designing FET Amplifier Networks 511 8.13 Summary Table 513 8.14 Effect of RL and Rsig 516 8.15 Cascade Configuration 518 8.16 Troubleshooting 521 8.17 Practical Applications 522 8.18 Summary 530 8.19 Computer Analysis 531 CHAPTER 9: BJT and JFET Frequency Response 545 CONTENTS xv 9.1 Introduction 545 9.2 Logarithms 545 9.3 Decibels 550 9.4 General Frequency Considerations 554 9.5 Normalization Process 557 9.6 Low-Frequency Analysis—Bode Plot 559 9.7 Low-Frequency Response—BJT Amplifier with RL 564 9.8 Impact of Rs on the BJT Low-Frequency Response 568 9.9 Low-Frequency Response—FET Amplifier 571 9.10 Miller Effect Capacitance 574 9.11 High-Frequency Response—BJT Amplifier 576 9.12 High-Frequency Response—FET Amplifier 584 9.13 Multistage Frequency Effects 586 9.14 Square-Wave Testing 588 9.15 Summary 591 9.16 Computer Analysis 592 CHAPTER 10: Operational Amplifiers 607 10.1 Introduction 607 10.2 Differential Amplifier Circuit 610 10.3 BiFET, BiMOS, and CMOS Differential Amplifier Circuits 617 10.4 Op-Amp Basics 620 10.5 Practical Op-Amp Circuits 623 10.6 Op-Amp Specifications—DC Offset Parameters 628 10.7 Op-Amp Specifications—Frequency Parameters 631 10.8 Op-Amp Unit Specifications 634 10.9 Differential and Common-Mode Operation 639 10.10 Summary 643 10.11 Computer Analysis 644 CHAPTER 11: Op-Amp Applications 653 11.1 Constant-Gain Multiplier 653 11.2 Voltage Summing 657 11.3 Voltage Buffer 660 11.4 Controlled Sources 661 11.5 Instrumentation Circuits 663 11.6 Active Filters 667 11.7 Summary 670 11.8 Computer Analysis 671 CHAPTER 12: Power Amplifiers 683 12.1 Introduction—Definitions and Amplifier Types 683 12.2 Series-Fed Class A Amplifier 685 xvi CONTENTS 12.3 Transformer-Coupled Class A Amplifier 688 12.4 Class B Amplifier Operation 695 12.5 Class B Amplifier Circuits 699 12.6 Amplifier Distortion 705 12.7 Power Transistor Heat Sinking 709 12.8 Class C and Class D Amplifiers 712 12.9 Summary 714 12.10 Computer Analysis 715 CHAPTER 13: Linear-Digital ICs 722 13.1 Introduction 722 13.2 Comparator Unit Operation 722 13.3 Digital–Analog Converters 729 13.4 Timer IC Unit Operation 732 13.5 Voltage-Controlled Oscillator 736 13.6 Phase-Locked Loop 738 13.7 Interfacing Circuitry 742 13.8 Summary 745 13.9 Computer Analysis 745 CHAPTER 14: Feedback and Oscillator Circuits 751 14.1 Feedback Concepts 751 14.2 Feedback Connection Types 752 14.3 Practical Feedback Circuits 758 14.4 Feedback Amplifier—Phase and Frequency Considerations 763 14.5 Oscillator Operation 766 14.6 Phase-Shift Oscillator 767 14.7 Wien Bridge Oscillator 770 14.8 Tuned Oscillator Circuit 771 14.9 Crystal Oscillator 774 14.10 Unijunction Oscillator 777 14.11 Summary 778 14.12 Computer Analysis 779 CHAPTER 15: Power Supplies (Voltage Regulators) 783 15.1 Introduction 783 15.2 General Filter Considerations 784 15.3 Capacitor Filter 786 15.4 RC Filter 789 15.5 Discrete Transistor Voltage Regulation 791 15.6 IC Voltage Regulators 798 15.7 Practical Applications 803 15.8 Summary 805 15.9 Computer Analysis 806 CHAPTER 16: Other Two-Terminal Devices 811 CONTENTS xvii 16.1 Introduction 811 16.2 Schottky Barrier (Hot-Carrier) Diodes 811 16.3 Varactor (Varicap) Diodes 815 16.4 Solar Cells 819 16.5 Photodiodes 824 16.6 Photoconductive Cells 826 16.7 IR Emitters 828 16.8 Liquid-Crystal Displays 829 16.9 Thermistors 831 16.10 Tunnel Diodes 833 16.11 Summary 837 CHAPTER 17: pnpn and Other Devices 841 17.1 Introduction 841 17.2 Silicon-Controlled Rectifier 841 17.3 Basic Silicon-Controlled Rectifier Operation 842 17.4 SCR Characteristics and Ratings 843 17.5 SCR Applications 845 17.6 Silicon-Controlled Switch 849 17.7 Gate Turn-Off Switch 851 17.8 Light-Activated SCR 852 17.9 Shockley Diode 854 17.10 Diac 854 17.11 Triac 856 17.12 Unijunction Transistor 857 17.13 Phototransistors 865 17.14 Opto-Isolators 867 17.15 Programmable Unijunction Transistor 869 17.16 Summary 874 Appendix A: Hybrid Parameters—Graphical Determinations and Conversion Equations (Exact and Approximate) 879 A.1 Graphical Determination of the h-Parameters 879 A.2 Exact Conversion Equations 883 A.3 Approximate Conversion Equations 883 Appendix B: Ripple Factor and Voltage Calculations 885 B.1 Ripple Factor of Rectifier 885 B.2 Ripple Voltage of Capacitor Filter 886 B.3 Relation of Vdc and Vm to Ripple r 887 B.4 Relation of Vr (rms) and Vm to Ripple r 888 B.5 Relation Connecting Conduction Angle, Percentage Ripple, and Ipeak兾Idc for Rectifier-Capacitor Filter Circuits 889 xviii CONTENTS Appendix C: Charts and Tables 891 Appendix D: Solutions to Selected Odd-Numbered Problems 893 Index 901 Semiconductor Diodes 1 CHAPTER OBJECTIVES Become aware of the general characteristics of three important semiconductor materials: Si, Ge, GaAs. Understand conduction using electron and hole theory. Be able to describe the difference between n- and p-type materials. Develop a clear understanding of the basic operation and characteristics of a diode in the no-bias, forward-bias, and reverse-bias regions. Be able to calculate the dc, ac, and average ac resistance of a diode from the characteristics. Understand the impact of an equivalent circuit whether it is ideal or practical. Become familiar with the operation and characteristics of a Zener diode and light-emitting diode. 1.1 INTRODUCTION One of the noteworthy things about this field, as in many other areas of technology, is how little the fundamental principles change over time. Systems are incredibly smaller, current speeds of operation are truly remarkable, and new gadgets surface every day, leaving us to wonder where technology is taking us. However, if we take a moment to consider that the majority of all the devices in use were invented decades ago and that design techniques appearing in texts as far back as the 1930s are still in use, we realize that most of what we see is primarily a steady improvement in construction techniques, general characteristics, and application techniques rather than the development of new elements and fundamen- tally new designs. The result is that most of the devices discussed in this text have been around for some time, and that texts on the subject written a decade ago are still good ref- erences with content that has not changed very much. The major changes have been in the understanding of how these devices work and their full range of capabilities, and in improved methods of teaching the fundamentals associated with them. The benefit of all this to the new student of the subject is that the material in this text will, we hope, have reached a level where it is relatively easy to grasp and the information will have applica- tion for years to come. The miniaturization that has occurred in recent years leaves us to wonder about its limits. Complete systems now appear on wafers thousands of times smaller than the single element of earlier networks. The first integrated circuit (IC) was developed by Jack Kilby while working at Texas Instruments in 1958 (Fig. 1.1). Today, the Intel® CoreTM i7 Extreme 1 2 SEMICONDUCTOR Edition Processor of Fig. 1.2 has 731 million transistors in a package that is only slightly DIODES larger than a 1.67 sq. inches. In 1965, Dr. Gordon E. Moore presented a paper predicting that the transistor count in a single IC chip would double every two years. Now, more than 45 years, later we find that his prediction is amazingly accurate and expected to continue for the next few decades. We have obviously reached a point where the primary purpose of the container is simply to provide some means for handling the device or system and to provide a mechanism for attachment to the remainder of the network. Further miniaturiza- tion appears to be limited by four factors: the quality of the semiconductor material, the network design technique, the limits of the manufacturing and processing equipment, and the strength of the innovative spirit in the semiconductor industry. The first device to be introduced here is the simplest of all electronic devices, yet has a range of applications that seems endless. We devote two chapters to the device to introduce the materials commonly used in solid-state devices and review some fundamental laws of electric circuits. 1.2 SEMICONDUCTOR MATERIALS: Ge, Si, AND GaAs Jack St. Clair Kilby, inventor of the The construction of every discrete (individual) solid-state (hard crystal structure) electronic integrated circuit and co-inventor of device or integrated circuit begins with a semiconductor material of the highest quality. the electronic handheld calculator. Semiconductors are a special class of elements having a conductivity between that of a (Courtesy of Texas Instruments.) good conductor and that of an insulator. Born: Jefferson City, Missouri,1923. In general, semiconductor materials fall into one of two classes: single-crystal and MS, University of Wisconsin. compound. Single-crystal semiconductors such as germanium (Ge) and silicon (Si) have a Director of Engineering and Tech- repetitive crystal structure, whereas compound semiconductors such as gallium arsenide nology, Components Group, Texas (GaAs), cadmium sulfide (CdS), gallium nitride (GaN), and gallium arsenide phosphide Instruments. Fellow of the IEEE. (GaAsP) are constructed of two or more semiconductor materials of different atomic Holds more than 60 U.S. patents. structures. The three semiconductors used most frequently in the construction of electronic devices are Ge, Si, and GaAs. In the first few decades following the discovery of the diode in 1939 and the transis- tor in 1947 germanium was used almost exclusively because it was relatively easy to find and was available in fairly large quantities. It was also relatively easy to refine to obtain very high levels of purity, an important aspect in the fabrication process. How- ever, it was discovered in the early years that diodes and transistors constructed using germanium as the base material suffered from low levels of reliability due primarily to its sensitivity to changes in temperature. At the time, scientists were aware that another material, silicon, had improved temperature sensitivities, but the refining process for manufacturing silicon of very high levels of purity was still in the development stages. The first integrated circuit, a phase- Finally, however, in 1954 the first silicon transistor was introduced, and silicon quickly shift oscillator, invented by Jack S. became the semiconductor material of choice. Not only is silicon less temperature sensi- Kilby in 1958. (Courtesy of Texas Instruments.) tive, but it is one of the most abundant materials on earth, removing any concerns about availability. The flood gates now opened to this new material, and the manufacturing FIG. 1.1 and design technology improved steadily through the following years to the current high Jack St. Clair Kilby. level of sophistication. As time moved on, however, the field of electronics became increasingly sensitive to issues of speed. Computers were operating at higher and higher speeds, and communica- tion systems were operating at higher levels of performance. A semiconductor material capable of meeting these new needs had to be found. The result was the development of the first GaAs transistor in the early 1970s. This new transistor had speeds of operation up to five times that of Si. The problem, however, was that because of the years of intense design efforts and manufacturing improvements using Si, Si transistor networks for most applications were cheaper to manufacture and had the advantage of highly efficient design strategies. GaAs was more difficult to manufacture at high levels of purity, was more ex- pensive, and had little design support in the early years of development. However, in time the demand for increased speed resulted in more funding for GaAs research, to the point that today it is often used as the base material for new high-speed, very large scale integrated (VLSI) circuit designs. This brief review of the history of semiconductor materials is not meant to imply that COVALENT BONDING 3 GaAs will soon be the only material appropriate for solid-state construction. Germanium AND INTRINSIC MATERIALS devices are still being manufactured, although for a limited range of applications. Even though it is a temperature-sensitive semiconductor, it does have characteristics that find application in a limited number of areas. Given its availability and low manufacturing costs, it will continue to find its place in product catalogs. As noted earlier, Si has the benefit of years of development, and is the leading semiconductor material for electronic components and ICs. In fact, Si is still the fundamental building block for Intel’s new line of processors. 1.3 COVALENT BONDING AND INTRINSIC MATERIALS To fully appreciate why Si, Ge, and GaAs are the semiconductors of choice for the elec- tronics industry requires some understanding of the atomic structure of each and how the atoms are bound together to form a crystalline structure. The fundamental components of an atom are the electron, proton, and neutron. In the lattice structure, neutrons and protons form the nucleus and electrons appear in fixed orbits around the nucleus. The Bohr model for the three materials is provided in Fig. 1.3. Valence shell (Four valence electrons) Valence electron FIG. 1.2 Shells Intel® Core™ i7 Extreme Edition Processor. + + Orbiting electrons Nucleus Silicon Germanium (a) (b) Three valence Five valence electrons electrons + + Gallium Arsenic (c) FIG. 1.3 Atomic structure of (a) silicon; (b) germanium; and (c) gallium and arsenic. As indicated in Fig. 1.3, silicon has 14 orbiting electrons, germanium has 32 electrons, gallium has 31 electrons, and arsenic has 33 orbiting electrons (the same arsenic that is a very poisonous chemical agent). For germanium and silicon there are four electrons in the outermost shell, which are referred to as valence electrons. Gallium has three valence electrons and arsenic has five valence electrons. Atoms that have four valence electrons are called tetravalent, those with three are called trivalent, and those with five are called pentavalent. The term valence is used to indicate that the potential (ionization potential) required to remove any one of these electrons from the atomic structure is significantly lower than that required for any other electron in the structure. 4 SEMICONDUCTOR DIODES – – – – Si – – Si – – Si – – – – Sharing of electrons – – – – Si – – Si – – Si – – – – Valence electrons – – – – Si – – Si – – Si – – – – FIG. 1.4 Covalent bonding of the silicon atom. In a pure silicon or germanium crystal the four valence electrons of one atom form a bonding arrangement with four adjoining atoms, as shown in Fig. 1.4. This bonding of atoms, strengthened by the sharing of electrons, is called covalent bonding. Because GaAs is a compound semiconductor, there is sharing between the two different atoms, as shown in Fig. 1.5. Each atom, gallium or arsenic, is surrounded by atoms of the complementary type. There is still a sharing of electrons similar in structure to that of Ge and Si, but now five electrons are provided by the As atom and three by the Ga atom. – – – – – As – – As – – – Ga – – – – – Ga – – – Ga – – As – – – – – – – – – As – – – – As – – – Ga Ga – – – – – – – As – – FIG. 1.5 Covalent bonding of the GaAs crystal. Although the covalent bond will result in a stronger bond between the valence electrons and their parent atom, it is still possible for the valence electrons to absorb sufficient kinetic energy from external natural causes to break the covalent bond and assume the “free” state. The term free is applied to any electron that has separated from the fixed lattice structure and is very sensitive to any applied electric fields such as established by voltage sources or any difference in potential. The external causes include effects such as light energy in the form of photons and thermal energy (heat) from the surrounding medium. At room temperature there are approximately 1.5 : 1010 free carriers in 1 cm3 of intrinsic silicon material, that is, 15,000,000,000 (15 billion) electrons in a space smaller than a small sugar cube—an enormous number. The term intrinsic is applied to any semiconductor material that has been carefully ENERGY LEVELS 5 refined to reduce the number of impurities to a very low level—essentially as pure as can be made available through modern technology. The free electrons in a material due only to external causes are referred to as intrinsic car- riers. Table 1.1 compares the number of intrinsic carriers per cubic centimeter (abbreviated ni) for Ge, Si, and GaAs. It is interesting to note that Ge has the highest number and GaAs the lowest. In fact, Ge has more than twice the number as GaAs. The number of carriers in the intrinsic form is important, but other characteristics of the material are more significant in determining its use in the field. One such factor is the relative mobility (mn) of the free carriers in the material, that is, the ability of the free carriers to move throughout the mate- rial. Table 1.2 clearly reveals that the free carriers in GaAs have more than five times the mobility of free carriers in Si, a factor that results in response times using GaAs electronic devices that can be up to five times those of the same devices made from Si. Note also that free carriers in Ge have more than twice the mobility of electrons in Si, a factor that results in the continued use of Ge in high-speed radio frequency applications. TABLE 1.1 Intrinsic Carriers ni TABLE 1.2 Relative Mobility Factor mn Intrinsic Carriers Semiconductor (per cubic centimeter) Semiconductor Mn (cm2/V·s) GaAs 1.7 : 106 Si 1500 Si 1.5 : 1010 Ge 3900 Ge 2.5 : 1013 GaAs 8500 One of the most important technological advances of recent decades has been the abil- ity to produce semiconductor materials of very high purity. Recall that this was one of the problems encountered in the early use of silicon—it was easier to produce germanium of the required purity levels. Impurity levels of 1 part in 10 billion are common today, with higher levels attainable for large-scale integrated circuits. One might ask whether these extremely high levels of purity are necessary. They certainly are if one considers that the addition of one part of impurity (of the proper type) per million in a wafer of silicon material can change that material from a relatively poor conductor to a good conductor of electricity. We obviously have to deal with a whole new level of comparison when we deal with the semiconductor medium. The ability to change the characteristics of a material through this process is called doping, something that germanium, silicon, and gallium arsenide readily and easily accept. The doping process is discussed in detail in Sections 1.5 and 1.6. One important and interesting difference between semiconductors and conductors is their reaction to the application of heat. For conductors, the resistance increases with an increase in heat. This is because the numbers of carriers in a conductor do not increase significantly with temperature, but their vibration pattern about a relatively fixed location makes it in- creasingly difficult for a sustained flow of carriers through the material. Materials that react in this manner are said to have a positive temperature coefficient. Semiconductor materials, however, exhibit an increased level of conductivity with the application of heat. As the tem- perature rises, an increasing number of valence electrons absorb sufficient thermal energy to break the covalent bond and to contribute to the number of free carriers. Therefore: Semiconductor materials have a negative temperature coefficient. 1.4 ENERGY LEVELS Within the atomic structure of each and every isolated atom there are specific energy levels associated with each shell and orbiting electron, as shown in Fig. 1.6. The energy levels associated with each shell will be different for every element. However, in general: The farther an electron is from the nucleus, the higher is the energy state, and any electron that has left its parent atom has a higher energy state than any electron in the atomic structure. Note in Fig. 1.6a that only specific energy levels can exist for the electrons in the atomic structure of an isolated atom. The result is a series of gaps between allowed energy levels 6 SEMICONDUCTOR Energy DIODES Valence level (outermost shell) Energy gap Second level (next inner shell) Energy gap Third level (etc.) etc. Nucleus (a) Energy Electrons Energy Energy Conduction band "free" to establish conduction Conduction band – – – – The bands Conduction band overlap – – – – E g > 5 eV Eg Unable to reach Valence band conduction level – – Valence – – – – – – electrons Valence band Conductor – – – – bound to Valence band the atomic stucture Insulator E g = 0.67 eV (Ge) E g = 1.1 eV (Si) E g = 1.43 eV (GaAs) Semiconductor (b) FIG. 1.6 Energy levels: (a) discrete levels in isolated atomic structures; (b) conduction and valence bands of an insulator, a semiconductor, and a conductor. where carriers are not permitted. However, as the atoms of a material are brought closer together to form the crystal lattice structure, there is an interaction between atoms, which will result in the electrons of a particular shell of an atom having slightly different energy levels from electrons in the same orbit of an adjoining atom. The result is an expansion of the fixed, discrete energy levels of the valence electrons of Fig. 1.6a to bands as shown in Fig. 1.6b. In other words, the valence electrons in a silicon material can have varying energy levels as long as they fall within the band of Fig. 1.6b. Figure l.6b clearly reveals that there is a minimum energy level associated with electrons in the conduction band and a maximum energy level of electrons bound to the valence shell of the atom. Between the two is an energy gap that the electron in the valence band must overcome to become a free carrier. That energy gap is different for Ge, Si, and GaAs; Ge has the smallest gap and GaAs the largest gap. In total, this simply means that: An electron in the valence band of silicon must absorb more energy than one in the valence band of germanium to become a free carrier. Similarly, an electron in the valence band of gallium arsenide must gain more energy than one in silicon or germanium to enter the conduction band. This difference in energy gap requirements reveals the sensitivity of each type of semiconductor to changes in temperature. For instance, as the temperature of a Ge sample increases, the number of electrons that can pick up thermal energy and enter the conduction band will increase quite rapidly because the energy gap is quite small. However, the number of electrons entering the conduction band for Si or GaAs would be a great deal less. This sensitivity to changes in energy level can have positive and negative effects. The design of photodetectors sensitive to light and security systems sensitive to heat would appear to be an excellent area of application for Ge devices. However, for transistor networks, where stability is a high priority, this sensitivity to temperature or light can be a detrimental factor. The energy gap also reveals which elements are useful in the construction of light-emitting n-TYPE AND p-TYPE 7 devices such as light-emitting diodes (LEDs), which will be introduced shortly. The wider MATERIALS the energy gap, the greater is the possibility of energy being released in the form of visible or invisible (infrared) light waves. For conductors, the overlapping of valence and conduc- tion bands essentially results in all the additional energy picked up by the electrons being dissipated in the form of heat. Similarly, for Ge and Si, because the energy gap is so small, most of the electrons that pick up sufficient energy to leave the valence band end up in the conduction band, and the energy is dissipated in the form of heat. However, for GaAs the gap is sufficiently large to result in significant light radiation. For LEDs (Section 1.9) the level of doping and the materials chosen determine the resulting color. Before we leave this subject, it is important to underscore the importance of understand- ing the units used for a quantity. In Fig. 1.6 the units of measurement are electron volts (eV). The unit of measure is appropriate because W (energy) = QV (as derived from the defining equation for voltage: V = W/Q). Substituting the charge of one electron and a potential dif- ference of 1 V results in an energy level referred to as one electron volt. That is, W = QV = (1.6 * 10-19 C)(1 V) = 1.6 * 10-19 J and 1 eV = 1.6 * 10-19 J (1.1) 1.5 n-TYPE AND p-TYPE MATERIALS Because Si is the material used most frequently as the base (substrate) material in the con- struction of solid-state electronic devices, the discussion to follow in this and the next few sections deals solely with Si semiconductors. Because Ge, Si, and GaAs share a similar covalent bonding, the discussion can easily be extended to include the use of the other materials in the manufacturing process. As indicated earlier, the characteristics of a semiconductor material can be altered sig- nificantly by the addition of specific impurity atoms to the relatively pure semiconductor material. These impurities, although only added at 1 part in 10 million, can alter the band structure sufficiently to totally change the electrical properties of the material. A semiconductor material that has been subjected to the doping process is called an extrinsic material. There are two extrinsic materials of immeasureable importance to semiconductor device fabrication: n-type and p-type materials. Each is described in some detail in the following subsections. n-Type Material Both n-type and p-type materials are formed by adding a predetermined number of impurity atoms to a silicon base. An n-type material is created by introducing impurity elements that have five valence electrons ( pentavalent), such as antimony, arsenic, and phosphorus. Each is a member of a subset group of elements in the Periodic Table of Elements referred to as Group V because each has five valence electrons. The effect of such impurity elements is indicated in Fig. 1.7 (using antimony as the impurity in a silicon base). Note that the four covalent bonds are still present. There is, however, an additional fifth electron due to the impurity atom, which is unassociated with any particular covalent bond. This remaining electron, loosely bound to its parent (antimony) atom, is relatively free to move within the newly formed n-type material. Since the inserted impurity atom has donated a relatively “free” electron to the structure: Diffused impurities with five valence electrons are called donor atoms. It is important to realize that even though a large number of free carriers have been estab- lished in the n-type material, it is still electrically neutral since ideally the number of posi- tively charged protons in the nuclei is still equal to the number of free and orbiting negatively charged electrons in the structure. 8 SEMICONDUCTOR DIODES – – – – Si – – Si – – Si – – – – Fifth valence electron of antimony – – – – – Si – – Sb – – Si – – – – Antimony (Sb) impurity – – – – Si – – Si – – Si – – – – FIG. 1.7 Antimony impurity in n-type material. The effect of this doping process on the relative conductivity can best be described through the use of the energy-band diagram of Fig. 1.8. Note that a discrete energy level (called the donor level ) appears in the forbidden band with an Eg significantly less than that of the intrinsic material. Those free electrons due to the added impurity sit at this energy level and have less difficulty absorbing a sufficient measure of thermal energy to move into the conduction band at room temperature. The result is that at room temperature, there are a large number of carriers (electrons) in the conduction level, and the conductivity of the ma- terial increases significantly. At room temperature in an intrinsic Si material there is about one free electron for every 1012 atoms. If the dosage level is 1 in 10 million (107), the ratio 1012>107 ⫽ 105 indicates that the carrier concentration has increased by a ratio of 100,000:1. Energy Conduction band E g = considerably less than in Fig. 1.6(b) for semiconductors – – – – Eg for intrinsic Donor energy level materials – – – – Valence band FIG. 1.8 Effect of donor impurities on the energy band structure. p-Type Material The p-type material is formed by doping a pure germanium or silicon crystal with impurity atoms having three valence electrons. The elements most frequently used for this purpose are boron, gallium, and indium. Each is a member of a subset group of elements in the Peri- odic Table of Elements referred to as Group III because each has three valence electrons. The effect of one of these elements, boron, on a base of silicon is indicated in Fig. 1.9. Note that there is now an insufficient number of electrons to complete the covalent bonds of the newly formed lattice. The resulting vacancy is called a hole and is represented by a small circle or a plus sign, indicating the absence of a negative charge. Since the resulting vacancy will readily accept a free electron: The diffused impurities with three valence electrons are called acceptor atoms. The resulting p-type material is electrically neutral, for the same reasons described for the n-type material. n-TYPE AND p-TYPE 9 – – – MATERIALS – Si – – Si – – Si – – – Void – (O or +) – – – – Si – – B – Si – – – Boron (B) – impurity – – – – Si – – Si – – Si – – – – FIG. 1.9 Boron impurity in p-type material. Electron versus Hole Flow The effect of the hole on conduction is shown in Fig. 1.10. If a valence electron acquires sufficient kinetic energy to break its covalent bond and fills the void created by a hole, then a vacancy, or hole, will be created in the covalent bond that released the electron. There is, therefore, a transfer of holes to the left and electrons to the right, as shown in Fig. 1.10. The direction to be used in this text is that of conventional flow, which is indicated by the direction of hole flow. – – – – Si – – B – – Si – – B – – Si – – B – – – – – – – (a) (c) Hole flow Electron flow (b) FIG. 1.10 Electron versus hole flow. Majority and Minority Carriers In the intrinsic state, the number of free electrons in Ge or Si is due only to those few elec- trons in the valence band that have acquired sufficient energy from thermal or light sources to break the covalent bond or to the few impurities that could not be removed. The vacan- cies left behind in the covalent bonding structure represent our very limited supply of holes. In an n-type material, the number of holes has not changed significantly from this intrinsic level. The net result, therefore, is that the number of electrons far outweighs the number of holes. For this reason: In an n-type material (Fig. 1.11a) the electron is called the majority carrier and the hole the minority carrier. For the p-type material the number of holes far outweighs the number of electrons, as shown in Fig. 1.11b. Therefore: In a p-type material the hole is the majority carrier and the electron is the minority carrier. When the fifth electron of a donor atom leaves the parent atom, the atom remaining ac- quires a net positive charge: hence the plus sign in the donor-ion representation. For similar reasons, the minus sign appears in the acceptor ion. 10 SEMICONDUCTOR Donor ions Acceptor ions DIODES Majority + –– + – + – – – – – carriers – – + – + – – + – – – – – + – – + + Minority Majority – – – + – – + carrier carriers – – Minority n-type p-type carrier (a) (b) FIG. 1.11 (a) n-type material; (b) p-type material. The n- and p-type materials represent the basic building blocks of semiconductor devices. We will find in the next section that the “joining” of a single n-type material with a p-type ma- terial will result in a semiconductor element of considerable importance in electronic systems. 1.6 SEMICONDUCTOR DIODE Now that both n- and p-type materials are available, we can construct our first solid-state electronic device: The semiconductor diode, with applications too numerous to mention, is created by simply joining an n-type and a p-type material together, nothing more, just the joining of one material with a majority carrier of electrons to one with a majority carrier of holes. The basic simplicity of its construction simply reinforces the importance of the development of this solid-state era. No Applied Bias (V ⴝ 0 V) At the instant the two materials are “joined” the electrons and the holes in the region of the junction will combine, resulting in a lack of free carriers in the region near the junction, as shown in Fig. 1.12a. Note in Fig. 1.12a that the only particles displayed in this region are the positive and the negative ions remaining once the free carriers have been absorbed. This region of uncovered positive and negative ions is called the depletion region due to the “depletion” of free carriers in the region. If leads are connected to the ends of each material, a two-terminal device results, as shown in Figs. 1.12a and 1.12b. Three options then become available: no bias, forward bias, and reverse bias. The term bias refers to the application of an external voltage across the two terminals of the device to extract a response. The condition shown in Figs. 1.12a and 1.12b is the no-bias situation because there is no external voltage applied. It is simply a diode with two leads sitting isolated on a laboratory bench. In Fig. 1.12b the symbol for a semiconductor diode is provided to show its correspondence with the p–n junction. In each figure it is clear that the applied voltage is 0 V (no bias) and the resulting current is 0 A, much like an isolated resistor. The absence of a voltage across a resistor results in zero current through it. Even at this early point in the discussion it is important to note the polarity of the voltage across the diode in Fig. 1.12b and the direction given to the current. Those polarities will be recognized as the defined polarities for the semiconductor diode. If a voltage applied across the diode has the same polarity across the diode as in Fig. 1.12b, it will be considered a positive voltage. If the reverse, it is a negative voltage. The same standards can be applied to the defined direction of current in Fig. 1.12b. Under no-bias conditions, any minority carriers (holes) in the n-type material that find themselves within the depletion region for any reason whatsoever will pass quickly into the p-type material. The closer the minority carrier is to the junction, the greater is the attraction for the layer of negative ions and the less is the opposition offered by the positive ions in the depletion region of the n-type material. We will conclude, therefore, for future discus- sions, that any minority carriers of the n-type material that find themselves in the depletion region will pass directly into the p-type material. This carrier flow is indicated at the top of Fig. 1.12c for the minority carriers of each material. Depletion region SEMICONDUCTOR DIODE 11 –– – ++ – – – + + + – – +– – – – –– –– + + – + – – ++ – – ++ + – + – – – – ++ + – – – – ++ – – – – – + + + – – – ++ – – + – Metal contact p n ID = 0 mA ID = 0 mA + VD = 0 V – (no bias) (a) Minority carrier flow + VD = 0 V – Ielectron Ihole (no bias) ID = 0 mA Ihole Ielectron p n Majority carrier flow (b) (c) FIG. 1.12 A p–n junction with no external bias: (a) an internal distribution of charge; (b) a diode symbol, with the defined polarity and the current direction; (c) demonstration that the net carrier flow is zero at the external terminal of the device when VD ⫽ 0 V. The majority carriers (electrons) of the n-type material must overcome the attractive forces of the layer of positive ions in the n-type material and the shield of negative ions in the p-type material to migrate into the area beyond the depletion region of the p-type mate- rial. However, the number of majority carriers is so large in the n-type material that there will invariably be a small number of majority carriers with sufficient kinetic energy to pass through the depletion region into the p-type material. Again, the same type of discussion can be applied to the majority carriers (holes) of the p-type material. The resulting flow due to the majority carriers is shown at the bottom of Fig. 1.12c. A close examination of Fig. 1.12c will reveal that the relative magnitudes of the flow vectors are such that the net flow in either direction is zero. This cancellation of vectors for each type of carrier flow is indicated by the crossed lines. The length of the vector representing hole flow is drawn longer than that of electron flow to demonstrate that the two magnitudes need not be the same for cancellation and that the doping levels for each material may result in an unequal carrier flow of holes and electrons. In summary, therefore: In the absence of an applied bias across a semiconductor diode, the net flow of charge in one direction is zero. In other words, the current under no-bias conditions is zero, as shown in Figs. 1.12a and 1.12b. Reverse-Bias Condition (VD * 0 V) If an external potential of V volts is applied across the p–n junction such that the positive terminal is connected to the n-type material and the negative terminal is connected to the p-type material as shown in Fig. 1.13, the number of uncovered positive ions in the deple- tion region of the n-type material will increase due to the large number of free electrons drawn to the positive potential of the applied voltage. For similar reasons, the number of uncovered negative ions will increase in the p-type material. The net effect, therefore, is a 12 SEMICONDUCTOR Is Minority-carrier flow DIODES

Electronic Devices and Circuit Theory - 11th Edition.pdf

Document Details

Tags

Related

Full Transcript

Upgrade to continue