Applied Electronics - Chapter Three (3rd Year Physics) PDF

Applied Electronics Chapter Three 3th Year l Physics CHAPTER Three Load lines and DC Bias circuit 3.1 Introduction The analysis or design of a transistor amplifier requires a knowledge of both the dc and the ac re...

Applied Electronics Chapter Three 3th Year l Physics CHAPTER Three Load lines and DC Bias circuit 3.1 Introduction The analysis or design of a transistor amplifier requires a knowledge of both the dc and the ac response of the system. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an external energy source. Important of VCE: The voltage VCE is very important in checking whether the transistor is (a) Working in cut-off, VCC=VCE , IC =0 ………………………..Off (b) Saturation VCE=0 or well into saturation. VCE=mV, at VCE=0, Ic=Ic(sat)=max. Value……………..ON (c) Active, for amplifier operation, 1 VCE = VCC 2 Transistor is operated at approximately ½ ON. In this way, variations in IB in either direction will control IC in both directions. In other words, when IB increases or decreases, IC also increases or decreases. However, if IB is OFF, IC is also OFF. On the other hand, if collector has been turned fully ON, maximum IC flows. Hence, no further increase in IB can be reflected in IC. 3.2 D.C. Load Line For drawing the dc load line of a transistor, one needs to know only its cut-off and saturation points. It is a straight line jointing these two points. For the CE circuit of Fig. (3.3, a), the load line is drawn in Fig. (3.3, b). A is the cut-off point and B is the saturation point. The voltage equation of the collector-emitter is VCC=ICRL+VCE VCC VCE IC = − RL RL Consider the following two particular cases: (i) When IC = 0, VCE = VCC -----cutoff point (A) 42 Applied Electronics Chapter Three 3th Year l Physics VCC (ii) When VCE=0, IC = ------saturation point (B) RL Fig. (3.3,a) Fig. (3.3,b) Obviously, load line can be drawn if only VCC and RL are known. Incidentally slope of the load line AB = –1/RL 3.3 Load-Line Analysis The same approach can be applied to BJT networks. The characteristics of the BJT are superimposed on a plot of the network equation defined by the same axis parameters. The load resistor RC for the fixed-bias configuration will define the slope of the network equation and the resulting intersection between the two plots. The smaller the load resistance, the steeper the slope of the network load line. The network of Fig. 3.4 establishes an output equation that relates the variables IC and VCE in the following manner: VCE = VCC - ICRC Fig.3.4 Load-line analysis the network 43 Applied Electronics Chapter Three 3th Year l Physics The output characteristics of the transistor also relate the same two variables IC and VCE as shown in Fig. 3.5 Fig. 3.5: the device characteristics. The device characteristics of I C versus V CE are provided in Fig. 3.5. We must now superimpose the straight line defined by Eq. on the characteristics. VCE = VCC - ICRC The most direct method of plotting Eq. (on the output characteristics is to use the fact that a straight line is defined by two points. If we choose IC to be 0 mA, we are specifying the horizontal axis as the line on which one point is located. By substituting IC =0 mA into Eq. we find that VCE = VCC - (0)RC and VCE = VCC when IC=0 mA defining one point for the straight line as shown in Fig. 3.6. 44 Applied Electronics Chapter Three 3th Year l Physics Fig. 3.6 Fixed-bias load line. If we now choose VCE to be 0 V, which establishes the vertical axis as the line on which the second point will be defined, we find that IC is determined by the following equation: 0 = VCC – ICRC V  I C =  CC   RC  VCE =0V The resulting line on the graph of Fig. 3.6 is called the load line because it is defined by the load resistor RC. By solving for the resulting level of IB , we can establish the actual Q -point as shown in Fig. 3.6. If the level of IB is changed by varying the value of RB , the Q -point moves up or down the load line as shown in Fig. 3.7 for increasing values of IB. 45 Applied Electronics Chapter Three 3th Year l Physics Fig. 3.7 Movement of the Q-point with increasing level of IB. If VCC is held fixed and RC increased, the load line will shift as shown in Fig. 3.8. Fig. 3.8 Effect of an increasing level of RC on the load line and the Q-point. If IB is held fixed, the Q -point will move as shown in the same figure. If RC is fixed and VCC decreased, the load line shifts as shown in Fig. 3.9. 46 Applied Electronics Chapter Three 3th Year l Physics Fig. 3.9 Effect of lower values of VCC on the load line and the Q-point Example 3.1- For the CE circuit of Fig. 3.1, find the value of VCE. Take β = 100 and neglect VBE. Is the transistor working in cut-off or saturation? Solution. IB = VCC/RB= 10/100 = 0.1 A IC = β IB = 100 × 0.1 = 10 A VCE = VCC – IC RL = 10 – 10 × 1 = 0 Obviously, the transistor is operating just at saturation and not well into saturation. Fig. (3.1) 47 Applied Electronics Chapter Three 3th Year l Physics Example 3.2- Find out whether the transistor of Fig. 3.2 is working in saturation or well into saturation. Neglect VBE. Solution. IB=10/100.2=0.0998 A IC=βIB=100*0.0998=9.98A Then, VCE = VCC – IC RL = 10 – (9.98 × 1) = 0.02 V It means that the transistor is working well into saturation. Fig. (3.2) Example 3.3 Given the load line of figure below and the defined Q -point, determine the required values of VCC , RC , and RB for a fixed-bias configuration. Solution: From Fig. VCE = VCC = 20 V at IC = 0 mA 48 Applied Electronics Chapter Three 3th Year l Physics V  I C =  CC  at VCE =0  RC  V  20V I C =  CC  = = 2 K  RC  10mA V = V BE  I B =  CC   RB  V = VBE  20V − 0.7V RB =  CC = 772 K  IB  25A The load-line analysis of the emitter-bias network is only slightly different from that encountered for the fixed-bias configuration. The level of IB as determined by Eq. defines the level of IB on the characteristics of Fig. 3.25 (denoted IBQ).  VCC = VBE  IB =    RB + (  + 1) R E  The collector–emitter loop equation that defines the load line is VCE = VCC - IC(RC + RE) Fig. 3.10 Load line for the emitter-bias configuration 49 Applied Electronics Chapter Three 3th Year l Physics Choosing I C = 0 mA gives VCE = VCC when IC=0 mA as obtained for the fixed-bias configuration. Choosing V CE = 0 V give  VCC  IC =   at VCE =0  RC + RE  as shown in Fig. 3.10. Different levels of IBQ will, of course, move the Q -point up or down the load line. Example 3.4 a. Draw the load line for the network of Fig. 3.26a on the characteristics for the transistor appearing in Fig. 3.11. b. For a Q -point at the intersection of the load line with a base current of 15 m A , find the values of ICQ and VCEQ. c. Determine the dc beta at the Q -point. d. Using the beta for the network determined in part c, calculate the required value of RB and suggest a possible standard value. Fig. 3.11network for Example 3.4. Solution: a. Two points on the characteristics are required to draw the load line. At VCE = 0 V 50 Applied Electronics Chapter Three 3th Year l Physics  V  18V I C =  CC  = = 5.45mA  RC + RE  2.2 K + 1.1K At IC =0 mA: VCE =VCC = 18 V The resulting load line appears in Fig. 3.11. b. From the characteristics of Fig. 3.27 we find VCEQ  7.5 V, ICQ  3.3 mA c. The resulting dc beta is: I CQ = = 220 I EQ d.  VCC = VBE  17V − 0.7V IB =  =  RB + (  + 1) R E  RB + (220 + 1)(1.1k) 17V − 0.7V 15A = RB + (220 + 1)(1.1k) RB = 910 K 51 Applied Electronics Chapter Three 3th Year l Physics 3.4 BJT Switches (at cutoff and saturation region) When using BJT as a switch, usually two levels of control signal are employed, with one level, the transistor operates in the cut-off region (open) whereas with the other level, it operates in the saturation region and acts as a short-circuit. Fig. (3.12) Fig. 2.12 (b) shows the condition when control signal vi = 0. In this case, the BE junction is reverse-biased and the transistor is open and, hence acts as an open switch. However, as shown in Fig. 2.12 (c) if vi equals a positive voltage of sufficient magnitude to produce saturation i.e. if vi = vi the transistor acts as a closed switch. 52 Applied Electronics Chapter Three 3th Year l Physics Example 3.5. From the fig 3.5 of BJT circuit find the value of the (RB) required to switch the load fully “ON” when the input terminal voltage exceeds 2.5V. VCC=ICRC+VCE VCC 10 At saturation VCE=0V --- IC max(sat.) = = =5 mA RC 2K IB required for to switch the load fully (ON) = IC 5 IB = = = 0.025mA β 200 Vin − VBE 2.5 − 0.7 RB = = = 72K IB 0.025 3.5 Notation for Voltags and Currents In order to avoid confusion while dealing with dc and ac voltages and currents, following notation will be employed : 1. For d.c. or non-time-varying quantities We will use capital letters with capital subscripts such as IE, IB, IC — for dc currents VE, VB, VC — for dc voltages to ground VBE, VCB, VCE — for dc potential differences VEE, VCC, VBB — for dc source or supply voltages 2. For ac quantities 53 Applied Electronics Chapter Three 3th Year l Physics We will use the following symbols : ie, ib, ic — for instantaneous values of ac currents Ie, Ib, Ic — for r.m.s values of a.c. currents v e, v b, v c — for instantaneous values of a.c. voltages to ground vbe, veb, vce — for a.c. voltage differences 3. Total ac and dc voltages and currents In this case, we will use a hybrid notation. For example, iE will be used to represent the total emitter current, i.e. sum of dc and ac currents in the emitter. Fig. 3.13 illustrates the notation discussed above. Fig. 3.13 3.6. Transistor AC/DC Analysis In Fig. Fig. 3.13 is shown a CE amplifier circuit having an ac signal voltage vbe applied across its E/B junction. This voltage will be added to the dc voltage V BE as if the two were connected in series. The resultant voltage is shown in Fig. 3.13 (b) which shows ac voltage riding the d.c. level. The variations in the resultant output voltage VCE [Fig. 3.14 (c)] can be expressed in terms of the increase/ decrease notation. It will be assumed that VBE is such as to bias VCE at VCC when no a.c. signal is applied. Fig. 3.13) 54 Applied Electronics Chapter Three 3th Year l Physics 3.7 D.C load Line (Active Region) All operating points (like C, D, E etc. in Fig. 3.3, b) lying between cut-off and saturation points form the active region of the transistor. In this region, E/B junction is forward-biased and C/B junction is reverse-biased—conditions necessary for the proper operation of a transistor. 3.8 Quiescent Point It is a point on the dc load line, which represents the values of IC and VCE that exist in a transistor circuit when no input signal is applied. It is also known as the dc operating point or working point. The best position for this point is midway between cut-off and saturation points where 1 VCE = VCC (like point D in Fig. 3.3, b). 2 Now let’s apple AC to the BJT circuit: Position of the Q-point on the dc load line determines the maximum signal that we can get from the circuit before clipping occurs. Consider the cases shown in Fig. 3.13. In Fig. 3.14 (a), when Q is located near cut-off point, signal first starts to clip at A. It is called cut-off clipping because the positive swing of the signal drives the transistor to cut-off. In fact, as seen from Fig. 3.14 (a), maximum positive swing is = ICQ Rac. Fig. 3.14. 55 Applied Electronics Chapter Three 3th Year l Physics If the Q-point Q2 is located near saturation point, then clipping first starts at point B as shown in Fig. 3.14 (b). It is caused by saturation. The maximum negative swing = VCEQ. In Fig. 3.14 (c), the Q-point Q3 is located at the center of the load line. In this condition, we get the maximum possible output signal. The point Q3 gives the optimum Q-point. The maximum undistorted signal = 2VCEQ Example 3.6. For the circuit shown in Fig. 3.14 (a), draw the dc load line and locate its quiescent or dc working point, neglecting VBE. Fig. 3.14 Solution. The cut-off point is easily found because it lies along X-axis where VCB = VCC = 20 V i.e. point A in Fig. 3.14 (b). At saturation point B, saturation value of collector current is IC (sat) = VCC/RL = 20 V/5 K = 4 mA. The line AB represents the load line for the given circuit. We will now find the actual operating point. IE = VEE /RE= 30 V/15 K = 2 mA —neglecting VBE IC = αIE ≅IE = 2 mA; ∴VCB = VCC – IC RL = 20 – 2 × 5 = 10 V Hence, Q-point is located at (10 V ; 2 mA) as shown in Fig. 3.14 (b) Example 3.7. In the CB circuit of Figure , find 56 Applied Electronics Chapter Three 3th Year l Physics (a) D.C operating point and D.C load line (b) Maximum peak-to-peak unclipped signal (c) the approximate value of ac source voltage that will cause clipping. (a) V IC(sat) = CC = 2mA — point B RL VCB at cut-off =VCC = 20 V —point A Hence, AB is the dc load line and is shown in Fig. 58.3 (b). Now, IE =10/20 = 0.5 mA IC ≈ IE = 0.5 mA VCB = VCC – IC RL= 20 – 0.5 × 10=15 V The Q-point is located at (15 V, 0.5 mA) (b) It is obvious from Fig. 58.3 (b) that maximum positive swing can be from 15 V to 20 V i.e. 5 V only. Of course, on the negative swing, the output swing can go from 15 V down to zero volt. The limiting factor being cut-off on positive half cycle, hence maximum unclipped peak-to-peak voltage that we can get from this circuit is 2 × 5 = 10 V. V R Av = o = L = 10 Rs Rs It means that signal voltage will be amplified 10 times. Hence, maximum value of source voltage for obtaining unclipped or undistorted output is Vo 10Vp.p Vv = = = 1 Vp. p 10 10 Example 3.8. Determine the value of RB required to adjust the circuit of Fig. to optimum operating point. Take β = 50 and VBE = 0.7 V. 57 Applied Electronics Chapter Three 3th Year l Physics Solution. As seen from above Note: The optimum point (ICQ)=IC(sat)/2 , VCE=VCC/2 VCC 20 ICQ = = = 1mA 2R L 2 ∗ 10 The corresponding base current is ICQ IBQ = β VCC=IBRB+VBE VCC − VBE 20 − 0.7 RB = = = 965K IB 20 ∗ 10−6 Example 3.9. The circuit of Fig. is designed to produce nearly constant current through the variable collector load resistance. An ideal 6V source is used to establish the current. Determine (a) value of IC and VE ,(b) range of RC over which the circuit will function properly. Assume silicon transistor and a b large enough to justify the assumptions used. 58 Applied Electronics Chapter Three 3th Year l Physics Solution. (a) IC ≅IE = ( 6 –0.7)/530 = 10 mA VE= 6 – 530 × (10 × 10) = 5.3 V. This voltage will remain constant so long as transistor operation is confined to active region. (b) When RC = 0 VCE = 12 – 5.3 = 6.7 V It is certainly well within the active region. As RC increases, its drop increases and hence, VCE decreases. There will be some value of RC at which active region operation ceases. Now, VCE =12 – 5.3 – IC RC = 6.7 – IC RC Value of RC (max) can be found by putting VCE = 0 ∴ 0 = 6.7 – IC RC (max) or RC(max) = 6.7/IC = 6.7/0.01 = 670Ω Hence, circuit will function as a constant current source so long as RC is in the range 0 < RC < 670. When RC exceeds 670Ω, the BJT becomes saturated. 3.9. Load Line and Output Characteristics Consider a silicon NPN transistor which is connected in CE configuration (Fig. 3.15) and whose output characteristics are given in the right of same figure. First, let us find the cut-off and saturation points for drawing the dc load line: IC(sat) = 10/2 = 5 mA —point B in Fig. 3.15 VCE(cut-off) = VCC = 10 V —point A in Fig. 3.15 The load line is drawn at the right of Fig. 3.15below. 59 Applied Electronics Chapter Three 3th Year l Physics Fig. (3.15) Second: find the Q-point. (VCE,IC), at IB= constant. VCC − VBE 10 − 0.7 IB = = = 20µA RB 470 IC = βIB = 100 ∗ 20 = 2000µ = 2mA VCE = VCC − IC R C = 10 − 2 ∗ 2 = 6V Suppose an Ac input signal voltage injects a sinusoidal base current of peak value 10 μA into the circuit of Fig. 3.13. Obviously, it will swing the operating or Q- point up and down along the load line. When positive half-cycle of IB is applied, the Q-point shifts to point C which lies on the IB= (20 + 10) = 30 μA line IC = 3mA. Hence, VCE = 10 – 2 × 3 = 4 V Similarly, during negative half-cycle of input base current, Q-point shifts to point D which lies on the IB= (20 – 10) = 10 μA line. IC= 1 mA. Hence, VCE = 10 – 2 × 1 = 8 V It is seen that VCE decreases from 6 V to 4V i.e. by a peak value of (6-4) = 2 V when base current goes positive. On the other hand, VCE increases from 6 V to 8 V i.e. by a peak value of (8–6) = 2 V when input base current signal goes negative. Since changes in VCE represent changes in output voltage, it means that when input signal is applied, IB varies according to the signal amplited and causes Ic to vary 60 Applied Electronics Chapter Three 3th Year l Physics from, thereby producing voltage variations incidentally, it may be noted that variation in the voltage drop across RL are exactly the same as in VCE. 3.10. AC Load Line It is the line along which Q-point shifts up and down when changes in output voltage and current of an amplifier are caused by an AC signal. This line is steeper than the dc line but the two intersect at the Q-point determined by biasing dc voltage and currents. AC load line takes into account the AC load resistance whereas DC load line considers only the dc load resistance. AC load line draws as given below 1- The cut-off point is given by VCE (cut-off)=VCEQ+ICQ*Rac ,where Rac is the AC load resistance. 2-Saturation point is given by IC(sat.) =ICQ*Rac It is represented by straight line CQD in Fig. 3.15. The slope of the ac load line is given by y = X* 1/Rac. Fig. (3.16) Example 3.10. Find the dc and ac load lines for CE circuit shown in Fig. , (a) with connecting Rload =(6K), (b) without connecting Rload =(6K). 61 Applied Electronics Chapter Three 3th Year l Physics DC- load line for both case (a,b) will be same : VCE(cutoff)=VCC=20V point (A) , IC(sat)=VCC/(RC+RE) 20/5 = 4mA (point B). Hence, AQB represents dc load line for the given circuit. IE=VE/RE=4/2=2 mA IC≈IE=ICQ VCEQ=VCC-ICQRC-REIEQ VCEQ=20-2*(3+2)=10V So, AC load line for (a) can be find by VCE(cutoff)=VCQ+ICQRac=10+2*2=14V Rac=RC//Rout =6*3/(6+3) IC(sat.)=ICQ+VCEQ/Rac=2+10/2=7mA =2K So, AC load line for (b) can be find by VCE(cutoff)=VCQ+ICQRac=10+2*3=16V IC(sat.)=ICQ+VCEQ/Rac=2+10/3=5.13mA 3.11. Temperature affecting bias variations After chose the best Q-point at the medial load line we must take in considerate the effect of temperature. In practice, it is found that even after careful selection, Q- point tends to shift its position. This bias instability is the direct result of thermal instability which itself is produced by cumulative increase in IC. The collector current for CE circuit is given by IC = βIB + ICEO = βIB + (1 + β) ICO This equation has three variables : β, IB and ICO all of which are found to increase with temperature. In particular, increase in ICO produces significant increase in collector current IC. This leads to increased power dissipation with further increase in temperature and hence IC. Being a cumulative process, it can lead to thermal runaway which will destroy the transistor itself ! However, if by some circuit modification, IC is made to decrease with temperature automatically, then decrease in the term βIB can be made to neutralize the increase 62 Applied Electronics Chapter Three 3th Year l Physics in the term (1 + β) ICO, thereby keeping IC constant. This will achieve thermal stability resulting in bias stability. However, if by some circuit modification, IC is made to decrease with temperature automatically, then decrease in the term βIB can be made to neutralize the increase in the term (1 + β) ICO, thereby keeping IC constant. This will achieve thermal stability resulting in bias stability. 3.12. Stability Factor The degree of success achieved in stabilizing IC in the face of variations in ICO is expressed in terms of current stability factor S. It is defined as the rate of change of IC with respect to ICO when both β and IB (VBE) are held constant. dI ∴S= c - β and IB constant dIco Larger the value of S, greater the thermal instability and vice versa (in view of the above, this factor should, more appropriately, be called instability factor !). The stability factor may be alternatively expressed by using the well-known equation IC = Iβ + (I + β) ICO which, on differentiation with respect to IC, yields. The stability factor of any circuit can be found by using the general formula RB = total series parallel resistance in the base RE = total series dc resistance in the emitter α = dc alpha of the transistor 63 Applied Electronics Chapter Three 3th Year l Physics 3.13 Different Methods for Transistor Biasing Some of the methods used for providing bias for a transistor are : 1. base bias or fixed current bias It is not a very satisfactory method because bias voltages and currents do not remain constant during transistor operation. 2. Base bias with emitter feedback This circuit achieves good stability of dc operating point against changes in β with the help of emitter resistor which causes degeneration to take place. 64 Applied Electronics Chapter Three 3th Year l Physics 1 + 𝑅𝐵 /𝑅𝐸 1 + 300𝐾/1𝐾 𝑆= = =7 1 + 𝑅𝐵 /(1 + 𝐵)𝑅𝐸 1 + 300𝐾/(101 ∗ 1) 3. base bias with collector feedback It is also known as collector-to-base bias or collector feedback bias. It provides better bias stability. 3. base bias with collector and emitter feedbacks It is a combination of (2) and (3) above. 65 Applied Electronics Chapter Three 3th Year l Physics 5. emitter bias with two supplies This circuit uses both a positive and a negative supply voltage. Here, base is at approximately 0 volt i.e. VB ≅ 0. ` 66 # Applied Electronics Chapter Three 3th Year l Physics It is seen that Q-point is very much dependent on temperature and makes the base- bias arrangement very unstable. 3.13 Voltage-Divider Bias Configuration The voltage-divider bias configuration of Fig.3.17 is such a network. If analyzed on an exact basis, the sensitivity to changes in beta is quite small. Fig. 3.17 Voltage-divider bias configuration. If the circuit parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally independent of beta. Recall from previous discussions that a Q -point is defined by a fixed level of ICQ and VCEQ as shown in Fig. 3.18. The level of IBQ will change with the change in beta, but the operating point on the characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters are employed. 67 Applied Electronics Chapter Three 3th Year l Physics Fig. 3.18 Defining the Q-point for the voltage-divider bias configuration. Exact Analysis For the dc analysis the network of Fig. 3.18 can be redrawn as shown in Fig. 3.19 Fig. 3.19 DC components of the voltagedivider configuration. The input side of the network can then be redrawn as shown in Fig. 3.20 for the dc analysis. The Thévenin equivalent network for the network to the left of the base terminal can then be found in the following manner: Fig. 3.20 Redrawing the input side of the network of Fig. 3.28. 68 Applied Electronics Chapter Three 3th Year l Physics RTh The voltage source is replaced by a short-circuit equivalent as shown in Fig. 3.21 : Fig. 3.21 Determining RTh R Th = R1 //R 2 ETh The voltage source VCC is returned to the network and the open-circuit Thévenin voltage of Fig. 3.22 determined as follows: Applying the voltage-divider rule gives R2VCC ETh = VR 2 = R1 + R2 Fig. 3.22 Determining Eth The Thévenin network is then redrawn as shown in Fig. 3.23 , and IBQ can be determined by first applying Kirchhoff’s voltage law in the clockwise direction for the loop indicated: ETh - IBRTh - VBE - IERE = 0 69 Applied Electronics Chapter Three 3th Year l Physics Fig. 3.23 Inserting the Thévenin equivalent circuit. Substituting IE = (β + 1) IB and solving for IB yields ETh − VBE IB = RTh + (  + 1) RE Although Eq. (3.30) initially appears to be different from those developed earlier, note that the numerator is again a difference of two voltage levels and the denominator is the base resistance plus the emitter resistor reflected by (  + 1) certainly very similar to Eq. (3.17). Once IB is known, the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration. That is, VCE = VCC - IC (RC + RE) which is exactly the same as Eq.(3.19). The remaining equations for VE, VC, and V B are also the same as obtained for the emitter-bias configuration. 70 Applied Electronics Chapter Three 3th Year l Physics EXAMPLE Determine the dc bias voltage V CONFIGURATION CE and the current I C for the voltage divider configuration of Figure below. Solution: RTh = R1 //R2 (39 K + 3.9 K) RTh = = 3.35 K (39 K * 3.9 K) R2VCC 3.9 K * 22V ETh = VR 2 = = = 2V R1 + R2 (39 K * 3.9 K) ETh − VBE 2V − 0.7V IB = = 8.38A RTh + (  + 1) RE 3.35V + (100 + 1)(1.5K) IC = β*IB = (100)(8.38 mA) = 0.84 mA VCE = VCC - IC(RC + RE) = 22 V - (0.84 mA)(10 kΏ + 1.5 kΏ) = 22 V - 9.66 V = 12.34 V 71 Applied Electronics Chapter Three 3th Year l Physics 3.14 Darlington Transistors The Darlington Transistor named after its inventor, Sidney Darlington is a special arrangement of two standard NPN or PNP bipolar junction transistors (BJT) connected together. A Darlington Transistor configuration, also known as a “Darlington pair” or “super-alpha circuit”, consist of two NPN or PNP transistors connected together so that the emitter current of the first transistor TR1 becomes the base current of the second transistor TR2. Using the NPN Darlington pair as the example, the collectors of two transistors are connected together, and the emitter of TR1 drives the base of TR2. This configuration achieves β multiplication because for a base current IB, the collector current is β.IB where the current gain is greater than one, or unity and this is defined as: ICt=IC1+IC2 IC= β1IB+ β2IB2 But the base current, IB2 is equal to transistor TR1 emitter current, IE1 as the emitter of TR1 is connected to the base of TR2. Therefore: IB2=IE1=IC1+IB=β1IB+IB=( β1+1)IB Then substituting in the first equation: IC= β1IB1+ β2.( β1+1).IB1 72 Applied Electronics Chapter Three 3th Year l Physics IC= β1IB1+ β2. β1 IB1 + β2.IB1 IC= (β1+ β2. β1+β2)IB1 Where β1 and β2 are the gains of the individual transistors If β1 and β2 are high enough (hundreds), this relation can be approximated with: Bt = B1.B2 This means that the overall current gain, β is given by the gain of the first transistor multiplied by the gain of the second transistor as the current gains of the two transistors multiply. In other words, a pair of bipolar transistors combined together to make a single Darlington transistor pair can be regarded as a single transistor with a very high value of β and consequently a high input resistance. advantages 1- The important point to remember is that the Darlington Pair is made up of two transistors and when they are arranged as shown in the circuit they are used to amplify weak signals. The circuit to the below shows a single transistor. When the switch is pressed current flows from the 9v to the 0v and also to the base of the transistor. This allows the transistor to switch and in turn, current / voltage flows through the bulb, which lights. However, there is a potential problem with this circuit. The signal / current at the base of the transistor may be too weak to switch the transistor and allow the bulb to light or it may flicker on and off. A possible solution is seen to the right. A second transistor is added to the circuit, the circuit is now likely to work as the original signal / current is amplified. The amount by which the weak signal is amplified is called the ‘GAIN’. 73 Applied Electronics Chapter Three 3th Year l Physics 2- A Darlington pair is sufficiently sensitive to respond to the small current passed by your skin and it can be used to make a touch-switch as shown in the diagram. For this circuit which just lights an LED the two transistors can be any general purpose low power transistors. The 100k resistor protects the transistors if the contacts are linked with a piece of wire. Disadvantages One drawback is an approximate doubling of the base–emitter voltage. Since there are two junctions between the base and emitter of the Darlington transistor, the equivalent base–emitter voltage is the sum of both base–emitter voltages: VBE= VBE+ VBE=2 VBE 74 Applied Electronics Chapter Three 3th Year l Physics For silicon-based technology, where each VBEi is about 0.65 V when the device is operating in the active or saturated region, the necessary base–emitter voltage of the pair is 1.3 V. Example No1 Two NPN transistors are connected together in the form of a Darlington Pair to switch a 12V and 75W halogen lamp. If the forward current gain of the first transistor is 25 and the forward current gain of the second transistor is 80. Ignoring any voltage drops across the two transistors, calculate the maximum base current required to switch the lamp fully-ON. Firstly, the current drawn by the lamp will be equal to the collector current of the second transistor, then: IC = I lamp I lamp=P/V=75/12=6.25mA β1=25 , β2=80 IC= (β1+ β2. β1+β2)IB 𝐼𝐶 𝐼𝐵 = = 2.9µA 𝛽1 + 𝛽1 𝛽2 + 𝛽2 Then we can see that a very small base current of only 2.9µA, such as that supplied by a digital logic gate or the output port of a micro-controller, can be used to switch the 75 Watt lamp “ON” and “OFF”.s If two identical bipolar transistors are used to make a single Darlington device then β1 is equal to β2 and the overall current gain will be given as: If β1= β2 IC= (β2+2 β) IB Generally the value of β2 is much greater than that of 2β, in which case it can be ignored to simplify the maths a little. Then the final equation for two identical transistors configured as a Darlington pair can be written as: IC= β2.IB 75 Applied Electronics Chapter Three 3th Year l Physics Then we can see that for two identical transistors, β2 is used instead of β acting like one big transistor with a huge amount of gain. Darlington transistor pairs with current gains of more than a thousand with maximum collector currents of several amperes are easily available. For example: the NPN TIP120 and its PNP equivalent the TIP125. The advantage of using an arrangement such as this, is that the switching transistor is much more sensitive as only a tiny base current is required to switch a much larger load current as the typical gain of a Darlington configuration can be over 1,000 whereas normally a single transistor stage produces a gain of about 50 to 200. Then we can see that a darlington pair with a gain of 1,000:1, could switch an output current of 1 ampere in the collector-emitter circuit with an input base current of just 1mA. This then makes darlington transistors ideal for interfacing with relays, lamps and motors to low power microcontroller, computer or logic controllers as shown Example No2 In Fig. below, the first transistor has a current gain of 100, and the second transistor has a current gain of 50. What is the base current in the first transistor? 76