UNIT2_COD_2024 (2).pdf

RISC V ARCHITECTURE UNIT 2 – Data Flow Model - RISC-V Mahesh Awati Department of Electronics and Communication Engineering Parallelism and Instructions & Arithmetic for Computer Real Stuff: The rest of RISC V Instruction Set ▪ RISC-V architects partitioned the instruction set into a base archit...

RISC V ARCHITECTURE UNIT 2 – Data Flow Model - RISC-V Mahesh Awati Department of Electronics and Communication Engineering Parallelism and Instructions & Arithmetic for Computer Real Stuff: The rest of RISC V Instruction Set ▪ RISC-V architects partitioned the instruction set into a base architecture (RV32I) and several extensions (A,M,F,D and so on). ▪ Each is named with a letter of the alphabet, and the base architecture is named I for integer. Reference : Computer Organization and Design - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer Real Stuff: The rest of RISC V Instruction Set ▪ The first instruction, auipc, is used for PC-relative memory addressing. Like the lui instruction, it holds a 20-bit constant that corresponds to bits 12 through 31 of an integer. ▪ auipc’s effect is to add this number to the PC and write the sum to a register. Combined with an instruction like addi, it is possible to address any byte of memory within 4 GiB of the PC. Reference : Computer Organization and Design - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer RISC-V Addressing for wide immediate and addresses Addressing beyond the range of jal PC- Relative Addressing ▪ If addresses of the program had to fit in this 20-bit C: 0x7FFF F018 field, it would mean that no program could be bigger than +/- 220, which is far too small to be a realistic option today. ▪ jal rd,imm[20:0] How to jump anywhere in a 32-bit absolute C: 0x00000018 address range ????? ▪ The JALR instruction was defined to enable a two- instruction sequence to jump anywhere in a 32-bit absolute address range. ▪ A LUI instruction can first load rs1 with the upper 20 bits of a target address, then JALR can add in the lower lui x10,0x7FFFF bits. Jalr x1,x10,0x018 ▪ Similarly, AUIPC then JALR can jump anywhere in a 32- x1 = PCnew = X10+ imm[11:0] bit pc-relative address range. Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer RISC-V Addressing for wide immediate and addresses auipc: Add Upper Immediate value to PC and place the result in rd. Syntax: auipc rd, imm[31:12] Example : Assume PC=0x00000008 & imm[31:12]=0x10000 auipc x11, 0x10000 PC = 0x00000 008 = 0x10000 x11 = 0x10000 008 Use: PC+ relative addressing Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer RISC-V Addressing for wide immediate and addresses Use 1: auipc used for PC+relative addressing to calculate base address of symbol defined in data segment Assume base address of num3 in data memory to be accessed is 0x1000 num1 0x1000 0000 num1 0020 and PCpreset = 0x0000 0008. Write program to initialize base 0x1000 0004 num1 address in x11 using PC+relative addressing using auipc and addi 0x1000 0008 num1 Step1: Calculate Relative address 0x1000 000C num1 Relative address = Base address – PCpresent 0x1000 0010 num1 Relative address = 0x1000 0020 – 0x0000 0008 =0x1000 0018 num2 0x1000 0014 num2 Step2: Divide Relative address in to two parts as Upper 20 bits and Lower 12 bits 0x1000 0018 num2 0x1000 0 018 0x1000 001C num2 Step3: Use following set of Instructions num3 0x1000 0020 num3 auipc x10, 0x10000 addi x10,0x018 0x1000 0020 Num3 x10 =PCpresent[31:12] + 0x10000 | PCpresent[11:0] =0x00000 +0x10000 | 0x008 = 0x10000 008 x10= x10+imm[11:0] = 0x10000008 +0x018 = 0x10000020 Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer RISC-V Addressing for wide immediate and addresses Use 2: auipc used for to calculate long target address of symbol beyond the range of jal num1 0x1000 0000 num1 Assume address of symbol is 0x07FFF F018 and PCpresent = 0x0000 0008. Write program change the control of execution to address of symbol. 0x1000 0004 num1 0x1000 0008 num1 Step1: Calculate Relative address 0x1000 000C num1 Relative address = Base address – PCpresent Relative address = 0x07FFF F018 – 0x0000 0008 =0x7FFF F010 0x1000 0010 num1 Step2: Divide Relative address in to two parts as Upper 20 bits and Lower 12 num2 0x1000 0014 num2 bits 0x1000 0018 num2 0x7FFF F | 0x010 Step3: Use following set of Instructions 0x1000 001C num2 auipc x10, 0x7FFFF num3 0x1000 0020 num3 jalr x1,x10,0x010 0x1000 0020 Num3 PCnew=PCpresent[31:12] + 0x7FFFF | PCpresent[11:0] = 0x00000 +0x7FFFF | 0x008 = 0x7FFFF 008 PCnew= x10+imm[11:0] = 0x7FFFF 008 + 0x010 = 0x07FFF F018 Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer Real Stuff: The rest of RISC V Instruction Set ▪ The next four instructions compare two integers, then write the Boolean result of the comparison to a register. slt and sltu compare two registers as signed and unsigned numbers, respectively, then write 1 to a register if the first value is less than the second value, or 0 otherwise. slti and sltiu perform the same comparisons, but with an immediate for the second operand. ▪ M Extension, adds instructions to multiply and divide integers. ▪ A Extension, supports atomic memory operations for multiprocessor synchronization. The load-reserved (LR.W) and store-conditional (SC.W) instructions ▪ F Extension and D Extension , provide operations on floating-point numbers Reference : Computer Organization and Design - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer Real Stuff: The rest of RISC V Instruction Set ▪ The last extension, C, provides no new functionality at all. ▪ Rather, it takes the most popular RISC-V instructions, like addi, and provides equivalent instructions that are only 16 bits in length, rather than 32. ▪ It thereby allows programs to be expressed in fewer bytes, which can reduce cost and, can improve performance. Reference : Computer Organization and Design - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy Parallelism and Instructions & Arithmetic for Computer Summary Reference : Computer Organization and Design - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy RISC V ARCHITECTURE The Processor Mahesh Awati Department of Electronics and Communication Engineering RISC V ARCHITECTURE 4.1: Page 254-258 4.2: Page 258-261 4.3 pages:261-268 4.4 pages:269-281 4.6 4.7 pages:296-312 4.8 pages:313-324 Mahesh Awati Department of Electronics and Communication Engineering The Processor Introduction An implementation that includes a subset of the core RISC-V instruction set: ▪ Memory reference instructions: load word (lw) and store word (sw) ▪ The arithmetic-logical instructions : add, sub, and, and or ▪ The conditional branch instruction: branch if equal (beq) Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation For every instruction, the first two steps are identical: 1. Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory. IF Machine Code I1-101010101 I2-000101010 Memory (Instructions) I3-111010101 P I3-111010101 Instruction C Addr Memory P Instruction Fetch 1 R O C E In IF stage S 1) Machine Code is Fetched from Memory location S pointed by PC. O R Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation For every instruction, the first two steps are identical: 2. Read one or two registers, using fields of the instruction to select the registers to read. ID Reg1 Instn Wd Fetched Ws Register Memory (Instructions) Decoder Rs1 File Time Slot Rs2 Reg2 P Instruction Fetch 1 R Immd O Instruction Decoding 2 C In ID stage E 1) Content of Two Source Registers is read (Reg1 & Subset S Reg2 )and given to Next stage ( ADD x5,x6,x7 or ▪ Load, & store, S beq x5,x6,label ▪ Arithmetic, O 2) If Load/Store Instruction – The base register ▪ Conditional R content is read as Reg1 and the 12-bit Immediate branch value as the offset Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation ▪ After these two steps, the actions required to complete the instruction depend on the instruction class. ▪ Fortunately, for each of the three instruction IE classes the actions are largely the same. Reg1 ALU Opr1 Result Memory (Instructions) Reg2 Opr2 Zero imm P Instruction Fetch 1 R In IE stage O Instruction Decoding 2 ✓ The memory-reference instructions (load C and store) use the ALU for an address E Execution 3 calculation, Subset S ✓ The arithmetic-logical instructions for the ▪ Load, & store, S operation execution, and ▪ Arithmetic, O ✓ Conditional branches for the equality test. ▪ Conditional R branch Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation After using the ALU, the actions required to complete various instruction classes differ. Subset Actions Store access the memory: write data for a store. Load access the memory: Read data for a load and load the data into destination register. An arithmetic- write the data out from the ALU into a register logical A conditional need to change the next instruction address based on the branch comparison instruction PCnew=PCpre+4 , Pcnew=PCpre+Signed offset Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation After using the ALU, the actions required to complete various instruction classes differ. ▪ A memory-reference instruction (Load / Store ) MEM will need to access the memory either to read data for a load or write data for a store. A L Addr DataOut U Memory (Instructions) o Data Time Slot u Memory t P Instruction Fetch 1 DataIn R Ws O Instruction Decoding 2 In MEM stage C 1) If LOAD – The ALUout is address of Data Memory E Execution 3 Location and the content is read and available at S output of MEM stage. S Memory Access 4 2) If STORE - The ALUout is address of Data Memory O Location and Content of source register is stored in R Memory location. Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register. WB ALUout Register Memory (Instructions) Addr File Time Slot DataOut Data read from Data Memory P Instruction Fetch 1 Memory R O Instruction Decoding 2 DataIn C Ws E Execution 3 In WB stage S 1) If it is R-type Instruction – Content of ALUout is S Memory Access 4 stored into destination register O 2) If Load Instruction – The Data read from the R Write Back 5 Memory location is stored into destination register Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation A conditional branch instruction, we may need to change the next instruction address based on the comparison; otherwise, the PC should be incremented by four to get the address of the subsequent instruction 04 For example, the value written into the PC can come from one of two adders. imm Machine Code PC=0x0001 0000 I1-101010101 I2-000101010 I3-111010101 P I3-111010101 Instruction PCnew C Addr Memory Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy  The Processor An Overview of the Implementation An abstract view of the implementation of the RISC-V subset Although this figure shows most of the flow of data through the processor, it omits two important aspects of instruction execution. 1. Data going to a particular unit as coming from two different sources. Can’t just 04 join wires together - Use multiplexers. imm ▪ PC = o/p one of two adders, Machine Code ▪ The data written into PC=0x0001 0000 the register file can Reg1 ALU come from either the I1-101010101 Wd Opr1 I2-000101010 DataOut ALU or the data I3-111010101 Ws Register Addr memory, P Rs1 File ▪ The second input to the Instruction Data PCnew C Addr Opr2 ALU can come from a Memory Rs2 Memory Reg2 DataIn register or the immediate field of the Immd instruction. Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy  The Processor An Overview of the Implementation The basic implementation of the RISC-V subset, including the necessary multiplexors ▪ The data written into the register file can come from either the ALU or the data PC = o/p one of two adders memory, ▪ The second input to the ALU can come from a 04 imm register or the immediate field of the Imm Generator instruction. Machine Code PC=0x0001 0000 Reg1 ALU I1-101010101 Wd Opr1 I2-000101010 DataOut I3-111010101 Ws Register Addr P Rs1 File Instruction Data PCnew C Addr Opr2 Memory Rs2 Reg2 Memory DataIn Immd Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy  2. The second omission in abstract view is that The Processor several of the units must be controlled An Overview of the Implementation depending on the type of instruction. PCSrc add x5,x6,x7 Branch=0 0 MUX3 PCpre+4 04 Zero Control Signals ▪ RegWrite. S ▪ MemRead L ▪ MemWrite. ▪ ALUOperation PCpre ALU Register File ▪ Branch. MUX Data Memory ▪ ALUSrc 2 Reg1 Wd Opr1 Machine Code Ws DataOut ▪ MemtoReg Register Addr MemtoReg P Rs1 File Reg2 C MUX1 PCnew Addr Opr2 Rs2 Instruction ALUOperation DataIn RegWrite Memory ALUSrc Imm Gen MemWrite MemRaed The basic implementation of the RISC-V subset, including the necessary CONTROL multiplexors and Control lines Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy  The Processor An Overview of the Implementation PCSrc lw x5,0x04(x10) Branch=0 0 MUX3 Pcold+4 04 04 Zero Control Signals ▪ RegWrite. S ▪ MemRead L ▪ MemWrite. ▪ ALUOperation ALU ▪ Branch. Register File MUX Data Memory Wd Reg1 Opr1 ▪ ALUSrc Machine Code Ws DataOut ▪ MemtoReg Register Addr MemtoReg P Rs1 File Reg2 C MUX1 PCnew Addr Opr2 Rs2 Instruction ALUOperation DataIn RegWrite Immd Memory ALUSrc Imm Gen MemWrite MemRead The basic implementation of the RISC-V subset, including the necessary CONTROL multiplexors and Control lines Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation PCSrc sw x5,0x04(x10) Branch=0 0 MUX3 Pcold+4 04 04 Zero=0 Control Signals ▪ RegWrite. S ▪ MemRead L ▪ MemWrite. ALU ▪ ALUOperation Register File ▪ Branch. MUX Data Memory Wd Reg1 Opr1 ▪ ALUSrc Machine Code Ws DataOut ▪ MemtoReg Register Addr MemtoReg P Rs1 File Reg2 C MUX1 PCnew Addr Opr2 Rs2 Instruction ALUOperation DataIn RegWrite Memory ALUSrc Imm Gen MemWrite MemRaed The basic implementation of the RISC-V subset, including the necessary CONTROL multiplexors and Control lines Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy The Processor An Overview of the Implementation PCSrc beq x5,x6,label Branch=1 0 MUX3 Pcold + offset

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