Unit 1: Binary Systems PDF

Class code uhaoqnc Unit 1: Binary Systems  Analog System Digital System Parameters Analog signal represents Digital signals are discrete and Signal physical measurements. generated by digita...

Class code uhaoqnc Unit 1: Binary Systems  Analog System Digital System Parameters Analog signal represents Digital signals are discrete and Signal physical measurements. generated by digital modulation. Waves Sine Waves Square Waves Representati Continuous range of values to Uses discrete values to represent on represent information information Samples analog waveforms into a Records waveforms as they Technology limited set of numbers and then are. records them. Data Affected by noise during Noise-immune during transmission transmission and write/read transmission and write/read cycle. s cycle. Response to More likely to get affected Less likely to get affected Noise Flexibility Hardware is not flexible. Hardware is flexible. More bandwidth to carry out Bandwidth Less bandwidth. the same information Stored data in the form Stored data in the form of Memory of wave signal binary bit Power Consumes large power Consumes neglible power Best suited for audio Best suited for Computing Uses and video transmission. and digital electronics. Cost Cost is low Cost is high  Clock Waveform In electronics and especially synchronous digital circuits, a clock signal is an electronic logic signal (voltage or current) which oscillates between a high and a low state at a constant frequency and is used like a metronome to synchronize actions of digital circuits. In a synchronous logic circuit, the most common type of digital circuit, the clock signal is applied to all storage devices, flip-flops and latches and causes them all to change state simultaneously, preventing race conditions. A clock signal is produced by an electronic oscillator called a clock generator. The most common clock signal is in the form of a square wave with a 50% duty cycle. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge or in the case of double data rate, both in the rising and in the falling edges of the clock cycle. Timing diagram - The End