Set_5_Verfication_using_SV(2).pptx

Design Verification Using System Verilog Dr. Hani Saleh  Outline  Introduction to Verification  Testbench Architecture  Blocking and Nonblocking assignments  Fork and Join...

Design Verification Using System Verilog Dr. Hani Saleh  Outline  Introduction to Verification  Testbench Architecture  Blocking and Nonblocking assignments  Fork and Join  Verification Constructs in SystemVerilog  Randomization  Constrained Random Verification  Practical Examples A Great Resource to learn about SV for Another Great Resource to learn about SV Verification: for Verification: https://www.chipverify.com/tutorials/ https://verificationguide.com/systemverilog/ systemverilog systemverilog-tutorial/ Design Verification Using System 2 Verilog  Importance of Verification Verification ensures the 1. Ensuring Correctness: the correctness of the design design behaves as intended. and helps avoid costly errors. 2. Cost Efficiency: avoid the high costs associated with reworking or It is a critical step in the recalling defective products. design process to ensure 3.Improving Quality: A thorough that the final product meets verification process ensures that the the specifications and functions as intended. design performs correctly under various conditions and scenarios. 4.Reducing Time-to-Market: By identifying and resolving issues early, verification accelerates the development process. 5.Compliance with Standards: Verification ensures that the design complies with industry standards and regulations. 6.Facilitating Debugging: making it easier to debug and troubleshoot issues. 3  Verification Types of Verification Verification Strategies 1. Simulation-Based Verification: 1.Directed Testing: Writing This method uses testbenches to specific test cases to check simulate the design and check its behavior. It is flexible and widely certain functionalities. It is adopted but can be time-consuming straightforward but may not and may not cover all scenarios. cover all possible scenarios. 2. Formal Verification: This method uses mathematical methods to prove 2.Constrained Random the correctness of the design. It is Verification: Generating random exhaustive and mathematically rigorous but can be complex and may test cases within specified not scale well for large designs. constraints to cover a wide range of scenarios. It improves 3. Emulation and Prototyping: This coverage but requires careful method uses hardware platforms to constraint definition. verify the design in real-time. It can handle large designs and provides real-time verification but is expensive 3.Coverage-Driven Verification: and requires specialized hardware. Using coverage metrics to guide the verification process and ensure all aspects of the design are tested. It provides a 4  Testbench 1.Purpose Generate different types of Testbench input stimulus Components Component Description 2. Drive the design inputs with the generated stimulus This is the part of the testbench that 3. Allow the design to process generates the input signals to drive the input and provide an output Design Under Test (DUT). 4. Check the output with expected Stimulus It can include various types of input behavior to find functional patterns, such as random data, specific test vectors, or sequences designed to defects test functionalities of the DUT. 5. If a functional bug is found, then change the design to fix the bug This is the actual hardware design or module that you are testing. 6. Perform the above steps until there are no more functional The DUT is instantiated within the Design Under Test testbench, and it receives the stimulus defects (DUT) signals as inputs. The DUT processes these inputs Testbench Architecture according to its design and produces output signals. Also known as the monitor or scoreboard, this component verifies that the outputs of the DUT are correct. It compares the actual outputs from the Output Checker DUT against the expected outputs and flags any discrepancies. This helps in identifying any errors or DUT: is the design under test and is bugs in the DUT. the hardware design described in SV. 5  Testbench Example Counter Module module up_down_counter ( // Clock generation input logic clk, initial begin //non synthesizable input logic reset, input logic up_down, // 1 for up, 0 for down clk = 0; output logic [2:0] count forever #5 clk = ~clk; // 10ns period clock ); end always_ff @(posedge clk or posedge reset) begin if (reset) count 1; // Ensure my_rand_var is greater than 1 my_rand_var < 6; // Ensure my_rand_var is less than 6 1. Basic Constraints: Use the my_randc_var inside {0, 1, 2, 4, 5, 6, 7}; // Ensure my_randc_var constraint keyword to define is not equal to 3} constraints within a class. endclass 2. In-line Constraints: Specify constraints directly within the module rand_randc_const; randomize() call. initial begin automatic MyClass obj = new(); // Declare obj as automatic 3. Soft Constraints: Use the soft keyword to define constraints that can be overridden by other // Randomize and display values for a few iterations constraints. repeat (10) begin if (obj.randomize() with {obj.my_inline_var inside 4. Pre/Post Randomize Functions: {1,2,3};}) begin Use pre_randomize and if (obj.my_rand_var inside {2, 3, 4, 5} && post_randomize functions to execute code before and after obj.my_randc_var inside {0, 1, 2, 4, 5, 6, 7}) begin randomization. $display("rand: %0d, randc: %0d, inline: %d", obj.my_rand_var, obj.my_randc_var,obj.my_inline_var); # rand: 3, randc: 5, inline: 3 5. Distribution Constraints: Use the end else begin # rand: 5, randc: 2, inline: 1 dist keyword to specify the $display("Constraint violation: rand# = rand: %0d,3, randc: 4, inline: 2 probability distribution of random values. randc = %0d, inline = %0d", obj.my_rand_var, # rand: 4, randc: 0, inline: 2 obj.my_randc_var,obj.my_inline_var); # rand: 4, randc: 1, inline: 1 6. Implication Constraints: Use the - end # rand: 3, randc: 7, inline: 3 > operator to define conditional # rand: 3, randc: 6, inline: 1 end else begin constraints. $display("Randomization failed"); # rand: 2, randc: 6, inline: 2 end # rand: 3, randc: 5, inline: 3 end # rand: 3, randc: 2, inline: 3  Important Built-in Classes Classes in System Verilog SystemVerilog includes several built-in classes that are particularly useful:  In SystemVerilog (SV), classes are a fundamental part of the language, especially 1. Mailbox: Used for async. communication between processes. useful for testbench automation and OOP. mailbox mbox = new(); - Class Declaration: a user-defined data type 2. Semaphore: Used for controlling access to shared that includes data (properties) and resources. functions/tasks (methods) to operate on that semaphore sem = new(1); // Initialize with 1 permit data. 3. Queue: A dynamic array that can grow and shrink. class MyClass; class QueueExample; int x; // Property int queue[$]; endclass function void set(int i); x = i; 4. Randomize: built-in methods for randomization. endfunction class RandomExample; rand int x; function void do_randomize(); function int get(); if (!randomize()) $display("Randomization failed"); return x; endfunction endfunction endclass endclass Key Features of SystemVerilog Classes - Object Creation: To use a class, you need to - Encapsulation: Bundling data and methods that operate on create an instance (object) of it. the data within one unit. - Inheritance: Creating new classes based on existing ones. MyClass obj = new(); - Polymorphism: Methods can be overridden in derived obj.set(10); classes. $display("Value of x: %0d", obj.get()); - Data Hiding: Restricting access to certain details of an object. 41  Built-in Methods in System Verilog 1. $display, $write, $strobe 3. $time, $realtime These functions are used for displaying These functions return the current messages during simulation. simulation time. - $display: Prints a message and - $time: Returns the current moves to a new line. $display("Hello, World!"); simulation time as an integer. $display("Current time: %0t", $time); - $write: Prints a message without moving to a new line. - $realtime: Returns the current $write("Hello, "); simulation time as a real number. $write("World!"); $display("Current real time: %0f", $realtime); - $strobe: Prints a message at the end of the current simulation time step. $strobe("End of time step"); 4. $random, $urandom Used for generating random numbers. 2. $monitor - $random: Generates a signed Continuously monitors and prints the random number. values of variables whenever they int rand_num; change. rand_num = $random; $monitor("Time: %0t, a: %0d, b: %0d", $time, a, b); - $urandom: Generates an unsigned random number. int urand_num; 42 urand_num = $urandom;  Explanation: Built-in Methods in System Verilog INHERITANCE Class Definitions: You 5. $finish, $stop 8. $cast have a base class Base and a derived These functions control the simulation. Used for type casting. class Derived that class Base; extends Base. - $finish: Ends the simulation & quit endclass Object Creation: You the simulator. create an object b of $finish; class Derived extends Base; type Base and declare a endclass variable d of type Derived. - $stop: Pauses the simulation & keep Type Casting: session open. Derived d; The $cast function $stop; Base b = new(); attempts to cast b to type Derived and assigns it to d. If the cast is 6. $fatal if ($cast(d, b)) begin successful, it prints “Cast Terminates the simulation and provides $display("Cast successful"); successful”. an exit code. end $fatal(1, "Fatal error occurred"); 7. $urandom_range 9. $clog2 Generates a random number within a Calculates the ceiling of the logarithm base specified range. 2 of a number, useful for determining the number of bits required to represent a // Generates a number between 1 and value. 100 int rand_num; int num_bits; rand_num = $urandom_range(1, 100); num_bits = $clog2(16); // Returns 4, as 2^4 = 16 43  Built-in Methods in System Verilog 10. $bits 12. $isunknown Checks if a value contains any unknown (X or Z) bits. Returns the number of bits required to represent a variable or type. logic [3:0] val = 4'b1X01; if ($isunknown(val)) begin $display("Value contains unknown bits"); int a; end $display("Number of bits in a: %0d", $bits(a)); // Typically returns 32 for an 13. $onehot, $onehot0 int Checks if a value is one-hot encoded (only one bit set to 1). 11. $countones - $onehot: Checks for exactly one bit set to 1. Counts the number of 1s in a binary representation of a number. logic [3:0] val = 4'b0100; if ($onehot(val)) $display("Value is one-hot"); int num = 13; // Binary: 1101 - $onehot0: Checks for all zeros or one bit set to 1. int ones_count; ones_count = $countones(num); // logic [3:0] val = 4'b0000; if ($onehot0(val)) $display("Value is one-hot or zero"); Returns 3 $onehot0(vector) returns 1 (true) if the vector has $onehot(vector) returns 1 (true) if exactly one bit is set either no bits set to 1 or exactly one bit set to 1. to 1 and all other bits are 0. bit [3:0] vector; bit [3:0] vector; initial begin initial begin vector = 4'b0000; // $onehot0 returns 1 (true) vector = 4'b0001; // $onehot returns 1 (true) vector = 4'b0010; // $onehot0 returns 1 (true) vector = 4'b0000; // $onehot returns 0 (false) vector = 4'b0110; // $onehot0 returns 0 (false) vector = 4'b0101; // $onehot returns 0 (false) end end 44  Built-in Methods in System Verilog 14. $rose, $fell, $stable These functions are used for edge detection in signals. - $rose: Detects a rising edge. always @(posedge clk) begin if ($rose(signal)) $display("Rising edge detected"); end //checks if the signal has transitioned from 0 to 1 since the last time the always block was executed. - $fell: Detects a falling edge. always @(posedge clk) begin if ($fell(signal)) $display("Falling edge detected"); end //checks if the signal has transitioned from 1 to 0 since the last time the always block was executed. - $stable: Checks if a signal has remained stable. always @(posedge clk) begin if ($stable(signal)) $display("Signal is stable"); end // checks if the signal has not changed since the last time the always block was executed. 45 Dr. Hani Saleh  Vivado Installation 1. DownloadInstructions the folder 8. Start the installation by clicking “XILINX_Vivado_DS” from the following “Install” link: https://kudrive.ku.ac.ae/oc-shib/ 9. During the installation, the software index.php/s/EWo9dc7OJuUsIL6 might ask for your permission to install drivers. please click Yes whenever 2. Extract the downloaded folder, then it does run “xsetup.exe” 10. The Xilinx License Manager will open 3. You will get a pop-up window titled "A once the installation process is Newer Version is Available", click complete. If it doesn’t open, start Vivado "Continue", then click “Next” and click on “Help” ➔ “Manage License” 4. Accept the license agreements and click “Next” 11. Before proceeding further with the license manager, copy the license file 5. Select "Vivado Design Edition" and click “Xilinx.lic” from the downloaded folder “Next” and place it in “C:\Xilinx” folder 6. In the next window, click "reset to 12. Go back to the license manager and defaults" at the bottom right, then click “Manage License Search Paths” click “Next” 13. Type the following in both empty 47 7. Keep the installation directory as "C:\ fields:  A full Example Using NEXYS A7 Board will be given after we cover FPGA’s 48