Embedded System Architecture and Design Lectures PDF

Embedded System Architecture and Design (ICAT3050) Lectures UNIVERSITY of VAASA Tobias Glocker 1  Links to the Lectures ▪ Lecture 1 ▪ Lecture 2 ▪ Lecture 3 ▪ Lecture 4 ▪ Lecture 5 ▪ Lecture 6 ▪ L...

Embedded System Architecture and Design (ICAT3050) Lectures UNIVERSITY of VAASA Tobias Glocker 1  Links to the Lectures ▪ Lecture 1 ▪ Lecture 2 ▪ Lecture 3 ▪ Lecture 4 ▪ Lecture 5 ▪ Lecture 6 ▪ Lecture 7 ▪ Lecture 8 ▪ Lecture 9 ▪ Lecture 10 UNIVERSITY of VAASA Tobias Glocker 2  Embedded System Architecture and Design (ICAT3050) Lecture 1 Links to the Lectures Lecture 2 UNIVERSITY of VAASA Tobias Glocker 3  Table of Contents ▪ Course Information ▪ Learning Outcomes ▪ Motivation ▪ Contents of the Course ▪ Assembly Language Programming ▪ Numbering and Coding Systems ▪ Voltage, Current and Resistance ▪ Transistor ▪ Binary Logic ▪ Logic Gates ▪ Half-Adder and Full-Adder ▪ Bit-Masks ▪ Shift Operations ▪ References UNIVERSITY of VAASA Tobias Glocker 4  Course Information ▪ Lectures and Exercises: Tobias Glocker ▪ Office hour: By Appointment UNIVERSITY of VAASA Tobias Glocker 5  Course Information Credits: 5 ECTS ▪ 24h Lectures ▪ 24h Exercises Course Materials are available in MOODLE Course Key (ICAT3050) ▪ Requirements of the course ▪ Lecture Slides and Exercises UNIVERSITY of VAASA Tobias Glocker 6  Course Information Lectures and Exercises - The participation in the lectures and exercises are not mandatory but strongly recommended. Grading of the Course - The usual scale from 1-5 or failed. Exam + Homework (pass/fail)! - If a student fails in the homework, his/her exam grade will be lowered by one grade, under the condition that the exam grade is not one! Exam - The exam is closed book. No additional material can be used! % Grade - Exam Time: 2 hours ≥ 90 5 - Max. Points: 30 80 ≤ x < 90 4 70 ≤ x < 80 3 Important Notes 60 ≤ x < 70 2 - No solutions for the exercises are published! 50 ≤ x < 60 1 - No envelope exam will be provided! x < 50 0 x = (100/30) * exam_points UNIVERSITY of VAASA Tobias Glocker 7  Course Information Literature ▪ Lecture Notes ▪ Course Book Mazidi, Muhammad Ali & Janice Gillispie Mazidi & Rolin D. McKinlay (2013). The 8051 Microcontroller. A Systems Approach. PEARSON. ISBN-13: 978-0-13-304217-7. ▪ Vahid, Frank & Tony Givargis (1999). Embedded System Design: A Unified Hardware/Software Approach. University of California. UNIVERSITY of VAASA Tobias Glocker 8  Learning Outcomes After the course the student should be able to: - Select the right microcontroller/microprocessor in terms of the defined requirements! * Architecture (RISC) * Peripherals * Speed * Power Consumption * System Integration - Program a microcontroller with Assembly Language! - Understanding the concepts of: * Direct / Indirect Addressing * Program Counter, Stack Pointer etc. * Interrupts (IVT and ISR) UNIVERSITY of VAASA Tobias Glocker 9  Learning Outcomes ▪ Criteria for choosing a microcontroller 1) Efficiency and cost effectively speed, packaging (DIP, QFP), power consumption, amount of RAM, ROM, number of I/O Pins, timer (on chip), costs per unit. 2) Usability. (Availability of an assembler, a debugger, a code-efficient C compiler, an emulator, technical support etc.) 3) Availability in needed quantities now and in the future UNIVERSITY of VAASA Tobias Glocker 10  Motivation Application Examples of Microcontrollers [http://www.robotshop.com/inex- microcamp-robot-kit-5.html] [http://www.pro-4- [http://www.electronics- pro.com/en/Foodindustry/Arch lab.com/blog/?tag=sensor&paged=3] ive/Reference_Design_Low- Cost_Implementation_of_TFT_ Displays_in_Microcontroller_A pplications.html] [http://www.scaleochip.com/products.php] UNIVERSITY of VAASA Tobias Glocker 11  Contents of the Course - Numbering and Coding Systems - Logic Gates - Buses - Memory Organization - Memory Types - Interrupts - Pipelines - RISC Architecture - Assembly Language Programming (in the second part of the course) - Cache - Minimized Output Equations, Multiplexer, Interfacing, Direct Memory Access and System Integration UNIVERSITY of VAASA Tobias Glocker 12  Assembly Language Programming UNIVERSITY of VAASA Tobias Glocker 13  Assembly Language Programming ▪ EDSIM51 (can be downloaded for free) IDE (Integrated Development Environment) Download Link:  https://www.edsim51.com/installationInstructions.html UNIVERSITY of VAASA Tobias Glocker 14  Numbering and Coding Systems ▪ Converting from Decimal to Binary Convert 2510 to binary Quotient Remainder 25/2 = 12 1 (LSB) Least Significant Bit 12/2 = 6 0 06/2 = 3 0 03/2 = 1 1 01/2 = 0 1 (MSB) Most Significant Bit Result :110012 UNIVERSITY of VAASA Tobias Glocker 15  Numbering and Coding Systems ▪ Converting from Binary to Decimal Convert 110012 to decimal Weight: 16 8 4 2 1 Digits: 1 1 0 0 1 Sum: 16 + 8+ 0+ 0+ 1 = 2510 UNIVERSITY of VAASA Tobias Glocker 16  Numbering and Coding Systems Hex Decimal Binary Hex Decimal Binary Hex Table 0 0000 0 16 10000 10 1 0001 1 17 10001 11 2 0010 2 18 10010 12 3 0011 3 19 10011 13 4 0100 4 20 10100 14 5 0101 5 21 10101 15 6 0110 6 22 10110 16 7 0111 7 23 10111 17 8 1000 8 24 11000 18 9 1001 9 25 11001 19 10 1010 A 26 11010 1A 11 1011 B 27 11011 1B 12 1100 C 28 11100 1C 13 1101 D 29 11101 1D 14 1110 E 30 11110 1E 15 1111 F 31 11111 1F UNIVERSITY of VAASA Tobias Glocker 17  Numbering and Coding Systems ▪ Converting between Binary and Hex Convert 1001111101012 to hex. Bin 1001 1111 0101 Hex 9 F 5 ▪ Converting between Hex and Binary Convert hex 29B to binary 29B = 2 9 B Binary 0010 1001 1011 UNIVERSITY of VAASA Tobias Glocker 18  Numbering and Coding Systems ▪ Converting from Hex to Decimal Convert 4510 to hex. First convert the decimal number to binary Weight: 32 16 8 4 2 1 Binary Num: 1 0 1 1 0 1 Binary Num (8 bits): 0010 1101 Hex: 2 D UNIVERSITY of VAASA Tobias Glocker 19  Numbering and Coding Systems ▪ 2’s complement Convert the decimal number -4 to a binary number Convert first +410 to binary 410 = 01002 Invert binary number 0100 10112 Add 1 to the inverted binary number 10112 + 1 = 1100 UNIVERSITY of VAASA Tobias Glocker 20  Voltage, Current and Resistance ▪ Voltage ”Voltage is a representation of the electric potential energy per unit charge. If a unit of electrical charge were placed in a location, the voltage indicates the potential energy of it at that point. In other words, it is a measurement of the energy contained within an electric field, or an electric circuit, at a given point.” The unit of the voltage is volt (V). [http://physics.about.com/od/glossary/g/voltage.htm] ▪ Current ”Electrical current is a measure of the amount of electrical charge transferred per unit time. It represents the flow of electrons through a conductive material.” The unit of the current is ampere (A). [http://physics.about.com/od/glossary/g/Current.htm] ▪ Resistance Ohm’s Law: R=V/I The unit of the resistance is ohm (Ω). UNIVERSITY of VAASA Tobias Glocker 21  Voltage, Current and Resistance ▪ Example 5V I R=? VR VT VL GND Compute R for VL = 1.5V and I = 20mA UNIVERSITY of VAASA Tobias Glocker 22  Voltage, Current and Resistance ▪ Resistors in Series ▪ Resistors in Parallel 5V 5V I I I1 I2 R1 VR1 R1 R2 V VT VR2 R2 (1/Rtotal) = (1/R1) + (1/R2) GND RTotal = R1 + R2 UNIVERSITY of VAASA Tobias Glocker 23  Transistor ▪ CMOS and NPN Bipolar Transistor +5V +5V R R D IC G VCB IB VCE S VBE Main difference: MOSFET operates based on the input voltage BJT operates based on the input current. UNIVERSITY of VAASA Tobias Glocker 24  Binary Logic Voltage Computers use the binary number system 5 because the two voltage levels can be Logic 1 4 presented as the two digits 0 and 1. 3 2 1 Logic 0 0 ▪ Some Important Terminology Bit 0 Nibble 0000 Byte 0000 0000 Word 0000 0000 0000 0000 UNIVERSITY of VAASA Tobias Glocker 25  Logic Gates AND x y q x & 0 0 0 y q 0 1 0 1 0 0 1 1 1 OR x y q x ≥1 0 0 0 y q 0 1 1 1 0 1 1 1 1 NOT x q x 1 q 0 1 1 0 UNIVERSITY of VAASA Tobias Glocker 26  Logic Gates NAND x y q x & 0 0 1 y q 0 1 1 1 0 1 1 1 0 NOR x y q x ≥1 0 0 1 y q 0 1 0 1 0 0 1 1 0 UNIVERSITY of VAASA Tobias Glocker 27  Logic Gates XOR x y q x =1 0 0 0 y q 0 1 1 1 0 1 1 1 0 XNOR x y q x =1 0 0 1 y q 0 1 0 1 0 0 1 1 1 UNIVERSITY of VAASA Tobias Glocker 28  Half-Adder and Full-Adder Half-Adder x y sum C out x =1 y sum 0 0 0 0 0 1 1 0 & 1 0 1 0 C out 1 1 0 1 UNIVERSITY of VAASA Tobias Glocker 29  Half-Adder and Full-Adder Full-Adder x =1 =1 y sum & & ≥1 C out C in x y C in C sum out 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 UNIVERSITY of VAASA Tobias Glocker 30  Half-Adder and Full-Adder Full-Adder y2 x2 C in y1 x1 C in y0 x0 C in Full Adder Full Adder Full Adder C out sum2 C out sum1 C out sum0 UNIVERSITY of VAASA Tobias Glocker 31  Bit Masks Masking Operations Check bit, use and & if(REG & 0x10)  Checks the fifth last bit (“0001 0000”) Set bit, use or | REG = REG | 0x3;  The last two bits are set to 1, the others remain the same Clear bit, use and & REG = REG & 0xFE;  The last bit is set to 0, others remain the same Complement all bits REG =~REG; Change bit, use xor (^) REG = REG ^ 0xFF; All bits are inverted, e.g. from 10101010 to 01010101 REG = REG ^ 0x80; The first bit is inverted REG = REG ^ 0x1; The last bit is inverted UNIVERSITY of VAASA Tobias Glocker 32  Shift Operations Left Shift 0 0 0 0 0 0 0 1 (0x01) 0 0 0 0 1 0 0 0 (0x01 > 1) value > n n: number of places to shift UNIVERSITY of VAASA Tobias Glocker 33  References ▪ Mazidi, Muhammad Ali & Janice Gillispie Mazidi & Rolin D. McKinlay (2013). The 8051 Microcontroller. A Systems Approach. PEARSON. ISBN-13: 978-0-13-304217-7. UNIVERSITY of VAASA Tobias Glocker 34  Embedded System Architecture and Design (ICAT3050) Lecture 2 Lecture 1 Links to the Lectures Lecture 3 UNIVERSITY of VAASA Tobias Glocker 35  Table of Contents ▪ Microprocessor versus Microcontroller ▪ Buses ▪ Memory Organization ▪ Memory ▪ Memory Components ▪ Main Memory ▪ References UNIVERSITY of VAASA Tobias Glocker 36  Microprocessor versus Microcontroller ▪ Microprocessor Address bus CPU RAM ROM Disk Monitor Key- board Data bus Control bus ▪ Microcontroller CPU RAM ROM I/O Timer Serial ADC COM Port UNIVERSITY of VAASA Tobias Glocker 37  Buses CPU Memory I/O 0 Address Address … Data Data /CS /WE /OE /WR /RD Addr. Dec. Data bus Address bus Control /IOR bus /IOW /MEMR /MEMW UNIVERSITY of VAASA Tobias Glocker 38  Buses ▪ Data Bus Data bus is used to carry information in and out of a CPU. It is bidirectional, because the CPU must use them for receiving or sending data. The average size of data buses varies between 8 and 64 Bits. ▪ Address Bus The address bus is used to identify the devices and memory connected to the CPU. The more address buses, the larger the number of devices that can be addressed. A CPU with 16 address lines can provide a total of 65536 (2^16) or 64K of addressable memory. ▪ Control Bus The control bus is used to indicate if the CPU wants to write or read to/from the memory. UNIVERSITY of VAASA Tobias Glocker 39  Memory Organization AmplifiersD i Memory Cells Do X0 X1 X2 X3 Y0 Read & /CS Write /OE Logic /WE Row Decoder A1 A0 Y1 Ax = Address Signals Di = Data Input Do = Data Output Y2 CS = Chip Select OE = Output Enable WE = Write Enable Y3 Column Decoder UNIVERSITY of VAASA A2 A3Tobias Glocker 40  Memory ▪ ROM (Read-Only Memory) Does not loose its contents when power is turned off (non- volatile)! ▪ PROM (Programmable Read-Only Memory) ROM, the user can burn information into it! For every bit, there exists one fuse! Programmed by blowing fuses! If the burned information is wrong, PROM must be thrown away, since it is only OTP (One Time Programmable) UNIVERSITY of VAASA Tobias Glocker 41  Memory ▪ EPROM (Erasable Programmable Read-Only Memory) Invented to allow making changes in the contents of PROM after it is burned! EPROM can be erased and programmed thousands of times! The wideliest EPROM is the so called UV-EPROM! Erasing time ~20 min! [http://www.batronix.com/shop/chips/eproms.html] UNIVERSITY of VAASA Tobias Glocker 42  Memory ▪ EEPROM (Electrically EPROM) In contrast to the EPROM where the whole ROM is erased, a certain byte can be selected that should be erased. EEPROM does not require an external erasure and programming device. Its contents can be programmed and erased while it is still on the system board. It can be used for saving calibration values! It is byte-wise erasable! UNIVERSITY of VAASA Tobias Glocker 43  Memory ▪ Flash Memory 1990 Flash Memory became popular! Reason: Erasure time takes less than one second! Erasure method is electrical! It is block-wise erasable! Widely used to upgrade BIOS ROM of the PC! UNIVERSITY of VAASA Tobias Glocker 44  Memory ▪ RAM (Random Access Memory) There are three types of RAM:  Static RAM (SRAM) (volatile)!  Dynamic RAM (DRAM) (volatile)!  NV-RAM (nonvolatile RAM)!  Volatile means, that the stored information is lost, when cutting off the power! UNIVERSITY of VAASA Tobias Glocker 45  Memory ▪ SRAM (Static RAM) Storage cells in static memory are made with flip-flops and thus do not require refreshing in order to keep their data. Drawback: Each cell needs at least six transistors. Newer ones at least four. SRAM CELL DI/O ’0’ is stored VCC T1 on, T2 off 1 ’1’ is stored T1 off, T2 on T3 T4 T5 T6 T1 T2 Yn Xn UNIVERSITY of VAASA Tobias Glocker 46  Memory /CS /OE /WE Function ▪ SRAM 1 X X Component not selected A0-Ax /CS SRAM DIO 0 1 1 DIO has a high impedance /OE /WE 0 0 1 Read data 0 X 0 Write data SRAM READING CYCLE SRAM WRITING CYCLE A0-Ax Address valid A0-Ax /CS /CS DiO VALID /WE /OE /WE DIO VALID Data Data set up hold access time Data will be read from the Memory Data will be written to the Memory UNIVERSITY of VAASA Tobias Glocker 47  Memory ▪ DRAM (Dynamic RAM) Capacitors are used to store information! DRAM has a smaller cell size in comparison to the SRAM! Major advantages are high density (capacity), cheaper costs per bit and lower power consumption per bit! DRAMS cells must be refreshed to regular time intervalls. During the refreshing time the data can not be accessed. UNIVERSITY of VAASA Tobias Glocker 48  Memory ▪ DRAM DRAM CELL Cs Ts Yn DI DO Xn Stored Bit Value State of the Capacitor 0 uncharged 1 charged UNIVERSITY of VAASA Tobias Glocker 49  Memory ▪ DRAM Problem: DRAM refresh required because the energy of the capacitor gets lost. Solution: Refreshing the rows of the DRAM Content of each cell will be loaded to a ”row register” and from there each bit will be written back to the cells. Row Register X0 X1 X2 Xn DRAM DRAM DRAM DRAM … Cell 1 Cell 2 Cell 3 Cell N Yn UNIVERSITY of VAASA Tobias Glocker 50  Memory Row 1023 ▪ DRAM refresh … Row 0 Row 0 refresh refresh When one row refresh takes 15,6 us of time then the total refreshing time takes arround 16ms. UNIVERSITY of VAASA Tobias Glocker 51  Memory ▪ DRAM DRAM READING CYCLE DRAM WRITING CYCLE A0-Ax ROW COLUMN A0-Ax ROW COLUMN /RAS /RAS /CAS /CAS /WE /WE Dout VALID Din VALID /RAS == 0 -> Address will be taken to the Row Address Register /CAS == 0 -> Address will be taken to the Column Address Register DRAM REFRESH CYCLE A0-Ax ROW /RAS UNIVERSITY of VAASA Tobias Glocker 52  Memory ▪ NV-RAM (nonvolatile RAM) Whereas SRAM is volatile, there is a new type of nonvolatile RAM! It combines the best of RAM and ROM: read and write ability of RAM plus the nonvolatility of ROM! It uses extremly power-efficient SRAM cells built out of CMOS! Uses internal lithium battery as backup energy source! UNIVERSITY of VAASA Tobias Glocker 53  Memory ▪ Memory Overview Non-Volatile Memory Volatile Memory ROM NV-RAM FLASH Mem. RAM PROM EPROM EEPROM SRAM DRAM UNIVERSITY of VAASA Tobias Glocker 54  Memory ▪ CPU and its relation to RAM and ROM Data must be stored in RAM or ROM. ROM: fixed and permanent information! RAM: temporary information that can change with time! ▪ PC RAM contains program and data! Accessing the information directly from the hard drive is slow! ▪ Embedded System ROM/Flash Memory: Program! RAM: modifiable data! UNIVERSITY of VAASA Tobias Glocker 55  Memory Components CPU Register Flip-Flop Cache SRAM Cache SRAM Main Memory SRAM or DRAM ROM Memory Flash-EPROM I/0 Memory Mass Storage UNIVERSITY of VAASA Tobias Glocker 56  Main Memory Mem. Mem. Comp. 1... Comp. N Control Signal (CS, WE, RAS, …) RAM DIR Controller Address bus EN CPU Data bus Control bus ▪ Amount of memory components depends on: Desired memory capacity! CPU data bus! ▪ RAM Controller: Converts the signals delivered from the CPU in RAM control signals! UNIVERSITY of VAASA Tobias Glocker 57  Main Memory ▪ Examples of Memory Components 1Mx8 512Kx8 512Kx4 … 220 - 1 219 - 1 219 - 1 … … 10101010 0 10101010 0 1010 0 1M → Addresses 512K → Addresses 512K → Addresses x8 → Each address has 8 bits! x8 → Each address has 8 bits! x4 → Each address has 4 bits! Memory Size: 1MB Memory Size: 512KB Memory Size: 256KB UNIVERSITY of VAASA Tobias Glocker 58  Main Memory (SRAM) ▪ A system has 4MB (4 x 1Mx8) SRAM memory, a 32 bit data bus and a 32 bit address bus. Draw the system and describe in detail how each component is connected. 1Mx8 1Mx8 1Mx8 1Mx8 CS0 CS1 CS2 CS3 A2-A21 A2-A21 A2-A21 A2-A21 D0-D7 D8-D15 D16-D23 D24-D31 RAM DIR Controller EN Address bus A2-A21 D0-D31 A0-A1 CPU Data bus Control bus UNIVERSITY of VAASA Tobias Glocker 59  Main Memory (SRAM) 1Mx8 1Mx8 1Mx8 1Mx8 ▪ Memory Bank Bank 2 More memory chips can be CS4 CS5 CS6 CS7 used A2-A21 A2-A21 A2-A21 A2-A21 D0-D7 D8-D15 D16-D23 D24-D31 1Mx8 1Mx8 1Mx8 1Mx8 Bank 1 Byte Transfer: - Only one byte can be transmitted CS0 CS1 CS2 CS3 at a time! A2-A21 A2-A21 A2-A21 A2-A21 D0-D7 D8-D15 D16-D23 D24-D31 RAM DIR Controller EN Address bus A2-A21 D0-D31 A0, A1, A22 CPU Data bus Control bus UNIVERSITY of VAASA Tobias Glocker 60  Main Memory (DRAM) ▪ DRAM Memory Controller DRAM DRAM 1 CPU CONTROLLER DRAM 2.. ▪ Tasks of a DRAM Controller: DRAM N Refresh DRAM cells! Chip selection! Signal convertion (CPU to DRAM) and time handling! Address multiplexing! UNIVERSITY of VAASA Tobias Glocker 61  Main Memory (DRAM) ▪ An example of a 386 SX- System /RASH 1Mx1 /RASH 1Mx1 /CASH DRAM /CASH DRAM /WE /WE MUX2 ID0-ID7 ID8-ID15 /CASH /RASH /WE MUX1 ENL ENH DIR Refresh Control Logic Configuration Counter Register W/R, D/C, M/IO /Reset, CLK /BLE, /BHE D0-D7 D8-D15 D0-D7 A21-A23 /READY /ADS A11-A20 D0-D15 A1-A10 UNIVERSITY of VAASA Tobias Glocker 62  Main Memory (DRAM) ▪ Control Logic Controls and monitors the refresh cycles! Time handling! ▪ Data Bus Driver Connects/disconnects the CPU to/from the Data bus! Is activated from the control logic! The direction will be set from the control logic! ▪ Refresh Counter Whenever a refresh needs to be done it generates the row address! Count impulses will be generated from the control logic! UNIVERSITY of VAASA Tobias Glocker 63  Main Memory (DRAM) ▪ Address-Multiplexer MUX1 Delivers row address! Forwards the ”refresh row address” or the received row address bits from the CPU to DRAM’s! ▪ Address-Multiplexer MUX2 Fowards row or column address! UNIVERSITY of VAASA Tobias Glocker 64  Main Memory (DRAM) ▪ Memory Optimization Memory Bank 1 CPU Bank 2 Problem without Bank interleaving DRAM Cycle Time Cycle Time Cycle Time Access Access Access CPU Busy Wait Busy Wait Busy Wait CPU needs to wait! Why? UNIVERSITY of VAASA Tobias Glocker 65  Main Memory (DRAM) ▪ Bank Interleaving Microprocessor with 32 Bit Instructions Address Instr. Code Bank 0000 0000 AB 54 76 32 Bank1 0000 0004 A3 94 FE 01 Bank2 0000 0008 75 FE 18 43 Bank1 0000 000C 66 F1 1F 98 Bank2 0000 0010 FB FC 01 02 Bank1 Changing the Bank: Address differentiate according to the A2 bit! A2 = 0 Bank 1 0x…0 = 0b0000 0x…8 = 0x1000 A2 = 1 Bank 2 0x…4 = 0b0100 0x…C = 0x1100 UNIVERSITY of VAASA Tobias Glocker 66  References ▪ Mazidi, M., J. Mazidi & R. McKinlay (2013). The 8051 Microcontroller. A System Approach. PEARSON. ISBN-13: 978-0-13-304217-7. ▪ Mazidi, M., Sa. Naimi & Se. Naimi (2011). The avr microcontroller and embedded system. Using assembly and c. PEARSON. ISBN-13: 978-0-13-800331-9. ▪ Strahnen, Manfred (2004). Computertechik III. Vorlesungsskript. Hochschule Ulm. UNIVERSITY of VAASA Tobias Glocker 67  Embedded System Architecture and Design (ICAT3050) Lecture 3 Lecture 2 Links to the Lectures Lecture 4 UNIVERSITY of VAASA Tobias Glocker 68  Table of Contents ▪ Polling ▪ Interrupts ▪ References UNIVERSITY of VAASA Tobias Glocker 69  Polling ▪ Reading Data from Sensors Micro- controller Consider a sensor with three registers! Temperature CR DR SR Sensor CR: Control register (different operation modes) DR: Data register (contains the measured value) SR: Status register (shows if new data are in the DR) Operation Modes: Polling or Interrupt UNIVERSITY of VAASA Tobias Glocker 70  Polling Evaluation of the efficiency! ▪ Flowchart for Polling Assume a sensor delivers 20 Start measurements per minute which are read by a microcontroller. read SR The time for reading the sensor takes 125 ms. no SR=1? Calculate the busy time for the CPU per minute. yes read DR TCPU_BUSY = 20 accesses/min * 125 ms/access TCPU_BUSY = 2.5 s/min reset SR In the remaining time the processor is busy with checking the Status Register Operation Mode: Polling CPU is only 2.5s/60s * 100% = 4.2% efficiently used. UNIVERSITY of VAASA Tobias Glocker 71  Interrupts ▪ Solution Micro- Add interrupt wire between the microcontroller controller INTR0 and the temperature sensor. When temperature dectection value is high Temperature then the sensor will send an interrupt request Sensor (INTR) to the microcontroller to sinal that it should read the data from the data register of the sensor. INTR Voltage Time UNIVERSITY of VAASA Tobias Glocker 72  Interrupts ▪ Interrupt Classification Hardware Interrupt: There are maskable and non-maskable interrupts. Maskable interrupts can be disabled while non-maskable interrupts can not be disabled. Software Interrupt: A software interrupt is “caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed.” [http://en.wikipedia.org/wiki/Interrupt] Example: Interrupt (process_ID, interrupt_number) Handle (interrupt_number, handler) Process_1 Process_2 UNIVERSITY of VAASA Tobias Glocker 73  Interrupts ▪ Triggering Methods Level-triggered - Interrupt is signaled by maintaining the interrupt line at a high or low level. The active level (high or low) is hold until the interrupt request is serviced. Edge-triggered - A falling or a rising edge on the interrupt signals an interrupt request. Hybrid - A combination of level-triggered and edge-triggered signalling. Not only the rising or falling edge is checked but it is also checked if the signal is active for a certain time. [http://en.wikipedia.org/wiki/Interrupt] UNIVERSITY of VAASA Tobias Glocker 74  Interrupts ▪ Interrupt Detection An interrupt is detected over the interrupt signaling line. Whenever there is a change in the voltage level (0 to 1 or 1 to 0) an interrupt is detected. ▪ What happens when an interrupt occurs? Current Program Interrupt Service Routine (ISR) 0x0000 instruction A 0x1000 instruction IA 0x0004 instruction B 0x1004 instruction IB 0x0008 instruction C 0x1008 instruction IC 0x000C instruction D Program counter (PC) finishes the 0x0010 instruction E instruction C Then it jumps to the address 0x0014 instruction F where the ISR starts. After completing the 0x0018 instruction G instruction IC the PC jumps back to address 0x000C (instruction D). UNIVERSITY of VAASA Tobias Glocker 75  Interrupts ▪ Interrupt Service Routine For every interrupt, one ISR must exist. When an interrupt is detected the micrcontroller runs into the ISR. Normally, each microprocessor/microcontroller has for every interrupt a fixed location in the memory, holding the address of its ISR. When an interrupt occurs the following steps are done: 1. The current instruction will be completed. The address of the next instruction will be saved on the stack. 2. The PC is intialized with the start address of the corresponding ISR given in the Interrupt Vector Table (IVT). 3. Then the ISR is executed until the last instruction (return from interrupt short: RET) of the ISR is executed. 4. The program continues from where it has been interrupted. The PC will be initalized with the address that has been saved on the stack before it jumped to the IVT. UNIVERSITY of VAASA Tobias Glocker 76  Interrupts ▪ Interrupt Vector Table high Interrupt Interrupt Flag Interrupt Vector Address / Number ROM Location - RESET - 0000H 0 INT0 (Ext. Int. 0) IE0 0003H Priority 1 Timer 0 TF0 000BH 2 INT1 (Ext. Int. 1) IE1 0013H 3 Timer 1 TF1 001BH 4 Serial TI/RI 0023H low [https://www.electronicwings.com/8051/8051-interrupts] UNIVERSITY of VAASA Tobias Glocker 77  Interrupts ORG 0H ▪ Memory Layout rom_start: LJMP main_code ORG 3H int0_vec: LJMP int0_isr ORG 13H int1_vec: LJMP int1_isr $yyy ISR INT0 (int0_isr) $xxx main_code: ;… $zzz ISR INT1 (int1_isr) $yyy int0_isr: $xxx main_code ;… $zzz int1_isr: ;… $013 $zzz $003 $yyy Interrupt Vector Table (IVT) $000 $xxx UNIVERSITY of VAASA Tobias Glocker 78  Interrupts ▪ Problem When interrupt line is high for a long time (assume level triggered interrupt) then ISR is executed again and again. INTRx time ISRx Instr. IA Instr. IB Instr. IC time INTR is still active ISRx Instr. IA Instr. IB Instr. IC time ▪ Solution: When entering the ISR, the interrupt must be disabled and enabled when the ISR has been executed. In some microcontroller’s the disabling and enabling of the interrupt is done automatically. Some microcontrollers require besides the disabling and enabling of the interrupt also the clearing of the interrupt flag. UNIVERSITY of VAASA Tobias Glocker 79  Interrupts ▪ Clearing of an Interrupt Request For clearing an interrupt request there are two solutions. Software Solution: Whenever the data register of the source (sensor, I/O unit) that generates an interrupt request is accessed, the interrupt is reset. Hardware Solution: In addition to the interrupt request wire (INTR) there is a interrupt acknowledge (IACK) wire for resetting the interrupt after the data register has been accessed. Micro- INTR controller INTR IACK IACK UNIVERSITY of VAASA Temperature Sensor Tobias Glocker 80  Interrupts ▪ Multiple Interrupt Devices Normally when an ISR is executed the Interrupt is disabled until it finishes its execution. If an interrupt occurs during the Micro- controller time when an ISR is executed, the ISR of INTR2 new interrupt will be executed after the completion of the current ISR. INTR0 INTR1 However it is possible that the current ISR is interrupted when a new interrupt occurs. Condition: Interrupt is not disabled during the Execution time of the current ISR. Temperature Sensors There is also the possibility of priority based Scheduling. Every Interrupt has a priority. The interrupt with the highest priority will be served CPU first. INTR0 ≥1 INTR1 Condition: ISR must be interruptable. INTR2 UNIVERSITY of VAASA Tobias Glocker 81  Interrupts ▪ Flowchart Interrupt Micro- controller INTR2 // Interrupt Service Routine ISR { // do something } INTR0 INTR1 Configure Interrupt, Sleep main Mode etc Temperature Sensors Enable Global Interrupt Infinite Loop Put the device in sleep mode Advantage: Processor can go into sleep mode. It wakes up when interrupt request is sent. UNIVERSITY of VAASA Tobias Glocker 82  Interrupts ▪ Timer Interrupt System Clock (CLK) CLK/8 CLK/... Prescaler CLK/... CLK/1024 8 Bit Timer (0...255) 16 Bit Timer (0...65535) UNIVERSITY of VAASA Tobias Glocker 83  Interrupts ▪ Defining the Cycle of the Timer Interrupt! First we need to know the following things: 1. What CPU Frequency will be used (CLK)? 2. Do we use a prescaler? 3. Do we use an 8 bit counter or a 16 bit counter? UNIVERSITY of VAASA Tobias Glocker 84  Interrupts ▪ Timer generates Rollover Interrupt Example: CLK = 4MHz, prescaler 8, 8 bit timer! f = CLK/prescaler = 4MHz/8 = 500kHz Time = 1/f = 1/500kHz = 2us (one clock pulse) 256 *2us = 512us (counter overflows) To generate an interrupt every 200us the timer needs to count to 100. Thus the count register (CRx) must be initialized with 256-100 = 156. CRx counter overflows -> interrupt occurs CRx += 1 time Time for one clock count (tick) UNIVERSITY of VAASA Tobias Glocker 85  Interrupts ▪ Timer generates Interrupt in Compare Mode Example: CLK = 4MHz, prescaler 8, 8 bit timer! f = CLK/prescaler = 4MHz/8 = 500kHz Time = 1/f =1/500kHz = 2us (one clock pulse) To generate an interrupt every 200us the timer needs to count to 100. Thus, the compare register (CMPREGx) must be initialized with 99*/100 in Clear Time on Compare match (CTC) Mode. * Some microcontrollers require one clock cycle for the comparison! CRx CMPREGx == Interrupt CRx CMPREGx==99*/100 CR += 1 time Time for one clock count (tick) UNIVERSITY of VAASA Tobias Glocker 86  Interrupts ▪ Timer generates Interrupt in Compare Mode Example: CLK = 4MHz, prescaler 8, 8 bit timer! f = CLK/prescaler = 4MHz/8 = 500kHz Time = 1/f =1/500kHz = 2us (one clock pulse) To generate an interrupt every 200us the timer needs to count to 100. Thus, the compare register (CMPREGx) must be initialized with 99*/100 and after each interrupt increased by 100. Resetting the counter register (CRx) is inaccurate. CRx counter overflows CMPREGx==199*/200 CMPREGx==99*/100 CR += 1 CMPREGx==43*/44 time Time for one clock count (tick) UNIVERSITY of VAASA Tobias Glocker 87  References ▪ Barnett, R., S. Cox and L. O’Cull (2007). Embedded C Programming and the ATMEL AVR. 2nd Edition. Thomson. ISBN-13: 978-1-4180-3959-2. ▪ Mazidi, M., Sa. Naimi & Se. Naimi (2011). The avr microcontroller and embedded system. Using assembly and c. PEARSON. ISBN-13: 978-0-13-800331-9. ▪ Strahnen, Manfred (2004). Computertechik II. Vorlesungsskript. Hochschule Ulm. UNIVERSITY of VAASA Tobias Glocker 88  Embedded System Architecture and Design (ICAT3050) Lecture 4 Lecture 3 Links to the Lectures Lecture 5 UNIVERSITY of VAASA Tobias Glocker 89  Table of Contents ▪ CPU Architecture ▪ Peripherals ▪ References UNIVERSITY of VAASA Tobias Glocker 90  CPU Architecture ▪ Overview CPU Address Bus Program Counter Control Bus Int. Sources Instruction Register Flags ALU Instruction decoder, timing and control Interrupt Data Bus Controller Please note: IVN Address Interrupt Vector Internal Buses Table (IVT) and Register A Interrupt Service Routine (ISR) Interrupt Unit that initializes the Register B are in the RAM (normal PC), Vector Program Counter when Register C ROM, or FLASH MEMORY Number an Interrupt occurs! (Microcontroller)! Register D UNIVERSITY of VAASA Tobias Glocker 91  CPU Architecture ▪ Resources of a CPU - Registers The CPU uses registers to store information temporarily. Two values that need to be processed, or the address of the value needed to be fetched from the memory can be considered as information. The size of the register can be 8Bits, 16Bits, 32Bits or even 64Bits. - Arithmetic/Logic Unit (ALU) The ALU is responsible for performing arithmetic functions such as ”add”, ”subtract”, ”multiply”, and ”divide” as well as logic functions such as ”and”, ”or” and so on. UNIVERSITY of VAASA Tobias Glocker 92  CPU Architecture ▪ Resources of a CPU - Program Counter (PC) In every CPU there is a program counter that points to the address of the next instruction that needs to be executed. ”The contents of the program counter are placed on the address bus to find and fetch the desired instruction”. - Instruction Decoder Interprets the instruction fetched into the CPU. An instruction decoder tells the CPU what steps should be done when receiving a certain instruction. UNIVERSITY of VAASA Tobias Glocker 93  CPU Architecture ▪ Internal working of CPUs Action Code Data move value 21H into register A B0H 21H add value 42H to register A 04H 42H add value 12H to register A 04H 12H Memory Contents of the Comments Address memory address 1400H B0H moving a value to register A 1401H 21H value to be moved 1402H 04H adding a value to register A 1403H 42H value to be added 1404H 04H adding a value to register A 1405H 12H value to be added 1406H F4H halt UNIVERSITY of VAASA Tobias Glocker 94  CPU Architecture ▪ Internal working of CPUs 1) The program counter must be initialized with the address from where the first instruction of the program starts. In this case (1400H). 2) The address 1400H is put on the address bus by the CPU to indicate that it wants to access the memory address 1400H. Over the control bus the CPU tells to the memory if it wants to read or write from/to the selected memory location. The content of this address (B0) is put on the data bus from where the CPU can receive this value. 3) After receiving the value the instruction is decoded with the instruction decoder. In this case (code value B0) stands for moving a value into register A. The instruction decoder takes care that the controller circuitry does precisely do that. Then the data value (21H) is read and moved to register A. Every time when an instruction is completed the program counter is initialized with the address of the next instruction. UNIVERSITY of VAASA Tobias Glocker 95  CPU Architecture ▪ Internal working of CPUs 4) When the code value 04H is received then the CPU knows that there is an addition to do between the next read value and the value in the register A. The addition is performed by the ALU. The result of this addition is written to register A (previous value of register A will be overwritten). 5) Then the other addition is executed (register value A + 12H). 6) When the CPU fetches and executes the ”HALT” instruction, the program counter is not incremented anymore. Without ”HALT” the program counter would be continously updated. UNIVERSITY of VAASA Tobias Glocker 96  CPU Architecture ▪ Instruction Pipeline The aim of an instruction pipeline is to increase the throughput of multiple instructions. Pipelining does not reduce the completion time of one instruction, but it increases the throughput by executing multiple operations in parallel. Example of a pipeline with six stages. IF ID OF EX MEM WB UNIVERSITY of VAASA Tobias Glocker 97  CPU Architecture ▪ Instruction Pipeline Abbreviation Pipeline Explanation Command IF Instruction Fetch Reads the next instruction that needs to be executed! ID Instruction Decodes the instructions! Decodes OF Operand(s) Fetch Reading the required operand(s)! EX Execute Executes the instruction! MEM Memory Access Saves the result (of an aritmetic operation) in the memory! WB Register write back Saves the result (of an aritmetic operation) in the register! UNIVERSITY of VAASA Tobias Glocker 98  CPU Architecture ▪ Instruction Pipeline Assume that every instruction requires six clock cycles. Calculate the amount of clock cycles needed for five instructions. a) Without pipelining! b) With pipelining! Solution for a) To execute one instruction six clock cycles are needed. Five instructions are executed. Total execution time = 5 * 6 clock cycles = 30 clock cycles UNIVERSITY of VAASA Tobias Glocker 99  CPU Architecture ▪ Instruction Pipeline Solution for b) Clock 1 2 3 4 5 6 7 8 9 10 Cycles Instr. 1 IF ID OF EX MEM WB Instr. 2 IF ID OF EX MEM WB Instr. 3 IF ID OF EX MEM WB Instr. 4 IF ID OF EX MEM WB Instr. 5 IF ID OF EX MEM WB Total execution time = 10 clock cycles Total execution time = number_of_stages + number_of_instructions – 1 UNIVERSITY of VAASA Tobias Glocker 100  CPU Architecture ▪ Instruction Pipeline Speed up factor (SF): The speed up factor is the relation between the total execution time without pipelining and the total execution time with pipelining. SF = total execution time without pipelining / total execution time with pipelining SF = 30 clock cycles / 10 clock cycles SF = 3 For five instructions the processor is three times faster with pipelining than without pipelining. UNIVERSITY of VAASA Tobias Glocker 101  CPU Architecture ▪ Instruction Pipeline Problems: - Not all instructions need 6 stages! - Not every instruction needs the same execution time! - There can be access conflicts. For example, when fetching an instruction (IF) and writing data to the memory (MEM) and to the register (WB). - There can be dependencies between the different pipeline stages. Increasing a register value that is used in the next instruction, for example. 1: Add 1 to R7 2: Copy R7 to R8 UNIVERSITY of VAASA Tobias Glocker 102  CPU Architecture ▪ Instruction Pipeline Problems: Unconditional Branches - Branch out of a normal instruction sequence causes a problem because the pipeline continues with fetching instruction sequentially. Since there is a jump to another part of the program, the following instructions after the jump condition that are already in the pipeline can not be used. Conditional Branches - More problematic are conditional branches. Here the jump is not guaranteed. The jump depends on the computed result. UNIVERSITY of VAASA Tobias Glocker 103  CPU Architecture ▪ Instruction Pipeline Conditional Branches: Assume that instruction 3 is a conditional jump to instruction 15. The pipeline must be emptied from the instructions 4 to 6. Clock 1 2 3 4 5 6 7 8 9 10 11 12 13 Cycles Instr. 1 IF ID OF EX MEM WB Instr. 2 IF ID OF EX MEM WB jump if zero Instr. 3 IF ID OF EX JZ Label1 Instr. 4 IF ID OF Instr. 5 IF ID Instr. 6 IF Label1: Instr. 15 IF ID OF EX MEM WB Instr. 16 IF ID OF EX MEM WB UNIVERSITY of VAASA Tobias Glocker 104  CPU Architecture ▪ Instruction Pipeline Solutions: There are techniques that are used in pipelined processors when the programmer assumes that each instruction completes before the next one begins. - Delaying the second instruction (and subsequent instruction) until the required value is ready for further processing. - Some processors are able to detect the dependency between instructions and execute the instructions in such a way, that they won’t need to wait for each other (out of order execution). UNIVERSITY of VAASA Tobias Glocker 105  CPU Architecture ▪ Instruction Pipeline Solution for conditional branches: Branch prediction Branch predictors are used to guess the result of a branch before it is known. Target: Flow optimization of the pipeline! Pattern History Table Two states: Strongly taken and weakly taken! Strongly taken: Probability for a jump is high! Weakly taken: Probability for a jump is low! If, for example, a conditional jump occured every third time (sequence 001001001) and the entry number of the pattern history table is 00, then the ”strongly taken” state is selected to indicate that after two zeros follows a one. UNIVERSITY of VAASA Tobias Glocker 106  CPU Architecture ▪ ”Von Neumann Architecture” and ”Harvard Architecture” Address Bus Code Data CPU Memory Memory Von Neumann Architecture Data Bus Address Bus Address Bus Code Data Memory CPU Memory Harvard Architecture Data Bus Data Bus UNIVERSITY of VAASA Tobias Glocker 107  CPU Architecture ▪ ”Von Neumann Architecture” and ”Harvard Architecture” Every processor has a memory space to store program (code) and data. Code: Contains instructions for the CPU (ROM/Flash Memory)! Data: Information to be processed (RAM)! Von Neumann (Princeton) Architecture: - Same buses are used to access code and data. Disadvantage: Slows down the processor speed, because each has to wait for the others to finish fetching. Harvard Architecture: - Seperate buses for code and data memory! - Four sets of different buses are required! 1) Bus to carry data from and to the CPU! 2) Address bus to access data! 3) Bus to carry code from and to the CPU! 4) Address bus to access code! Advantage: Process of program execution is faster! Disadvantage: The number of wire traces will be two times more than for the ”Von Neumann Architecture”! UNIVERSITY of VAASA Tobias Glocker 108  Peripherals ▪ Peripheral Overview ADC Micro- Analog-to-Digital Converter controller UART Universal Asynchronous Receiver Transmitter SPI Serial Peripheral Interface Timer/PWM I2C Inter-Integrated Circuit Timer/Pulse-Width-Modulation UNIVERSITY of VAASA Tobias Glocker 109  Peripherals Adj. ▪ Analog-to-Digital Converter (ADC) Power Supply Voltage Micro- + - Uin controller ADC Uin Time Example of a 2-Bit ADC Example: Input Voltage 0...2V 2 Bit ADC converter (0...3) ADC Code Event should occur when input voltage is higher than 1.55V. 11 Find the ADC code. 10 (1.55 * 4) / 2 = 3.1 3.1 -> ADC code in binary 11 01 𝑈_𝑒𝑣𝑒𝑛𝑡 ∗(2𝑛 ) 00 Vin ADC_CODE_DEC = 𝑈_𝑖𝑛_𝑚𝑎𝑥 n = number of ADC bits 0 0.5 1 1.5 2 Then convert the ADC code to binary. UNIVERSITY of VAASA Tobias Glocker 110  Peripherals Vin 𝑉𝑟𝑒𝑎𝑑 𝐴𝐷𝐶_𝑉𝐴𝐿𝑈𝐸 = Vmax 𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛 2𝑛 t Please note, that the ADC Vmin value must be always rounded down! Figure 5. Voltage Signal Vin Vin t t Figure 6. Low Sampling Rate Figure 7. High Sampling Rate Nyquist Theorem: fs ≥ 2f UNIVERSITY of VAASA Tobias Glocker 111  Peripherals Enable ADC, set Ready Bit etc. Data Bus ▪ ADC Components Control and Status Register ADC Data Register VREF Conversion Logic Select Channel Register Input Channels Multiplexer UNIVERSITY of VAASA Tobias Glocker 112  Peripherals ▪ Analog-to-Digital Converter (ADC) If a microcontroller does not have an integrated ADC, an external ADC can be used which is connected with the microcontroller! Micro- External controller ADC Universal Asynchronous Receiver Transmitter (UART) Serial Peripheral Interface (SPI) etc. UNIVERSITY of VAASA Tobias Glocker 113  Peripherals ▪ Universal Asynchronous Receiver Transmitter (UART) Bytes of data are transmitted asindividual bits in a sequential fashion. When the receiver receives the bits it re-assembles them into bytes. Baudrates Stop Bits Character Frame 1200 19200 1 2400 38400 1.5 Start D0 D1 D2 D3 D4 D5 D6 D7 PAR Stop 4800 57600 2 9600 115200 Parity Bit: even, odd parity Micro- TxD TxD Micro- or disabled contr. 1 RxD RxD contr. 2 Voltage GND GND 5 0 Time 0 1 1 0 0 1 1 0 0 1 1 start bit 0 bit 7 odd stop parity sent value 0x33 -> ASCII char ’3’ UNIVERSITY of VAASA Tobias Glocker 114  Peripherals ▪ Even versus Odd Parity 7 bits of data Count of 1 Even Parity Odd Parity bits 0000000 0 00000000 00000001 1010001 3 10100011 10100010 1101001 4 11010010 11010011 1111111 7 11111111 11111110 UNIVERSITY of VAASA Tobias Glocker 115  Peripherals ▪ RS232 Voltage 12 0 Time -12 0 1 1 0 0 1 1 0 0 1 start bit 0 bit 7 stop TxD TxD MAX TxD TxD Micro- PC RxD GND RxD GND 232 RxD GND RxD GND Contr. voltage level converter A transmission example for the communication of Computer (PC) and UART. UNIVERSITY of VAASA Tobias Glocker 116  References ▪ Barnett, R., S. Cox and L. O’Cull (2007). Embedded C Programming and the ATMEL AVR. 2nd Edition. Thomson. ISBN-13: 978-1-4180-3959-2. ▪ Mazidi, M., J. Mazidi & R. McKinlay (2013). The 8051 Microcontroller. A System Approach. PEARSON. ISBN-13: 978-0-13-304217-7. ▪ Stallings, William (2003). Computer Organization & Architecture. Sixth Edition. Prentice Hall. ISBN 0-13-049307-4. ▪ Strahnen, Manfred (2004). Computertechik III. Vorlesungsskript. Hochschule Ulm. UNIVERSITY of VAASA Tobias Glocker 117  Embedded System Architecture and Design (ICAT3050) Lecture 5 Lecture 4 Links to the Lectures Lecture 6 UNIVERSITY of VAASA Tobias Glocker 118  Table of Contents ▪ Microcontroller ▪ Assembly Language Programming ▪ References UNIVERSITY of VAASA Tobias Glocker 119  Microcontroller ▪ Overview PROGRAM ROM / RAM EEPROM TIMERS Flash Mem. CPU Program Bus Bus Interrupt Ports Other Unit Peripherals OSC I/O Pins UNIVERSITY of VAASA Tobias Glocker 120  Microcontroller ▪ Components Program ROM / Flash Memory - Contains the program! CPU - Contains register, Aritmetic/Logic Unit (ALU), Instruction decoder, Program Counter (PC), etc. OSC - Determines the clock speed! RAM - Contains modificable data! EEPROM - Can be used to store data, or reading data during runtime. After switching off the power, the data remains in the memory. Timer - Can be used for generating different output signals! - Generating an interrupt after a certain time! UNIVERSITY of VAASA Tobias Glocker 121  Microcontroller ▪ Components Interrupt Unit - It takes care of the interrupt handling! Ports - I/O Pins! Other Peripherals - Analog-to-Digial Converter (ADC), for example! UNIVERSITY of VAASA Tobias Glocker 122  Microcontroller ▪ Pin Configurations (ADC0) P1.0 (ADC1) P1.1 PORT1 PORT3 (RX) P2.0 (TX) P2.1 PORT2 PORT4 UNIVERSITY of VAASA Tobias Glocker 123  Microcontroller ▪ Pin Configurations General-Purpose Input/Output (GPIO). Data Direction Register (DDR) Data Register (PORT) Input Pin Register (PIN) Bit 7 Bit 0  Each of these registers has usually eight Bits! - If a bit in the DDRx is set to one, it means that the corresponding PIN is defined as output pin, if zero it is defined as input PIN. - When a bit in the PORTx is set to one and the corresponding PIN was defined as an input then the pull-up resistor is activated. Setting the bit to 0 will deactivate the pull-up resistor. - When a bit in the PORTx is set to one and the corresponding PIN was defined as output, the output is driven high, if the bit is set to zero the output is driven low. UNIVERSITY of VAASA Tobias Glocker 124  Microcontroller ▪ Pull-up vs. Pull-down Resistor Circuit 5V 5V Micro- Micro- controller controller GND GND Pull-up resistor circuit Pull-down resistor circuit UNIVERSITY of VAASA Tobias Glocker 125  Microcontroller ▪ Pushbuttons and LEDs 5V 5V Microcontroller UNIVERSITY of VAASA Tobias Glocker 126  Microcontroller ▪ Components of a Microcontroller CPU Program Stack Counter (PC) Pointer (SP) SRAM Instruction Registers Register … … Program Flash Instruction Decoder Rn ALU Status Register UNIVERSITY of VAASA Tobias Glocker 127  Microcontroller ▪ General Purpose Registers and ALU PSW (Program Status Word) Register CY AC F0 RS1 RS0 OV -- P MSB LSB General Purpose Registers BIT Meaning of the BIT Carry Bit CY Carry Flag 8Bit wide 8Bit wide AC Auxillary Carry Flag Status Register F0 For general purpose! ALU RS1 Register Bank Selector Bit 1 RS0 Register Bank Selector Bit 0 Flags 8Bit wide OV Overflow Flag -- User-definable Bit P Parity Flag! Set when an odd number of 1 bits is in the accumulator! UNIVERSITY of VAASA Tobias Glocker 128  Microcontroller ▪ Explanation of the Flags (Addition of unsigned numbers) Example 1 (Correct Result) The Carry Flag (CY) is set, when the 1 0 0 1 1 1 0 0 (9CH) result is above 255 (0xFF, 11111111). + 0 0 0 0 1 1 1 1 (0FH) 1 0 1 0 1 0 1 1 (ABH) CY = 0 → No carry after the Bit_7! AC = 1 → Carry from Bit_3 to Bit_4! P = 1 → Accumulator has an odd number of 1s! Example 2 (Incorrect Result) 1 0 0 1 1 1 0 0 (9CH) 9CH + 0 1 1 0 0 1 0 0 (64H) + 64H 0 0 0 0 0 0 0 0 (00H) 100H CY = 1 → Carry after the Bit_7! AC = 1 → Carry from Bit_3 to Bit_4! P = 0 → Accumulator has an even number of 1s (it has zero ones)! UNIVERSITY of VAASA Tobias Glocker 129  Microcontroller ▪ Explanation of the Flags (Subtraction of unsigned numbers) Example 3 (Correct Result) The Carry Flag (CY) is set, when the 1 0 0 1 1 1 0 0 (9CH) result is below 0 (0x00, 00000000). - 0 0 0 0 1 1 1 1 (0FH) 1 0 0 0 1 1 0 1 (8DH) CY = 0 → No carry after the Bit_7! AC = 1 → Carry from Bit_3 to Bit_4! P = 0 → Accumulator has an even number of 1s! Example 4 (Incorrect Result) 1 0 0 1 1 1 0 0 (9CH) 156 - 1 0 0 1 1 1 0 1 (9DH) - 157 1 1 1 1 1 1 1 1 (FFH) -1 CY = 1 → Carry after the Bit_7! AC = 1 → Carry from Bit_3 to Bit_4! P = 0 → Accumulator has an even number of 1s (it has zero ones)! UNIVERSITY of VAASA Tobias Glocker 130  Microcontroller ▪ Explanation of the Flags (Addition of signed numbers) Overflow flag (OV) - Is set, when the result of an operation with signed numbers is too large! - Used in signed arithmetic operations! - OV is set when the following conditions occurs! → Carry from Bit_6 to Bit_7 but no carry after BIT_7 (CY = 0)! → Carry after Bit_7 (CY = 1) but no carry from Bit_6 to Bit_7! -128 … +127 Example 1 (Correct Result) Sign Magnitude 0110 0000 + 96 60H Bit_7 Bit_0 +0001 0100 + 20 + 14H 0111 0100 + 116 74H MSB LSB According to the CPU, the result is 116. The magnitude is represented Result is correct because the OV flag is not set (OV = 0)! in it’s two’s complement!!! UNIVERSITY of VAASA Tobias Glocker 131  Microcontroller ▪ Explanation of the Flags (Subtraction of signed numbers) Example 2 (Incorrect Result) 0110 0000 + 96 60H +0100 0110 + 70 + 46H 1010 0110 + 166 A6H (-90) According to the CPU, the result is -90. Result is wrong because the OV flag is set (OV = 1)! Example 3 (Correct Result) 1111 1110 - 2 FEH +1111 1011 + -5 + FBH 1111 1001 - 7 F9H (-7) According to the CPU, the result is -7. Result is correct because the OV flag is not set (OV = 0)! UNIVERSITY of VAASA Tobias Glocker 132  Microcontroller ▪ Explanation of the Flags (Subtraction of signed numbers) Example 4 (Incorrect Result) 1000 0000 - 128 80H +1111 1110 + -2 + FEH 0111 1110 - 130 7EH (+126) According to the CPU, the result is +126. Result is wrong because the OV flag is set (OV = 1)! UNIVERSITY of VAASA Tobias Glocker 133  Microcontroller ▪ Inside the 8051 Microcontroller (Block Diagram) External Interrupts Interrupt Control On-chip ROM / Etc. for Program On-chip TIMER 1 Counter CPU Code RAM TIMER 0 Inputs Bus Four I/O Serial Control Ports Port OSC P0 P2 P1 P3 TXD RXD UNIVERSITY of VAASA Tobias Glocker 134  Microcontroller ▪ Features of the 8051 Feature Quantity ROM 4K Bytes RAM 128 Bytes Timer 2 I/O Pins 32 Serial Port 1 Interrupt Sources 6 ROM indicates on-chip space! UNIVERSITY of VAASA Tobias Glocker 135  Microcontroller ▪ Inside the 8051 Microcontroller (Registers) 8 Bits A = Accumulator B = Helps Register A for arithmetic/logical Operations A R0 … R7 = General Purpose Registers Bit_7 Bit_0 B D7 D6 D5 D4 D3 D2 D1 D0 R0 MSB LSB R1 R2 DPTR = Data Pointer R3 PC = Program Counter R4 16 Bits R5 DPTR DPH DPL R6 PC PC (Program Counter) R7 UNIVERSITY of VAASA Tobias Glocker 136  Assembly Language Programming ▪ Data Type Most of the assembly languages have no data type! The 8051 has only one data type! It is 8 Bits, and each register has the size of 8 Bits! It is the programmer’s responsibility, when larger data (more than 8Bits, on an 8 Bit microcontroller) needs to be processed! ▪ Data Format Representation Hex numbers: 66H Binary numbers: 10001001B Decimal numbers: 6 ASCII characters: ‘3’ or ‘s’ ▪ Comments in Assembly Language Comments begin with a semicolon (;)! UNIVERSITY of VAASA Tobias Glocker 137  Assembly Language Programming ▪ Rules for labels in Assembly language Names of the labels should be meaningful! Names of the labels must be unique! Names of the labels consist of alphabetic in both upper and lower case, the digits 0 to 9 and special characters like question mark (?), period (.), at (@), underline (_) and dollar sign($)! Mnemonics are reserved words for instructions (their name can not be used for labels)! ▪ Structure of Assembly language [label:] mnemonic [operands] [; comment] UNIVERSITY of VAASA Tobias Glocker 138  Assembly Language Programming ▪ Assembler Directives Instructions: Tell the CPU what needs to be done! Directives: Directions for the Assembler! ORG (Origin) Directive Indicates the beginning of the address! ORG 500H EQU (Equate) Directive Directive for defining a constant value or a fixed address. COUNT EQU 25 … MOV R3, #COUNT UNIVERSITY of VAASA Tobias Glocker 139  Assembly Language Programming ▪ Assembler Directives END Directive Indicates the end of the source (asm) file! END UNIVERSITY of VAASA Tobias Glocker 140  Assembly Language Programming ▪ 8051 Directive DB (Define Byte) Directive It is the most widely used data directive in the assembler! Used to define 8-bit data! Can be used to define ASCII Strings! ORG 500H DATA1: DB 28 DATA2: DB 00110101B DATA3: DB 39H ORG 510H DATA4: DB ”2591” ; ASCII NUMBERS ORG 518H DATA6: DB ”MY NAME IS TOBIAS” ; ASCII CHARACTERS UNIVERSITY of VAASA Tobias Glocker 141  Assembly Language Programming ▪ Instructions MOV (Copies Data from one location to another!) MOV destination, source MOV A, #55H ; load value 55H into Register A MOV A, #0F9H ; load value F9H into Register A MOV A, #55 ; load value 55 (decimal) into Register A MOV A, #00000100B ; load value 4 (binary) into Register A MOV R0, #’4’ ; load the value ’4’ (ASCII value 34H) into Register R0 MOV R0, A ; copy contents of Register A into Register R0 MOV A, R3 ; copy contents of Register R3 into Register A ADD (Add the source operand to the Accumulator) ADD A, source MOV A, #20H ; load value 20H into Register A MOV R2, #33H ; load value 33H into Register R2 ADD A, R2 ; add the value of Register R2 to the Register A (A = A + R2) UNIVERSITY of VAASA Tobias Glocker 142  Assembly Language Programming ▪ Instructions 2762H -1296H SUBB ----------- SUBB A, source 14CCH MOV A, #62H SUBB A, #96H MOV R7, A Dest > Source → CY=0 → Positive Result! MOV A, #27H Dest == Source → CY=0 → Result 0! Dest < Source → CY = 1 → Negative Result! SUBB A, #12H (2’s complement) MOV R6, A A = A - source - CY MUL AB (Multiply AxB) MOV A, #5 MOV B, #7 MUL AB ; result is placed in A (lower Byte) and in B (higher Byte) → A = 35 = 23H, B=0 UNIVERSITY of VAASA Tobias Glocker 143  Assembly Language Programming ▪ Instructions DIV AB MOV A, #35 MOV B, #10 DIV AB ; A = 3 (quotient) and B = 5 (remainder) INC INC A INC Rn DEC DEC A DEC Rn UNIVERSITY of VAASA Tobias Glocker 144  Assembly Language Programming ▪ Program example: ORG 0H ; start (origin) at location 0 MOV R5, #25H ; load value 25H into Register R5 MOV A, #0 ; load value 0 into Register A ADD A, R5 ; add the contents of Register R5 to Register A (A = A + R5) ADD A, #12H ; add the value 12H to Register A (A = A + 12H) HERE: SJMP HERE ; endless loop or SJMP $ END ; end of asm source file How could the above code be optimized? UNIVERSITY of VAASA Tobias Glocker 145  Assembly Language Programming ▪ Steps to create a program Editor myprog.asm Assembler myprog.obj myprog.lst Linker other *.obj files Object to HEX Converter myprog.hex UNIVERSITY of VAASA Tobias Glocker 146  Assembly Language Programming ▪ ASM, OBJECT, LST and HEX Files ▪ ASM File Contains the source code; file extension *.asm! ▪ OBJECT File Contains the machine code. ▪ LST File Contains opcode, addresses and so