Lecture 6 - DeMorgan’s Laws, Karnaugh Maps PDF

ECOR1044: Binary and Boolean Logic III De Morgan’s Laws Karnaugh Maps 1 De Morgan’s Laws De Morgan’s Laws: a theorem relating AND & OR gates. – OR gate with inverted inputs AND gate with an inverted output. – AND gate with inverted inputs OR...

ECOR1044: Binary and Boolean Logic III De Morgan’s Laws Karnaugh Maps 1 De Morgan’s Laws De Morgan’s Laws: a theorem relating AND & OR gates. – OR gate with inverted inputs AND gate with an inverted output. – AND gate with inverted inputs OR gate with an inverted output. 2 3 4 De Morgan’s Laws 5 De Morgan’s Laws – Graphical Comparison Compare the following circuits, which of these is easier to understand? 6 De Morgan’s Laws – Real World Comparison A NAND/NOR logic schematic for starting a train with conditions: 7 De Morgan’s Laws – Real World Comparison A simplified AND/OR logic schematic for starting a train with conditions: 8 De Morgan’s Laws – Conversion Exp. 1: Convert the following circuit to only include AND and OR gates 𝑭 = (𝑨.B)+(C.D) 𝑭 = (𝑨.B)+(C.D) Note: One output circle cancels all the input circles it feeds 9 De Morgan’s Laws – Conversion Exp. 2: Convert the following circuit to only include AND & OR gates. 10 De Morgan’s Laws – Conversion Exp. 3: Find F 𝑭 = (𝑨+B).(A.B) 11 De Morgan’s Laws – Conversion Exp. 4: Find F 𝑭 = (A+B).(A.B) 12 De Morgan’s Laws – Conversion Exp. 5: Find F 𝑭 = (𝑨+𝑨).(B.B)= (𝑨+𝑨).(0)= 0 13 De Morgan’s Laws – Conversion Exp. 6: Find F 𝑭 = (𝑨+𝑨).(B.B)= (𝑨+𝑨).(1)= (𝑨+𝑨)=1 14 De Morgan’s Laws – Conversion Exp. 7: Find F 𝑭 = (𝑨.𝑨).(B+B)= (0).(B+B)= 0 15 De Morgan’s Laws – Larger Circuits Exp. 8: Find F 𝑭= (𝑨+B) (C+𝑩)+(BD) 16 K-Maps Karnaugh Maps, or K-maps, are a graphical method used to simplify Boolean algebra expressions, particularly in digital logic design to their minimal form. So, it can be implemented with fewer logic gates. Purpose of K-Maps: K-maps help simplify complex Boolean expressions into simpler forms, which: ✓ Reduces the number of logic gates required. ✓ Optimizes circuit performance and lowers cost and power consumption. The advantages of K-Maps: ✓ Provides a visual method for simplification. ✓ Useful for up to 4-6 variables. 17  A=1 A=0 K-Maps + The left half-table is for when 𝐴 = 0, and the right half-table is for when 𝐴 = 1. 18 K-Maps 19 K-Maps (Rules) 20 K-Maps (Rules) 21 K-Maps (Rules) 22 K-Maps (Rules) 23 K-Maps (Rules) 24 K-Maps (Rules) 25 Three-Variable K-Maps x1 x2 x3 x1 x2 0 0 0 m0 x3 00 01 11 10 0 0 1 m1 0 m0 m2 m6 m4 0 1 0 m2 0 1 1 m3 1 m1 m3 m7 m5 1 0 0 m4 1 0 1 m5 (b) Karnaugh map 1 1 0 m6 1 1 1 m7 (a) Truth table 26 K-Maps 27 Three-Variable K-Maps f =  (0,4) = B C f =  (4,5) = A B f =  (0,1,4,5) = B f =  (0,1,2,3) = A BC BC BC BC A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 f =  (0,4) = A C f =  (4,6) = A C f =  (0,2) = A C f =  (0,2,4,6) = C BC BC BC BC A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 28 Four-Variable K-Maps x1 x2 x3 x4 0 0 0 0 m0 x1 0 0 0 1 m1 x1 x2 0 0 1 0 m2 x3 x4 00 01 11 10 0 0 1 1 m3 0 1 0 0 m4 m0 m4 m 12 m8 00 0 1 0 1 m5 0 1 1 0 m6 0 1 1 1 m7 01 m1 m5 m 13 m9 1 0 0 0 m8 x4 1 0 0 1 m9 11 m3 m7 m 15 m 11 1 0 1 0 m10 x3 1 0 1 1 m11 m2 m6 m 14 m 10 10 1 1 0 0 m12 1 1 0 1 m13 1 1 1 0 m14 x2 29 1 1 1 1 m15 Four-Variable K-Maps CD CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 1 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 01 0 0 0 0 01 0 1 0 0 01 0 0 0 0 01 1 0 0 1 11 0 0 0 0 11 0 1 0 0 11 0 1 1 0 11 0 0 0 0 10 1 0 0 0 10 0 0 0 0 10 0 0 0 0 10 0 0 0 0 f =  (0,8) = B C D f =  (5,13) = B C D f =  (13,15) = A B D f =  (4,6) = A B D CD CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 0 0 1 1 00 0 0 0 0 00 0 0 1 1 00 1 0 0 1 01 0 0 1 1 01 1 0 0 1 01 0 0 0 0 01 0 0 0 0 11 0 0 0 0 11 1 0 0 1 11 0 0 0 0 11 0 0 0 0 10 0 0 0 0 10 0 0 0 0 10 0 0 1 1 10 1 0 0 1 f =  (2,3,6,7) = A C f =  (4,6,12,14 ) = B D f =  (2,3,10,11 ) = B C f =  (0,2,8,10) = B D 30 Four-Variable K-Maps CD CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 0 0 0 0 00 0 0 1 0 00 1 0 1 0 00 0 1 0 1 01 1 1 1 1 01 0 0 1 0 01 0 1 0 1 01 1 0 1 0 11 0 0 0 0 11 0 0 1 0 11 1 0 1 0 11 0 1 0 1 10 0 0 0 0 10 0 0 1 0 10 0 1 0 1 10 1 0 1 0 f =  (0, 3,5, 6, 9,10,12,15) f =  (1, 2, 4, 7,8,11,13,14) f =  (4,5, 6, 7) = A B f =  (3,7,11,15) = C D f = A  B C D f = A  B C D CD CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 0 1 1 0 00 1 0 0 1 00 0 0 0 0 00 1 1 1 1 01 0 1 1 0 01 1 0 0 1 01 1 1 1 1 01 0 0 0 0 11 0 1 1 0 11 1 0 0 1 11 1 1 1 1 11 0 0 0 0 10 0 1 1 0 10 1 0 0 1 10 0 0 0 0 10 1 1 1 1 f =  (1, 3,5, 7,9,11,13,15) f =  (0,2,4,6,8,10,12,14) f =  (4,5,6,7,12,13,14,15) f =  (0,1,2,3,8,9,10,11) f =D f =D f =B f =B 31 Parity Checker Parity Checker is a logic circuit that checks for possible errors in the transmission. This circuit can be an even or odd parity checker. 32 Example of Four-Variable K-Maps 33 Example of Four-Variable K-Maps 34 Example of Four-Variable K-Maps 35 Example of Four-Variable K-Maps 36 Design of combinational digital circuits Steps to design a combinational digital circuit: ✓ From the problem statement derive the truth table ✓ From the truth table derive the unsimplified logic expression ✓ Simplify the logic expression ✓ From the simplified expression draw the logic circuit Example: Design a 3-input (A,B,C) digital circuit that would give at its output (X) a logic 1 only if the binary number formed at the input has more ones than zeros. Inputs Output A B C X X =  (3, 5, 6, 7) 0 0 0 0 0 1 0 0 1 0 X BC 2 0 1 0 0 A 00 01 11 10 3 0 1 1 1 0 0 0 1 0 4 1 0 0 0 1 0 1 1 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 X = AC + AB + BC 37 A B C Design of combinational digital circuits Example: Design a 4-input (A,B,C,D) digital circuit that would give at its output (X) a logic 1 only if the binary number formed at the input is from 2 to 9. Inputs Output A B C D X X =  (2,3,4,5,6,7,8,9) 0 0 0 0 0 0 1 0 0 0 1 0 X 2 0 0 1 0 1 CD 3 0 0 1 1 1 AB 00 01 11 10 4 0 1 0 0 1 00 0 0 1 1 Same 5 0 1 0 1 1 01 1 1 1 1 6 0 1 1 0 1 7 0 1 1 1 1 11 0 0 0 0 8 1 0 0 0 1 10 1 1 0 0 9 1 0 0 1 1 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 0 X = AC + AB + A B C 13 1 1 0 1 0 14 1 1 1 0 0 38 15 1 1 1 1 0 A B C D X Design of combinational digital circuits Exercise: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if there is more ones than zeros in the binary number formed at the input. Inputs Output X= A B C D 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 CD AB 00 01 11 10 3 0 0 1 1 4 0 1 0 0 00 5 0 1 0 1 01 6 0 1 1 0 7 0 1 1 1 11 8 1 0 0 0 10 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 X= 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 A B C D X X 39 Sample Problem ATM machine has three options: Print statement Withdraw money Deposit money ATM machine will charge $1.00 to: Withdraw Print out statement with no transactions No charge for: Deposits without withdrawal 40 Sample Problem A truth table displays all possible INPUTS OUTPUT input / output combinations. P W D C 0 0 0 0 INPUT OUTPUT 0 0 1 0 P = Print C = Charge 0 1 0 1 W = Withdraw 0 1 1 1 D = Deposit 1 0 0 1 1 0 1 0 0 = “do not” 0 = $0.00 1 1 0 1 1 = “do” 1 = $1.00 1 1 1 1 41  Boolean Equations Boolean Equations Outputs with a value of INPUTS OUTPUT “ONE” are kept P W D C 0 0 0 0 C = PWD 0 0 1 0 0 1 0 1 + PWD 0 1 1 1 1 0 0 1 + PWD 1 0 1 0 1 1 0 1 + PWD 1 1 1 1 + PWD 42 Karnaugh Maps(K-maps) C = PWD+ PWD+ PWD + PWD + PWD 0 0 PWD 0 1 1 1 1 0 P W PW P W PW 0D 0 1 1 1 1D 0 1 1 0 _ Why can’t Whyyou can’tswitch PW you loop theand PW? three adjacent 1s in the top row together? 43  Karnaugh Maps(K-maps) C = PWD+ PWD+ PWD + PWD + PWD 0 0 0 1 1 1 1 0 P W PW P W PW 0D 0 1 1 1 1D 0 1 1 0 NOTE: Circle neighboring ONES in powers of 2. Try to find the greatest amount of “neighbors.” Only overlap circles as a last resort! 44 Simplified Boolean Equations _ _ _ D D PWD PWD Opposite values PW 0 0 cancel out PW 1 1 1 1_ PW 1 1 1 1PWD 1_ _ C=W _ + PD PW 1 0 _ 1 PWD PWD PWD 45  Combinational Logic Circuit Combinational Logic Circuit W C =W P _ + PD D _ PD D 46 Questions? 47