lec1digita 2.pdf

Digital and logic circuits 2 Prof. Dr. Labib M. Labib [email protected] Lec. 1 Outline Course Introduction – Course Information – Textbook – Grading – Course Outline Course Information Instructor: Dr. Labib M. Labib Email: Labibm@hotmail...

Digital and logic circuits 2 Prof. Dr. Labib M. Labib [email protected] Lec. 1 Outline Course Introduction – Course Information – Textbook – Grading – Course Outline Course Information Instructor: Dr. Labib M. Labib Email: [email protected] Email: [email protected] Office: Computer & system Eng. Dept. Office Hours for Dr. Labib:  References Mano, M. Morris, and Charles R. Kime. Logic and computer design fundamentals. Pearson Higher Education, 2015 Thomas L. Floyed, Digital fundamentals, Pearson international edition, 11th edition, 2019 Mano, M. Morris, “ Digital Design” , 1  Grading – Midterm Exam 20 – Homework's & Lec. & sec 30 – Final Exam 50 – Total degree 100 Policies – Attendance is required – All submitted work must be yours – Cheating will not be tolerated – Homework's are due on the midterm or tests dates No. of lec. /week 2 hours Exc. 2 hours Demonstrator syllabus Latches – SR Flip flops – D Flip flops – JK flip flops – T Flip flops– Edge triggered flip flops – Sequential circuit analysis – Analysis of clocked sequential circuits – state reduction – flip flop excitation tables – design procedure – registers – shift registers – ripple counters – synchronous counters – random access memory (RAM) – memory decoding – Algorithmic state machine (ASM): (timing consideration – control implementation – design with multiplexers) – Applications using FPGA - Practical experiments using TTL logic chips with the aid of 555 timer IC. Review Number systems Logica gates Combinational circuits Adder- subtractor- Multiplier- Decoder – encode- Multplexers- Comparator  Review Logic circuits combinational sequential A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. Sequential employ storage elements in addition to logic gates. Their outputs are a function of the inputs and the state of the storage elements COMBINATIONAL CIRCUITS n For n input variables, there are 2 possible combinations of the binary inputs and m outputs. Combinational Logic Report 1 Write a report about the following : *Logic gate (AND, OR,NOT, NAND, NOR, XOR, XNOR, Buffer) * Half adder, Full adder, Decoder , Multiplexer Sequential Logic Synchronous Sequential Logic Introduction Hand-held devices, cell phones, navigation receivers, personal computers, digital cameras, personal media players, and etc have the ability to send, receive, store, retrieve, and process information represented in a binary format So that, the devices must have memory. This chapter examines the operation and control of these devices and their use in circuits and enables you to better understand what is happening in these devices when you interact with them.  Cont. Introduction The next output of these circuits depends not only the present input but also the present output  SEQUENTIAL CIRCUITS The storage elements are devices capable of storing binary information. a sequential circuit is specified by a time sequence of inputs, outputs, and internal states  Types of sequential circuits There two types of sequential circuits: sequential circuits synchronous sequential asynchronous sequential The behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change synchronous a system whose behavior can be defined from the knowledge of its signals at sequential circuit discrete instants of time. The storage elements commonly used in asynchronous sequential circuits are time-delay devices  A synchronous sequential circuit employs signals that affect the storage elements at only discrete instants of time. Synchronization is achieved by a timing device called a clock (clock and clk) generator, Filp Flop The storage elements (memory) used in clocked sequential circuits are called flip flops. A flip-flop is a binary storage device capable of storing one bit of information A sequential circuit may use many flip-flops to store as many bits as necessary. A change in state of the flip-flops is initiated only by a clock pulse transition  STORAGE ELEMENTS: LATCHES A storage element in a digital circuit can maintain a binary state indefinitely The major differences among various types of storage elements are in the number of inputs they possess and in the manner in which the inputs affect the binary state. Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches , Latches are said to be level sensitive devices; those controlled by a clock transition are flip-flops. flip-flops are edge- sensitive devices latches are the basic circuits from which all flip-flops are constructed.  Difference Between Flip-Flop and Latch Flip-Flop Latch Flip-flop is a bistable device i.e., it has two stable states that are Latch is also a bistable device whose states are also represented as 0 and 1. represented as 0 and 1. It checks the inputs but changes the output only at times It checks the inputs continuously and responds to the defined by the clock signal or any other control signal. changes in inputs immediately. It is a edge triggered device. It is a level triggered device. Gates like NOR, NOT, AND, NAND are building blocks of flip These are also made up of gates. flops. They are classified into asynchronous or synchronous flipflops. There is no such classification in latches It forms the building blocks of many sequential circuits These can be used for the designing of sequential circuits like counters. but are not generally preferred. Flip-flop always have a clock signal Latches doesn’t have a clock signal Flip-flop can be build from Latches ex:D Flip-flop, JK Flip-flop Latches can be build from gates ex:SR Latch, D Latch  SR Latch Latch with NOR gates when put 1 on S , 0 to R is to set When to put 0 on S and 1 on R is to reset Latch with NAND gates when put 0 on S ,1 to R is to set When to put 1 on S and 0 on R is to reset  If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1 is forbidden. In normal operation, this condition is avoided by making sure that 1’s are not applied to both inputs simultaneously. Comparing between latches with NOR & NAND In comparing the NAND with the NOR latch, note that the input signals for the NAND require the complement of those values used for the NOR latch. Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an S’R’ latch. The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in their complement form to activate the circuit. The difference between NOR latch and NAND latches S-R S’R’ NOR NAND Active High set S =1, R=o, Reset S=0, R=1 Active Low set S =0, R=1, Reset S=1, R=0 No Change S=0, R=0 No Change S=1, R=1 Forbidden state S= 1, R= 1 Forbidden state S= 0, R= 0 SR Latch with control input D Latch (Transparent Latch) One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time The D latch receives that designation from its ability to hold data in its internal storage. The output follows changes in the data input as long as the enable input is asserted.  D Latch has 2 inputs the first is D and the other is En The D input goes directly to the S input, and its complement is applied to the R input. the circuit is often called a transparent latch. Graphic symbols for latches  STORAGE ELEMENTS: FLIP-FLOPS The state of a latch or flip-flop is switched by a change in the control input. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic-1 level The problem with the latch is that it responds to a change in the level of a clock pulse.  Edge-Triggered D Flip-Flop Thus, a change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to 0. The behavior of the master–slave flip-flop just described dictates that (1) the output may change only once, (2) a change in the output is triggered by the negative edge of the clock, and (3) the change may occur only during the clock’s negative level. The value that is produced at the output of the flip-flop is the value that was stored in the master stage immediately before the negative edge occurred. D flip flop with positive edge It is also possible to design the circuit so that the flip-flop output changes on the positive edge of the clock. This happens in a flip-flop that has an additional inverter between the Clk terminal and the junction between the other inverter and input En of the master latch. Such a flip-flop is triggered with a negative pulse, so that the negative edge of the clock affects the master and the positive edge affects the slave and the output terminal. The Q output goes to the state of the D input at the time of the positive-going clock edge. Edge-triggered D flip-flop Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig. 5.10. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. This causes the output to remain in its present state. Input D may be equal to 0 or 1. If D = 0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset state, making Q = 0. If there is a change in the D input while Clk = 1, terminal R remains at 0 because Q is 0. Thus, the flip-flop is locked out and is unresponsive to further changes in the input. When the clock returns to 0, R goes to 1, placing the output latch in the quiescent condition without changing the output. Similarly, if D = 1 when Clk goes from 0 to 1, S changes to 0. This causes the circuit to go to the set state, making Q = 1. Any change in D while Clk = 1 does not affect the output. In sum, when the input clock in the positive-edge-triggered flip-flop makes a positive transition, the value of D is transferred to Q. A negative transition of the clock (i.e., from 1 to 0) does not affect the output, nor is the output affected by changes in D when Clk is in the steady logic-1 level or the logic-0 level. Hence, this type of flip- flop responds to the transition from 0 to 1 and nothing else.  Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip- flops less widely used in D = JQ’ + K’Q the design of digital systems are the JK and T flip-flops Characteristic Tables Characteristic Equations of j-k Characteristic Equations of D flip flop Characteristic Equations For the D flip-flop, we have the characteristic equation Q(t + 1) = D The characteristic equation for the JK flip-flop can be derived from the characteristic table or from the circuit of Fig. 5.12. We obtain Q(t + 1) = JQ’ + K’Q The characteristic equation for the T flip-flop is obtained from the circuit of Fig. 5.13 : Q(t + 1) = TꚚQ = TQ’ + T’Q  Direct Inputs Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state independently of the clock. The input that sets the flip-flop to 1 is called preset or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. When power is turned on in a digital system, the state of the flip-flops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation. A positive-edge-triggered D flip-flop with active-low asynchronous reset