Hardware Clock Distribution PDF

# Clock Distribution ## 11.6 Controlling Crosstalk on Clock Lines - Chapter 5 makes clear the relation of crosstalk to line separation. - Over a solid ground plane, doubling line separation divides crosstalk by 4. - Clocks being delicate signals, we favor extra crosstalk protection for them. - Ga...

# Clock Distribution ## 11.6 Controlling Crosstalk on Clock Lines - Chapter 5 makes clear the relation of crosstalk to line separation. - Over a solid ground plane, doubling line separation divides crosstalk by 4. - Clocks being delicate signals, we favor extra crosstalk protection for them. - Gaining extra crosstalk protection involves two aspects: - The physical means of providing more crosstalk protection - The logistical means of getting the correct physical result. ### 11.7 Delay Adjustments - The physical means of providing extra protection are simple: - Leave extra gaps around traces. - Put clock traces on separate layers encapsulated between ground planes. - The logistical means of providing extra protection are more complex. - One must first complete the error-prone task of identifying each clock trace by either hand-drawn marks on a schematic or a list of schematic net names. - The special routing requirements must then be communicated to your layout person. - The layout person then either accommodates your requests or ignores them. - Remember that you and the layout people rarely share the same boss. No offense is meant to layout professionals, but realistically, a layout person generally has more than enough to do without accommodating a long list of intricate special requests. - Because written instructions for routing clock traces on a separate, protected layer are compact and easily understood, many engineers use this approach. Wasting a routing layer is, in their estimation, worth the cost if it accomplishes their goal. - A more elegant approach sets up different trace separation specifications by net class. Nets classified as clock nets stay farther from other traces, creating less crosstalk. - Each year, more automatic routing packages incorporate this feature. - If your layout package does not support different net routing classes, it may only support different trace widths. - Designating all the clock nets as fat traces will force other traces away from the clock nets during routing. - After routing, globally change the clock nets to a narrower width. - A major disadvantage of this approach is that fat clock traces won't fit between the pins of an integrated circuit. - To enforce spacing requirements, some designers insert guard traces during layout only to remove them at the last minute. - Their temporary guard traces force other traces away from high-speed lines during routing, thus reducing crosstalk problems. ## 11.8 Differential Distribution - Differential clock signals survive tougher noise environments than single-ended clock signals. - This happens for two reasons: - Signal size - Differential balance. - Since the total voltage swing between the two wires of a differential pair is twice that of a single-ended signal, a differential pair can tolerate twice the interference. - Even better, if noise equally affects the two parts of a differential clock line, it cancels completely in the differential receiver, producing no net timing jitter. - Noise that affects both sides of a differential line equally is called common mode noise. - Differential lines tolerate enormous amounts of common mode noise. - Crosstalk problems are particularly acute in TTL systems that use an ECL clock distribution backbone. - The ECL distribution backbone distributes clock with low skew, which is an advantage. - The disadvantage of ECL clock distribution involves the low amplitude of ECL signals. - The larger-amplitude TTL signals easily generate enough crosstalk to interfere with nearby ECL clock receivers. - Differential ECL signaling helps overcome TTL crosstalk problems. - Differential signaling helps only if the interfering noise affects both signals equally. - It does not help with the kind of crosstalk induced between circuit traces which run too close together. - That crosstalk usually affects one line far more strongly than the other, creating a truly differential noise signal. - Differential signaling helps a lot when communicating between two circuit boards whose ground planes carry different noise voltages. - Differences in the ground voltages cancel out in the differential receiver. - Differential ECL signaling handily overcomes TTL ground noise between daughter cards on a large backplane. ## 11.9 Clock Signal Duty Cycle - The ideal duty cycle for a clock signal is 50%. - The falling edge of an idea clock signal precisely bisects successive rising edges. - This feature permits use of the inverted clock as an intermediate timing waveform. - The average DC value of an ideal clock lies halfway between the HI and LO states. - This property permits the design of simple feedback mechanisms which keep the duty cycle fixed at 50%, as we shall see. - The reason clocks become unbalanced, drifting away from 50% duty cycle, is that clock repeaters have an asymmetric response to rising and falling waveforms. - Careful measurements reveal that the propagation delay for any gate differs for rising and falling edges. - A pulse propagating through an asymmetric gate is either shortened or lengthened by this difference in propagation delay. - This effect is called pulse width compression, pulse width expansion, or pulse width distortion. - When we cascade a long series of identical gates, the pulse width distortion in each stage adds. - Suppose the input pulse is positive-going and the delay of rising edges exceeds the delay of falling edges. - Positive pulses will emerge shorter from each gate than from the gate before them. - Somewhere along the chain, the positive pulses simply disappear. - A clock signal traversing this same chain of gates looks like a train of pulses. - If, at each stage, a positive-going pulse shrinks, the duty cycle of the clock will drop as we progress along the chain. - At some point along the chain, the clock fails to elicit any response, and subsequent stages fall silent. - Two clever tricks have saved generations of engineers from the misfortune of losing a clock signal as a result of asymmetric propagation delays. - The first trick inverts the clock signal at every stage. - This alternately converts rising edges to falling ones, and vice versa, which prevents pulse width compression. - The second trick delays each signal edge by half of a clock period. - This ensures that the signals receive a minimum propagation delay of half a clock period. - The effect of pulse width compression is thus minimized. - These two methods ensure that clock signals propagate long distances using reasonable component delays. - They also preserve 50% duty cycle. - The trick for perfect cancellation of a crosstalk pulse is that it must return to the driver at the same time as the original signal, with opposite polarity. - Perfectly balanced lines are an absolute requirement for these strategies. - All lines must be equally long and identically terminated for this approach to be effective. - The second trick, using a source terminator, is a more effective option. - Source terminations are commonly used in high-speed systems. - Source terminations ensure that crosstalk is completely canceled across the entire transmission line, regardless of the line's length. ## 11.10 Canceling Capacitance of a Clock Repeater - When a new device connects to a multidrop bus, - The parasitic capacitance of its clock receiver shifts the received clock phase of all devices on the line. - Clocks received both downstream and upstream of the new device are affected. - The amount of shift induced is proportional to the total parasitic capacitance of the new clock receiver. - If you can reduce this capacitance by changing the layout, specifying a better receiver, or using another connector, then do so. - When faced with using the components at hand, try the circuit in Figure 11.16. - The inductor in Figure 11.16 presents a negative reactance at the clock frequency that partially cancels the parasitic capacitance of the clock receiver circuit. - RF engineers call this a matching network. - The inductor-cancellation trick works only at one frequency, the fundamental. - The third and higher harmonics present in the clock waveform get no relief from this technique. - When canceling a parasitic capacitance, use a clock driver with slow rise and fall times. - The resulting clock has less harmonic content (it looks more sinusoidal), and the neutralizing effect works better. - The two resistors are optional. - In a fixed installation, where the clock receiver is never disconnected from the line, the resistors add nothing to the circuit. - In a hot plugging environment, where cards are plugged into a bus with the power turned on and the clock running, the resistors provide a vital service. - They help charge capacitor C₁ before it connects to the clock bus. - When the card is powered off, - Capacitor C₁ is discharged to 0 V. - When the circuit is operating, - Capacitor C₁ is charged to the midpoint between HI and LO logic levels. - In the absence of R₁ and R2, when the card first connects to its clock bus, the surge of current required to charge capacitor C₁ will seriously distort clock signals on the bus. - This effect can be circumvented by a prepower arrangement. - A properly designed hot plugging card receives power connections before touching the clock bus. - Once power comes on, resistors R₁ and R2 precharge capacitor C₁ to the middle voltage, where it stays until contacting the clock bus. - This design feature prevents any sudden current surges from affecting the clock bus. ## 11.11 Decoupling Clock Receivers from the Clock Bus - In some situations, clock taps on a clock distribution bus may seriously distort the passing clock waveform. - This often happens when there are a lot of taps, when the clock receivers have too much parasitic capacitance, or when operating at high speeds. - One way to reduce the impact of each tap, at the expense of requiring more voltage gain in each clock receiver, is to build a 3:1 attenuator at the input to each clock gate. - Try inserting an impedance in series with each gate input that is twice the expected input impedance of the gate at the clock frequency. - The attenuating network may include a resistor in parallel with a capacitor. - For CMOS circuits, which draw little DC bias current, the attenuating network alone is sufficient. - TTL gates may require a DC biasing network in addition to the attenuating components. - The advantage of a 3:1 attenuating network is that it triples the apparent input impedance of the receiver. - The disadvantage is that the signal received by the gate is smaller. - Fortunately, most gates have a lot of excess voltage gain. - Common differential receiver circuits, having plenty of gain and a very precise input-switching threshold, work well as attenuated clock receivers. - When using ordinary gates (which have a very imprecise switching threshold) as attenuated clock receivers, better biasing is needed. - Try a DC bias network that senses its own output duty cycle and then adjusts the input-switching threshold to maintain 50%. ## Points to Remember - An inductor can partially cancel the parasitic capacitance of a clock receiver. - An attenuating network can increase the effective input impedance of a clock receiver.