EE2028_2410_Lecture 7_Interfacing Concepts and GPIO.pdf

7 : Interfacing Concepts and GPIO Ankit Srivastava [T]EE2028 Slides by Dr. Rajesh Panicker Some slides courtesy Dr. Gu Jing, NUS ECE Unless stated otherwise, for the second part of the module, ‘STM32 Chip’ = STM32L47...

7 : Interfacing Concepts and GPIO Ankit Srivastava [T]EE2028 Slides by Dr. Rajesh Panicker Some slides courtesy Dr. Gu Jing, NUS ECE Unless stated otherwise, for the second part of the module, ‘STM32 Chip’ = STM32L475VG ‘Board’ = B-L475E-IOT01A1 Generic Computer System RAM Keyboard/ USB Mouse Processor Core (MP) Another Ethernet computer Interrupt Controller HDMI Display System Timer Internal peripherals/ controllers Accelerometer Flash I2C BUS Gyroscope Motherboard/ SoC External Devices Protocol specific signals / (Not specifically STM32 Chip / Board) connections 2 Multi-tiered Bus Architecture RAM Other high speed SPI SD Card peripherals (eg. Processor Graphics/ Core (MP) HDMI) High speed – Flash low speed I2C Accelerometer bridge Protocol specific High Speed Bus Low Speed Bus signals / connections Motherboard/ SoC 3  STM32 Chip and Board (Partial) ◼ Core peripherals – from ARM, tightly integrated with Cortex M4 ◼ On-chip peripherals – from STM. Part of STM32 Chip ◼ External devices / peripherals – mostly from STM on the Board RAM GPIO Switch/ LED ARM Cortex M4 CPU USB-UART Bridge (to UART another computer) Interrupt Core Controller (NVIC) peripherals SPI WiFi System Timer On-chip peripherals Accelerometer Cortex M4 Core I2C Flash BUS Temp. Sensor External Devices Board STM32 Chip (on Board) 4 STM32 Chip and Board (Partial) LD1 LD2  Peripheral Registers ◼ Software interacts with the hardware by reading / writing peripheral registers ◼ Details of the registers and what happens when you write them / what you get when you read them can be found in the appropriate datasheet ◼ Broadly 3 categories – status, Peripheral 1 control and data registers 0x4800A0B0 ◼ Status registers - read by the 0x4800A0B4 Peripheral processor to know the status of registers the hardware Cortex M4 … (status, control, ◼ Control registers - written by the Processor data) processor to give commands / control signals ◼ Data registers - read (for input) and/or written (for output) to perform actual transfer of data Peripheral 2 Some functionalities could be … ◼ combined in some registers, AHB2 BUS e.g., control cum status registers ◼ Peripheral registers are accessed like memory – using LDR/STR equiv. 6  Info on Peripheral Registers: Datasheets Reference Manual for ARMv7-M Datasheet for STM32L4x5/6 Processor Series Datasheet for specific SoC: STM32l475vg User Manual for Board: B- L475E-IOT01A Datasheets of specific Devices on Board (self-exploration) Refer to Canvas > EE2028 > FIles > Labs > Data sheet 7  Abstractions for Accessing Peripheral Regs: C language, libraries / API / drivers ◼ Libraries (collection of driver functions for a peripheral / API) encapsulate / abstract the process of reading/writing peripheral registers ◼ Internally use pointers to peripheral registers (i.e., holding peripheral register addresses) to accomplish reading/writing, which are eventually implemented as LDR/STR instructions or equivalent ◼ Allow ease of programming (higher layer of abstraction – no need to reinvent the wheel) ◼ Portability – we just need to recompile / re-link with the new library, user program will need minimal/no changes ◼ CMSIS : functions for core peripherals (NVIC/interrupts, SysTick etc.) ◼ HAL : functions for on-chip peripherals (GPIO, I2C, SPI, UART etc.) ◼ BSP : functions for external devices/peripherals on the baseboard (accelerometer, temperature sensor etc.) 8  Accessing Peripheral Registers – MMIO vs PMIO ◼ Memory-mapped IO (MMIO) : the addresses for peripheral registers shares the address space with the memory ◼ LDR/STR (or pointers) used for IO ◼ Port-mapped IO (PMIO) : the memory and peripherals and are in separate address spaces ◼ Separate instructions (eg. IN/OUT in Intel 32) required for IO Memory MEMORYBUS Memory 2 locations can’t A memory location and I/O Processor Processor have same address device can have same address I/O BUS I/O I/O BUS 9  Parallel vs Serial Protocols ◼ Parallel protocols : use a number of parallel wires to transmit bits in parallel ◼ Processor-to-memory busses, old (pre-2005) protocols such as PCI, IDE, printer port, AXI, AXI-Stream ◼ Serial protocols : data is sent through a single wire, one bit at a time ◼ Serial ATA (SATA), PCIe, I2C, SPI, UART b7 b0 b7 Device 1 Device 2 Device 1 0 1...1 1 Device 2 b0 MSB First (Need not always be the case) Need not always be 8-bit Note: Data processing and storage (e.g. ALU, Registers, Memories) deal with data in a parallel manner even when data transfer is serial. This means serial protocols require a parallel-serial converter at the transmitter, serial-parallel converter at the receiver 10  Parallel Protocols : Bus Skew ◼ Parallel : used in high-speed, low distance ◼ Suffers from bus-skew : different signals travel at diff. speeds ◼ Suffers from cross-talk : signals from diff. wires interfere with each other b1 b2 b3 Data valid at receiver only in this interval 11  Synchronous vs Asynchronous Protocols ◼ Synchronous : one of the wires carry clock - allows transmitter and receiver to have a common time reference ◼ Faster, but suffers from the same issue as the parallel protocols (cross-talk, skew etc.) ◼ SPI, I2C, AXI, AXI- b0=0 b7=0 Stream.... Device 1 Data Device 2 Clock b7 b0.... Device Device 1 2 Clock b0=1 b7=1.... Device 1 Data Device 2 Clock.... Note: Clock need not always be generated by the transmitting device 12  Synchronous vs Asynchronous Protocols ◼ Asynchronous : only data is transmitted, not clock ◼ Receiver needs to recover timing info from data/control bits (start/stop etc.) – slower, complicated hardware ◼ UART, USB b7 b0 Device 1 Device 2 Edge detected – done every once in a while for synchronization – to figure out when to sample Other means of asynch transmissions, such as read-acknowledge … handshaking exist, but require more wires Sample half Sample every bit period bit interval later 13  Bus-based vs Point-to-point Protocols ◼ Bus : a number of devices are connected to the same set of wires (called a bus) – each device has a unique address ◼ I2C, SPI, USB, AXI ◼ Point-to-point : two devices have a dedicated link between them – no addressing ◼ UART, AXI-Stream Slave 1 Device 1 Device 2 Master Slave 2 Bus 14  Master-Slave vs Peer-to-peer Protocols ◼ Master-slave : only a master device can initiate communication, decides which slave should respond, and (in some synchronous protocols) generates the clock ◼ I2C, SPI, USB, AXI, AXI-Stream ◼ Peer-to-peer : any device can initiate communication ◼ Ethernet (configuration dependent) Peer 2 Slave 1 Peer 1 Master Slave 2 Peer 3 Bus Bus 15  Simplex vs Half Duplex vs Full Duplex Protocols ◼ Simplex : single, unidirectional link, one-way interaction ◼ GPIO Output to LEDs / Input from switches, AXI-Stream ◼ Half-duplex : one bi-directional link, devices take turns ◼ I2C, USB 2.0 ◼ Full-duplex : at least two links, can transmit and receive at the same time Simplex ◼ SPI, UART, USB 3.x Device 1 Device 2 Half Duplex Device 1 Device 2 Full Duplex Device 1 Device 2 16  Addressing : In-band vs Out-of-band Protocols ◼ In-band : address of the device being accessed (to select the device), as well as the data (read from or written to the device) are sent through the same bus ◼ I2C, USB ◼ Out-of-band : separate address bus, a decoder enables (activates) the device ◼ SPI Peripheral 1 Peripheral 1 EN Same bus for Master Master Address, Data Peripheral 2 Peripheral 2 EN Address Address Data Bus Bus Decoder Bus 17 GPIO  GPIO Introduction ◼ STM32L475VG has 100 I/O lines, organized into ports and pins ◼ General Purpose Input-Output (GPIO) ports are named GPIOA to GPIOI (user programmable: up to GPIOH), with up to 16 I/O pins per port (not all pins are implemented – depends on the specific SoC) ◼ Directly connection to AHB2 bus allows fast I/O timing ◼ Each pin of the GPIO ports can be individually configured by software in several modes and directions: Input / Output / Analog / Alternative function (AF) ◼ The number of physical pins are kept low by multiplexing different functions on a particular pin. Helps keep the chip cost low ◼ Possible mutual exclusivity of functions, but typical applications need only a small subset of the various interfaces/peripherals available on an SoC ◼ GPIO interface is used for GPIO input/output and also all other embedded(on-chip) peripherals to interface with both digital and analog signals ◼ GPIO lines are configurable through GPIO registers, which have to be accessed as 32-bit words, half-words or bytes 19  GPIO in STM32L475VG ◼ STM32L475xx block diagram (incomplete) 20  GPIO Registers in STM32L475VG STM32L475xx devices peripheral register boundary addresses Memory map for STM32L475xx devices Ref. to RM0351_STM32L4x5 MCUs Ref Manual, Pg75-77 21  GPIO Registers in STM32L475VG Register Type Register Name (where x = A to H) Read-Write Mode register GPIOx_MODER RW Output type register GPIOx_OTYPER RW Output speed register GPIOx_OSPEEDR RW Pull-up / Pull-down register GPIOx_PUPDR RW Control Configuration lock register GPIOx_LCKR RW Alternate function low register GPIOx_AFRL RW Alternate function high register GPIOx_AFRH RW Analog switch control register GPIOx_ASCR RW Input data register GPIOx_IDR RO Output data register GPIOx_ODR RW Data Bit reset register GPIOx_BRR WO Bit set/reset register GPIOx_BSRR WO 22  GPIO Control Registers: MODER, AFR, OTYPER, PUPDR STM32 Chip Board BUS MODER 0x00 REG_1 PUPDR AFR 0x01 REG_2 OTYPER ….… P yyy SENSOR I2C_CR1 U N SDA.. I2C_ISR P 0x20 CTRL_REG1 ARM I2C_TXDR D N Cortex.. 0x2A TEMP_OUT_L I2C_RXDR M4 Core P 0x2B TEMP_OUT_H … U N I2C INTERFACE SCL ….. P D HTS221 N From other interfaces.. such as SPI, UART etc. IDR P U N NVIC INT EXTI P ODR D N. GPIO BLOCK to analog 23  GPIO Control Register: GPIOx_MODER ◼ MODER (Address Offset = 0x00) : Mode Register : First level of multiplexing ◼ GPIOx_MODER bits MODEy[1:0] configures the mode of pin y (y=15:0) of port x (x = A, B, C, D, E, F, G, H) to be ◼ 00: Input mode ◼ 01: General purpose output mode ◼ 10: Alternate function (AF) mode ◼ 11: Analog mode (reset state) ◼ 2 bits per pin -> 1 MODER register needed per port [port = up to 16 pins] ◼ E.g. To configure Port B Pin 14 as GPIO output (x=B, y=14): MODE14[1:0] of GPIOB_MODER, i.e., GPIOB_MODER [29:28] = 01 GPIOB_MODER address = AHB2 base (0x48000000) + GPIOB offset (1 KB = 0x400) + MODER offset (0x00) = 0x48000400 GPIOB starting address 24  GPIO Control Register: GPIOx_AFRL/H ◼ AFRL/H (Address Offset = 0x20/0x24) : Alternate Function Low/ High Registers : Second level multiplexing : Choosing which of the 16 internal peripherals/interfaces a pin is connected to, when GPIOx_MODER bits = 10 (alternate function) ◼ GPIOx_AFRL/H bits AFSELy[3:0]: Alternate function selection for port x pin y (y = 7:0 for AFRL; y = 15:8 for AFRH) GPIOx_AFRL ◼ 0000: AF0 ◼ 0001: AF1 ◼ 0010: AF2 GPIOx_AFRH ◼.... ◼ 1111: AF15 ◼ Since there are 16 alternate functions per pin, 4 AFSEL bits are required per pin. Hence, 2 AFR registers (AFRL and AFRH) per port ◼ E.g., To configure Port C Pin 12 as UART5_TX (x=C, y=12): AFSEL12[3:0] of GPIOC_AFRH, i.e., GPIOC_AFRH[19:16] = 4’b1000 (UART5_TX is AF8) Ref. to DS10969Rev5_STM32L475xx Data-sheet, Table 18 (pg.77) 25  GPIO Control Register: GPIOx_PUPDR ◼ PUPDR (Address Offset = 0x0C) : Pull-up/pull-down register: Selects whether an internal pull-up / pull-down resistor is connected to a pin ◼ GPIOx_PUPDR bits PUPDy[1:0] configures pull-up/down setting of port x pin y (y=15:0) VDD Chip ◼ 00: No pull-up, pull-down : Used when the pin is not an input, or when we do not wish to set a default value to input Pull-up When we are confident that the external device will drive a Device strong LOW or HIGH and won’t be floating GPIO ◼ 01: Pull-up : Sets the default input to HIGH. Used when the. Input pin is an input which could be floating (unconnected / not driven actively by the external device at times) VDD Chip The default HIGH is overridden by the strong LOW driven by VDD the external device GPIO 10: Pull-down : Similar to above, but sets the default input to Input ◼ LOW Device ◼ 11: Reserved – do not write 11 to PUPD bits Pull-down ◼ 2 bits per pin -> 1 PUPDR register needed per port. 26  GPIO Control Register: GPIOx_OTYPER ◼ OTYPER (Address Offset = 0x04) : Output Type Register ◼ GPIOx_OTYPER bits OTy configures OTYPE of port x pin y (y=15:0) 0: Output push-pull (reset state) : Output is 1: Output open-drain : Output is either a either a strong HIGH or a strong LOW. strong LOW or High-impedance (Z, also Cannot connect multiple outputs together called floating, weak HIGH etc.) PUN is disconnected. Pull-up Network (PUN = PMOS) Allows multiple outputs to be connected together to one bus. Pull-down Network Writing a logic 1 (weak (PDN = NMOS) HIGH) = disconnected from bus ◼ 1 bit per pin -> 1 OTYPER register needed per port, with 16 bits unused (= reserved = must be kept at reset level) ◼ E.g. To configure Port B Pin 14 as Output push-pull (x=B, y=14): OT14 of GPIOB_OTYPER, i.e., GPIOB_OTYPER = 0 27  Open-drain : Interfacing ◼ Open-drain mode can be used to interface between logic families using different voltage levels 5V 3.3V 5V Device Device Pin in open- drain mode 3.3V 3.3V 5V Device Device Pin in open- drain mode 28  Open-drain : Bi-directional Communication ◼ Open-drain mode allows bi-directional communication between multiple devices using a single wire STM32 internal pull- Vcc up can be used! Z Z O/P I/P O/P I/P O/P I/P Can be multicast Dev 1 Vcc Dev 3 (one device sends, more than one receives)! Z Z O/P I/P O/P I/P O/P I/P Dev 1 Dev 3 29  GPIO Data Regsiters ◼ When a pin is in GPIO input mode (MODE=00), the logic level of a pin can be read from the corresponding bit in the input data register (IDR) ◼ When a pin is in GPIO output mode (MODE=01), the logic level of a pin will be controlled/determined by the value of the corresponding bit in the output data register (ODR) ◼ ODR bits can also be manipulated indirectly through bit set/reset register (BSRR) and bit reset register (BRR) which are logical interfaces/means to affect the physical register ODR ◼ Use of BSRR and BRR allows certain pins to be modified in one action (atomic), without the need to read ODR -> modify the relevant bits -> write back to ODR  GPIOx_IDR and GPIOx_ODR ◼ GPIOx_IDR (Address offset = 0x10) : Input Data Register. It is read-only ◼ GPIOx_IDR IDy contains the logic level read from port x pin y (y=15:0). Bits 31:16 of this register is reserved ◼ E.g. To know the input level at Port C Pin 13 (x=C, y=13): check bit value at GPIOC_IDR ◼ GPIOx_ODR (Address offset = 0x14) : Output Data Register ◼ GPIOx_ODR ODy contains the logic level output on port x pin y (y=15:0). Bits 31:16 of this register is reserved ◼ E.g., To output 1 from Port B Pin 14 (x=B, y=14): Set GPIOB_ODR = 1 and keep the other bits unchanged ◼ ODR is read-write. We can read back and verify the output when the pin is a GPIO output. Reading ODR will not give the pin logic level in GPIO input mode  Set = make a bit 1 GPIOx_BRR and GPIOx_BSRR Reset = make a bit 0 ◼ GPIOx_BRR (Address offset = 0x28) : Bit Reset Register ◼ GPIOx_BRR BRy, for port x pin y (y = 15:0) works as below. There bits are write-only, a read to these bits returns the value 0x0000. Bits 31:16 of this register is reserved ◼ 0: no action on the corresponding ODy bit ◼ 1: Resets the corresponding ODy bit ◼ GPIOx_BSRR (Address offset = 0x18) : Bit Set/Reset Register. It is write-only ◼ GPIOx_BSRR BSy, for port x pin y (y = 15:0) works as below ◼ 0: no action on the corresponding ODy bit ◼ 1: Sets the corresponding ODy bit ◼ GPIOx_BSRR BRy, for port x pin y (y = 15:0) works as below ◼ 0: no action on the corresponding ODy bit BRy of BSRR is intended to be ◼ 1: Resets the corresponding ODy bit used only when there is a need to set some pins and reset some If both BSy and BRy are set in BSRR, BSy has priority other pins at the same instant GPIOx_BSRR and GPIOx_ODR GPIOx_BSRR 1 1 1 1 GPIOx_ODR 1 0 1  GPIO Supporting Functions in HAL Library ◼ Header File: Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h ◼ Contains declarations of constants, structures, functions etc used for GPIO peripheral ◼ Source File: Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c ◼ Contains the definitions of GPIO functions  GPIO Supporting Functions in HAL Library ◼ Example: use HAL_GPIO_WritePin() to output 1 from Port B Pin 14: ◼ Assume the GPIO pin has already been configured as Output (by Mode Register) ◼ User program: HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); Blink Program by CMSIS and HAL libraries ◼ Example project: Blink_by_HAL (on the Canvas) Interpreting Sensor Output  Interpreting Sensor Output ◼ The raw value given by a sensor typically does not represent the magnitude of the physical quantity directly ◼ magnitude = f(value) where f is a conversion function which is often, but not necessarily, linear ◼ Many sensors give 16-bit values as two separate bytes, as the protocols (e.g., I2C) may deal with data only in chunks of 8 bits ◼ Concatenate value_LSB B7 B6 B5 B4 B3 B2 B1 B0 the bytes value_MSB B15 B14 B13 B12 B11 B10 B9 B8 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 value = B15 B14 B13 B12 B11 B10 B9 B8 0 0 0 0 0 0 0 0 ((uint16_t)value_MSB