EIE202 Electronic Circuits Laboratory Manual (Aug 2024) PDF

School of Electrical & Electronics Engineering EIE202 ELECTRONIC CIRCUITS LABORATORY MANUAL (For II Year / III Semester) 1  EIE202 -Electronic Circuits Laboratory (Com...

School of Electrical & Electronics Engineering EIE202 ELECTRONIC CIRCUITS LABORATORY MANUAL (For II Year / III Semester) 1  EIE202 -Electronic Circuits Laboratory (Common to EIEand ECE) COURSE OBJECTIVE  To facilitate the learners to experimentally analyse the V - I characteristics of various active devices  To enable the learners to design electronic circuits for the given frequency response specifications LIST OF EXPERIMENTS 1. Design of emitter feedback, collector feedback and voltage divider bias using BJT 2. Frequency response characteristics of two stage RC coupled amplifier using BJT 3. Frequency response of CC amplifier 4. BJT, FET, MOSFET and CMOS as a switch 5. Design of common source FET amplifier for a given gain and plot the frequency response 6. Design of current amplifier using Darlington pair 7. Frequency response of current series amplifier (with and without feedback) 8. Design of Hartley / Colpitts oscillator 9. Study the characteristics of UJT and design a relaxation oscillator using UJT 10. Design of astable multivibrator using transistor 11. Frequency response characteristics of complementary symmetry push-pull amplifier 12. Frequency response characteristics of single tuned amplifier LABORATORY LEARNING OUTCOMES Upon successful completion of this course, learners will be able to:  Design voltage and current amplifiers for a given gain and bandwidth  Construct systems that can generate various test signals for characteristic study  Demonstrate the use of frequency response study in designing amplifiers EIE202 – Electronic Circuits Lab 2 Exp. No: 01 Date: DEIGN OF EMITTER FEEDBACK, COLLECTOR FEEDBACK AND VOLTAGE DIVIDER BIAS USING BJT AIM: To design a Emitter feedback, Collector feedback and Voltage divider bias using BJT for a given IC = ____________ (mA) and VCE = _____________(V) APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: Emitter feedback bias EIE202 – Electronic Circuits Lab 3 DESIGN: Emitter feedback bias: By Applying KVL to base and emitter loop, VCC  I B RB VBE I E RE  0 , where IC   I B and I E     1 I B Let, R e  200 By Applying KVL to collector and emitter loop,find Rc VCC  IC RC VCE  I C RE  0 VCC  VCE  IC RE Rc   IC Collector feedbackbias: By Applying KVL to collector and emitter loop, VCC  IC RC VCE  0 VCC  VCE RC   IC By Applying KVL to base and emitter loop,find Rb VCC (IC  I B )RC  I B RB VBE  0 ; IC   I B EIE202 – Electronic Circuits Lab 4  VCC  VBE  RC (   1) I B RB   IB Voltage divider bias: Given: VCC Assume, VE  10 VCC Assume, VE  10 VE  I E  RE = I E     1 I B = VE RE   IE Vth  VE  VBE R2  RE Vth  VCC  let, R2   R1  R2 10 EIE202 – Electronic Circuits Lab 5 R1  VCE  I C RC  VE  VCC ; VCC  VCE  VE RC   IC PROCEDURE: 1. For the given IC and VCE, calculate the value of the various resistors. 2. Connect the circuit in the bread board and verify the practical value of IC and VCE with the given value. RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 6 Exp. No: 02 Date: FREQUENCY RESPONSE CHARACTERISTICS OF TWO STAGE RC COUPLED AMPLIFIER USING BJT AIM: To obtain the Frequency response characteristics of two stage RC coupled amplifier using BJT APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: EIE202 – Electronic Circuits Lab 7 DESIGN: Design of RE and RC: 1 4 Let VRE  VCC and VRC  VCC 10 10 V  RC  0.4  CC   IC  V  RE  0.1 CC   IC  Design of R1 and R2: Current through R1 , I1  10I b VR 2  VBE  VRE VR1  VCC  VR 2 VR1 R1   I R1 VR 2 R2   I R1 Design ofCe: 1 Let, X ce  Re 10 1 1 X ce  & Ce   2 f Ce 2 f X ce Design of Cin: 1 X cin  Rin 10 26 mV re  IE Rin  R1  R2  (1  h fe re ) Let, f= 1000 Hz EIE202 – Electronic Circuits Lab 8 Therefore, 1 Cin   2 f X cin Design of Cout: 1 X cout  Rout 10 Where, RC  Rout 1 Cout   2 f X cout MODEL GRAPH: PROCEDURE: 1. Construct the circuit as shown in the figure for single stage amplifier. 2. Set the input sine wave value in the millvolts range using AFO 3. Vary the frequency from the AFO and note the output Vo in the CRO. 4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the lower and upper cutoff frequency by drawing the 3db line 6. Repeat the procedure for two stage amplifier. 7. Calculate the band width of single stage& two stage RC coupled amplifier. EIE202 – Electronic Circuits Lab 9  TABULATION: Vin  Sl. Output Voltage V0 Gain (dB) Frequency Gain ( A  ) No. (V0) Vin 20log( Av ) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 10 Exp. No: 03 Date: FREQUENCY RESPONSE OF CC AMPLIFIER AIM: To obtain the frequency response of Common Collectoramplifier. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: EIE202 – Electronic Circuits Lab 11 DESIGN: Design of RE: 1 Let VRE  VCC 10 V  RE  0.1 CC   IC  Design of R1 and R2: Current through R1 , I1  10I b VR 2  VBE  VRE VR1  VCC  VR 2 VR1 R1   I R1 VR 2 R2   I R1 MODEL GRAPH: EIE202 – Electronic Circuits Lab 12 PROCEDURE: 1. Give the connections as per the circuit diagram. 2. Set the magnitude of the input waveform to 0.4 V (Peak to Peak). 3. Vary the frequency from the signal generator and note the corresponding magnitude of the output voltage from the CRO. 4. Calculate the gain using the formula A = Vo/Vin 5. Plot the frequency response (Gain Vs Frequency) in the semi log sheet. TABULATION: Vin  Sl. Output Voltage V0 Gain (dB) Frequency Gain ( A  ) No. (V0) Vin 20log( Av ) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 13 Exp. No: 04 Date: TRANSISTOR, FET, MOSFET& CMOS AS A SWITCH AIM: To construct and verify the working of transistor, FET, MOSFET &CMOS as a switch. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: Transistor as a switch: EIE202 – Electronic Circuits Lab 14 FET as a switch: MOSFET as a switch: EIE202 – Electronic Circuits Lab 15 CMOS as a switch: MODE: GRAPH: PROCEDURE: 1. Make the connections as shown in the figure. 2. Provide square wave input of 1.5 V and observe the output at thecollector terminal for BJT. 3. Provide square wave input of 5 V at the drain terminal for FET and similarly for MOSFET. 4. Similarly carry out for CMOS. 5. Draw the input and output waveforms in the graph. TABULATION: Transistor as a Switch: Divisions in X Total Divisions Total Time/div Volt/div axis time in Y axis Voltage Input Output EIE202 – Electronic Circuits Lab 16 FET as a Switch: Divisions in X Total Divisions Total Time/div Volt/div axis time in Y axis Voltage Input Output MOSFET as a Switch: Divisions in X Total Divisions Total Time/div Volt/div axis time in Y axis Voltage Input Output CMOS as a Switch: Divisions in X Total Divisions Total Time/div Volt/div axis time in Y axis Voltage Input Output RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 17 Exp. No: 05 Date: DESIGN OF COMMON SOURCE FET AMPLIFIER AIM: To design common source FET amplifier for a given gain and to plot the frequency response. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: EIE202 – Electronic Circuits Lab 18 DESIGN: MODEL GRAPH: PROCEDURE: 1. Construct the circuit as shown in the circuit diagram. 2. Set the input sine wave value in the millvolts range using AFO 3. Vary the frequency from the AFO and note the output VO in the CRO. EIE202 – Electronic Circuits Lab 19  4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the lower and upper cutoff frequency by drawing the 3db line 6. Calculate the band width. TABULATION: Vin  Sl. Output Voltage V0 Gain (dB) Frequency Gain ( A  ) No. (V0) Vin 20log( Av ) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 20 Exp. No: 06 Date: DESIGN OF CURRENT AMPLIFIER USING DARLINGTON PAIR AIM: To design current amplifier using Darlington pair and to calculate the gain. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: EIE202 – Electronic Circuits Lab 21 DESIGN: MODEL GRAPH: PROCEDURE: 1. Construct the circuit as shown in the circuit diagram. 2. Set the input sine wave value in the millvolts range using AFO 3. Vary the frequency from the AFO and note the output Vo in the CRO. 4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the lower and upper cutoff frequency by drawing the 3db line 6. Calculate the band width. EIE202 – Electronic Circuits Lab 22 TABULATION: Vin  Sl. Output Voltage V0 Gain (dB) Frequency Gain ( A  ) No. (V0) Vin 20log( Av ) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 23 EX NO: 7 DATE: FREQUENCY RESPONSE OF CURRENT SERIES AMPLIFIER AIM: i. To construct and draw the frequency response of current series amplifier using BJT. ii. To find the bandwidth with and without feedback APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: VCC RC R1 COUT VOUT C1 VIN R2 RE CE EIE202 – Electronic Circuits Lab 24 DESIGN: The nominal value of collector current Ic and hfe (β) can be obtained from the datasheet of the transistor. Design of RE and RC : Let VRE = 10 % VCC Voltage across VRC = 40 % VCC V  V  RC  0.4  CC  and RE  0.1 CC   IC   IC  Design of R1 and R2 : Base Current IB = IC/ β.Current through R1 is IR1 = 10 IB VR2 = VBE +VRE VR1= VCC - VR2 VR1 V R1  and R2  R 2 I R1 I R1 Design of CE: Impedance of emitter bypass capacitor should be 1/10th of RE 1 1 X ce  & Ce  2 f Ce 2 f X ce Design of Cin: Xcin  110 Rin re  26mV IE Rin  R1  R2  (1  h fe re ) EIE202 – Electronic Circuits Lab 25 Therfore, 1 Cin  2 f Xcin Design of Cout: Xcout  110 Rout And Rc= Rout 1 Cout  2 f Xcout Calculation of gain: MODEL GRAPH: PROCEDURE: 1. Construct the circuit as shown in the circuit diagram. 2. Set the input value in millvolts range using AFO 3. Vary the frequency using the AFO and notedown the output voltage Vo in CRO. EIE202 – Electronic Circuits Lab 26 4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the lower and upper cutoff frequency by drawing the 3db line 6. From these two frequencies calculate the band width of the amplifier. This gives the bandwidth without feedback. 7. Remove the by pass capacitor CE and repeat the procedure from step 2 till step 5. 8. Calculate the band width. This gives the bandwidth with feedback. TABULATION: Without feedback (Presence of capacitor Ce) Vin = Output voltage (Vo) in Gain Gain in dB Frequency in Hz S.No Volts (A=Vo/Vin) 20 log(A) EIE202 – Electronic Circuits Lab 27  With feedback (Absence of capacitor Ce) Vin = Output voltage (Vo) in Gain Gain in dB Frequency in Hz S.No Volts (A=Vo/Vin) 20 log(A) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 28  Exp. No.8 DATE: DESIGN OF HARTLEY / COLPITTS OSCILLATOR Aim: To design Hartley and Colpitts oscillator APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM (Colpitts Oscillator) VCC RC R1 COUT VOUT CIN R2 RE CE C1 C2 L EIE202 – Electronic Circuits Lab 29  The resonant frequency is given by 1 = 2 Where ƒ is the resonant frequency = + HARTLEY OSCILLATOR VCC R1 RC C1 VOUT R2 RE CE L1 L2 C The frequency of oscillations in this circuit is fo = 1/ (2π √ (Leq C)) EIE202 – Electronic Circuits Lab 30  Where Leq is the total inductance of coils in the tank circuit is given as Leq = L1 + L2 Procedure: 1. Make the connections as per the circuit diagram. 2. Set VCC to 12 Volts. 3. Observe the output and measure the time period of the output waveform Vo 4. determine the frequency and trace it 5. Plot the output on a graph sheet. 6. Compare the experimental value with the theoretical value of output frequency Tabulation: Type of Calculated Amplitude Time Period Frequency Oscillator Frequency (In Volts) (In ms) Obtained Hartley Oscillator Colpitts Oscillator MODEL GRAPH: EIE202 – Electronic Circuits Lab 31  RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 32  Exp.9 DATE: STUDY THE CHARACTERISTICS OF UJT AND DESIGN A RELAXATION OSCILLATOR USING UJT Aim: To study the charateristics of UJT and its working as relaxation oscillator. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM: EIE202 – Electronic Circuits Lab 33  MODEL GRAPH: TABULATION: Voltage between B1 & B2 (VB2B1 = 2V ) Voltage between B1 & B2 (VB2B1 = 3V ) VEB(V) IE(mA) VEB(V) IE(mA) PROCEDURE: 1. Give the connections as per the circuit diagram. 2. For fixed VB1B2. Vary VEB and notedown the corresponding IE value and tabulate. 3. Draw the graph. EIE202 – Electronic Circuits Lab 34  CIRCUIT DIAGRAM: {UJT RELAXATION OSCILLATOR} VCC R2 R C R1 MODEL GRAPH: DESIGN Given f o  T  1f  o  1  T  R C ln    1   R1  R1  R2 PROCEDURE: 1. Give the connections as per the circuit diagram. 2. Switch ON the supply and observe the output across the capacitor in the CRO. EIE202 – Electronic Circuits Lab 35  3. Note the valley point Vv, peak point Vp, time period for one cycle and the shift. Calculate the frequency. 4. Draw the graph. TABULATION: No.of divisions Time/div Total time No.of divisions Volt/div Total in the X axis period(ms) in the Y axis voltage(V) Output RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 36 EXP.NO. 10 DATE: DESIGN OF ASTABLE MULTIVIBRATOR USING TRANSISTOR Aim: To design and construct astable multivibrator using transistor. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM VCC R1 R2 RC1 RC2 C1 C2 BC107 BC107 EIE202 – Electronic Circuits Lab 37 Theory: The Astable circuit has two quasi-stable states. Without external triggering signal the Astable configuration will make successive transitions from one quasi-stable state to the other. The Astable circuit is an oscillator. It is also called as free running multivibrator and is used to generate “Square Wave”. Since it does not require triggering signal, fast switching is possible. Operation: When the power is applied, due to some imbalance in the circuit, the transistor Q2 conducts more than Q1 i.e. current flowing through transistor Q2 is more than the current flowing in transistor Q1. The voltage VC2 drops. This drop is coupled by the capacitor C1 to the base by Q1 there by reducing its forward base-emitter voltage and causing Q1 to conduct less. As the current through Q1 decreases, VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2. There by increasing its base- emitter forward bias. This Q2 conducts more and more and Q1 conducts less and less, each action reinforcing the other. Ultimately Q2 gets saturated and becomes fully ON and Q1 becomes OFF. During this time C1 has been charging towards VCC exponentially with a time constant T1 = R1C1. The polarity of C1 should be such that it should supply voltage to the base of Q1. When C1 gains sufficient voltage, it drives Q1 ON. Then VC1 decreases and makes Q2 OFF. VC2 increases and makes Q1 fully saturated. During this time C2 has been charging through VCC, R2, C2 and Q2 with a time constant T2 = R2C2. The polarity of C2 should be such that it should supply voltage to the base of Q2. When C2 gains sufficient voltage, it drives Q2 On, and the process repeats. DESIGN: The period T is given by T = T1 + T2 = 0.69 (R1C1 + R2C2) For symmetrical circuit, with R1 = R2 = R & C1 = C2 = C T = 1.38 RC Let VCC = 12V; hfe = 51 (for BC107), VBESat = 0.7V; VCESat = 0.3V Let C = 0.1 F & T = 1mSec. 10-3 = 1.38 x R X 0.1 X 10-6 R = 7.24K (Practically choose 10K ) i.e., R1 and R2 resistors. Let ICmax=10mA RC = = 1.17K ( 1K is selected for Rc1 and Rc2) EIE202 – Electronic Circuits Lab 38 Procedure: 1. Make then connections as per the circuit diagram. 2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and measure the frequency (f = 1/T). 3. Trace the waveforms at collector and base as each transistor with the help of dual trace CRO and plot the waveforms. 4. Verify the practical output frequency with theoretical values f = 1/T, where T = 1.38 RC MODEL GRAPH: EIE202 – Electronic Circuits Lab 39 Theoretical calculations: F = 1/ T = (1/1.38RC) R = 10K C = 0.1 F RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 40 EXP.NO.11 DATE: FREQUENCY RESPONSE CHARACTERISTICS OF COMPLEMENTARY SYMMETRY PUSH-PULL AMPLIFIER Aim: To plot the frequency response characteristics of complementary push-pull amplifier. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIARAM VCC R1 R C1 VOUT VIN RL C2 R2 R EIE202 – Electronic Circuits Lab 41 DESIGN: Choose any value for R1 and R2 such that the transistors are properly biased Let R1 = R2 MODEL GRAPH PROCEDURE: 1. Construct the circuit as shown in the Fig. 2. Set the input voltage using AFO 3. Vary the frequency using AFO and note the output across RLin the CRO. 4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the lower and upper cutoff frequency by drawing the 3db line 6. From these two frequencies calculate the band width. EIE202 – Electronic Circuits Lab 42  TABULATION Vin = Amplitude of Frequency the output Gain Gain in db S.No in Hz voltage (A=Vo/Vin) 20log(A) (Vo) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 43 EXP. NO.12 DATE: FREQUENCY RESPONSE CHARACTERISTICS OF SINGLE TUNED AMPLIFIER Aim: To plot the frequency response charateristics of single tuned amplifier. APPARATUS REQUIRED: Sl. No Component/Equipment Range Quantity CIRCUIT DIAGRAM VCC L C R1 COUT VOUT CIN VIN R2 RE CE EIE202 – Electronic Circuits Lab 44 DESIGN: R1, R2, RE, CE, CIN AND COUT SHALL BE THE SAME AS USED IN BIASING fr = 1/ 2π√LC , fr = 7KHz Let C=.001µF, then L = 1/((2  fr)^2*C) L = 1/((2*3.14*7*10^3)^2*0.001*10^-6) L = 516mH MODEL GRAPH: PROCEDURE: 1. Construct the circuit as shown in the Fig. 2. Set the input value in the millvolts range using AFO 3. Vary the frequency using the AFO and note the output Vo in the CRO. 4. By taking the frequency in X-axis and gain in Y-axis draw the graph. 5. Note the center frequency fo and calculate the quality factor. EIE202 – Electronic Circuits Lab 45 TABULATION: Vin = Amplitude of Frequency the output Gain Gain in dB S.No in Hz voltage (A=Vo/Vin) 20log(A) (Vo) RESULT: INFERENCE: EIE202 – Electronic Circuits Lab 46 EIE202 – Electronic Circuits Lab 47