STM32 Core Peripherals PDF

STM32 Core Peripherals TABLE OF CONTENTS 01 02 03 Core Periphals RCC SYSTICK Overview 01 Core Peripherals Overview  Core Peripherals Main core peripherals: RCC: Manages system clocks, resets, and peripheral clock control. NVIC: Manages Interrupt priorit...

STM32 Core Peripherals TABLE OF CONTENTS 01 02 03 Core Periphals RCC SYSTICK Overview 01 Core Peripherals Overview  Core Peripherals Main core peripherals: RCC: Manages system clocks, resets, and peripheral clock control. NVIC: Manages Interrupt prioritization and handling SYSTICK: 24-bit system timer for interrupts and timing control. SCB: Manages system-level control. Exceptions and power modes. DMA: Accessing memory directly independent of the processor WWDG: Window-based watchdog. IWDG: Independent watchdog. TABLE OF CONTENTS 01 02 03 Core Periphals RCC SYSTICK Overview 02 RCC  RCC Reset & Clock control  RCC Reset 1- System reset 2- Power reset 3- Backup domain reset  RCC 1- System reset 1- External reset (NRST pin) 2- WWDG & IWDG end of count condition 3- Software reset (enabled in SCB) 4- Low-power management reset  RCC Low-power management reset 1- Reset on entering standby mode 2- Reset on entering stop mode Enabled by resetting nRST_STDBY & nRST_STOP bits in User Option Bytes  RCC Low-power management reset Enabled by resetting nRST_STDBY & nRST_STOP bits in User Option Bytes  RCC Reset 1- System reset 2- Power reset 3- Backup domain reset  RCC 2- Power reset sets all registers to their reset values except the Backup domain register 1- Power-on/power-down reset (POR/PDR reset) 2- When exiting Standby mode  RCC Reset 1- System reset 2- Power reset 3- Backup domain reset  RCC 3- Backup domain reset Backup domain?  RCC 3- Backup domain reset 1- Software reset, triggered by setting the BDRST bit in RCC_BDCR 2- VDD (main power supply pin) or VBAT (backup power supply pin) power on  RCC Reset Circuit  RCC Reset & Clock control  RCC Clock 1- HSI oscillator clock 2- HSE oscillator clock 3- PLL clock 4- 40 kHz low speed internal RC (LSI) 5- 32.768 kHz low speed external crystal (LSE)  RCC 1- HSI oscillator clock 8 MHz RC internal oscillator Used directly as system clock PLL input after division by 2 Faster, lower cost Frequency is less accurate  RCC Clock 1- HSI oscillator clock 2- HSE oscillator clock 3- PLL clock 4- 40 kHz low speed internal RC (LSI) 5- 32.768 kHz low speed external crystal (LSE)  RCC 2- HSE oscillator clock 2 Modes External source (HSE bypass) up to 50 MHz External crystal/ceramic resonator (HSE crystal) 3 to 25 MHz Very accurate Slower startup  RCC Clock 1- HSI oscillator clock 2- HSE oscillator clock 3- PLL clock 4- 40 kHz low speed internal RC (LSI) 5- 32.768 kHz low speed external crystal (LSE)  RCC 3- PLL clock HSI clock divided by 2 HSE Frequency multiplication  RCC Clock 1- HSI oscillator clock 2- HSE oscillator clock 3- PLL clock 4- 40 kHz low speed internal RC (LSI) 5- 32.768 kHz low speed external crystal (LSE) RCC  RCC System clock (SYSCLK) 1- HSI oscillator is selected 2- If another clock is selected, wait for ready flag 3- Ready flag from status bits in RCC_CR  RCC registers Clock control register (RCC_CR)  RCC registers Clock configuration register (RCC_CFGR)  RCC registers Clock interrupt register (RCC_CIR)  RCC registers Control/status register (RCC_CSR)  RCC registers Backup domain control register (RCC_BDCR) TABLE OF CONTENTS 01 02 03 Core Periphals RCC SYSTICK Overview 03 SYSTICK  SYSTICK 24-bit register  SYSTICK 24-bit register  SYSTICK 24-bit register Clock source: AHB/8 (9 MHZ) Processor Clock (AHB) (72 MHZ)  SYSTICK Registers SysTick control and status register (STK_CTRL) Privileged  SysTick control and status register (STK_CTRL) Enable (Bit 0) TICKINT (Bit 1) CLKSOURCE (Bit 2) COUNTFLAG (Bit 16)  SysTick control and status register (STK_CTRL) Cube IDE  SysTick control and status register (STK_CTRL) Cube IDE  SysTick control and status register (STK_CTRL) Cube IDE  SysTick control and status register (STK_CTRL) Cube IDE SysTick->CTRL  SYSTICK Registers SysTick reload value register (STK_LOAD) Privileged  SysTick reload value register (STK_LOAD) RELOAD (Counter reload value, Bits 23:0)  SysTick reload value register (STK_LOAD) Cube IDE SysTick->LOAD  SYSTICK Registers SysTick current value register (STK_VAL) Privileged  SysTick current value register (STK_VAL) CURRENT (Counter current value, Bits 23:0)  SysTick current value register (STK_VAL) Cube IDE SysTick->VAL Question Scan for resources RM0008.PDF: RCC pm0214-stm32- cortexm4-mcus-and- mpus-programming- manual- stmicroelectronics.pdf: SYSTICK Extra resources Eng. Ahmed El deep videos 22 & 23 Lecture 12: System Timer (SysTick) Thank you