CPE 409 Assembly Language Programming PDF

CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT UNIT-II 8086 ASSEMBLY LANGUAGE PROGRAMMING Contents at a glance: 8...

CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT UNIT-II 8086 ASSEMBLY LANGUAGE PROGRAMMING Contents at a glance: 8086 Instruc on Set Assembler direc ves Procedures and macros. 8086 MEMORY INTERFACING: 8086 addressing and address decoding Interfacing RAM, ROM, EPROM to 8086 INSTRUCTION SET OF 8086 The 8086 instruc ons are categorized into the following main types (i) Data copy /transfer instruc ons: These type of instruc ons are used to transfer data from source operand to des na on operand. All the store, load, move, exchange input and output instruc ons belong to this category. (ii) Arithme c and Logical instruc ons: All the instruc ons performing arithmetic , logical, increment, decrement, compare and ASCII instruc ons belong to this category. (iii) Branch Instruc ons: These instruc ons transfer control of execu on to the speciﬁed address. All the call, jump, interrupt and return instruc on belong to this class. (iv) Loop instruc ons: These instruc ons can be used to implement uncondi onal and condi onal loops. The LOOP, LOOPNZ , LOOPZ instruc ons belong to this category. (v) Machine control instruc ons: These instructions control the machine status. NOP, HLT, WAIT and LOCK instruc ons belong to this class. (vi) Flag manipula on instruc ons: All the instruc ons which directly eﬀect the ﬂag register come under this group of instruc ons. Instruc ons like CLD, STD, CLI, STI etc.., belong to this category of instruc ons. (vii) Shi and Rotate instruc ons: These instruc ons involve the bit wise shi ing or rota on in either direc on with or without a count in CX. (viii) String manipula on instruc ons: These instruc ons involve various string manipula on opera on s like Load, move, scan, compare, store etc.., 1. Data Copy/ Transfer Instruc ons: The following instruc ons come under data copy / transfer instruc ons: MOV PUSH POP IN OUT PUSHF POPF LEA LDS/LES XLAT XCHG LAHF SAHF Data Copy/ Transfer Instruc ons: MOV: MOVE: This data transfer instruc on transfers data from one reg ister / memory loca on to another register / memory loca on. The source may be any one of the segment register or other general purpose or special purpose registers or a memory loca on and another register or memory loca on may act as des na on. Syntax: 1) MOV mem/reg1, mem/reg2 MICROPROCESSORS AND MICROCONTROLLERS Page 1 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT [mem/reg1] [mem/reg2] Ex: MOV BX, 0210H MOV AL, BL MOV [SI], [BX] is not valid Memory uses DS as segment register. No memory to memory opera on is allowed. It won’t aﬀect ﬂag bits in the ﬂag register. 2) MOV mem, data [mem] data Ex: MOV [BX], 02H MOV [DI], 1231H 3) MOV reg, data [reg] data Ex: MOV AL, 11H MOV CX, 1210H 4) MOV A, mem [A] [mem] Ex: MOV AL, [SI] MOV AX, [DI] 5) MOV mem, A [mem] A A : AL/AX Ex: MOV [SI], AL MOV [SI], AX 6) MOV segreg,mem/reg [segreg] [mem/reg] Ex: MOV SS, [SI] 7) MOV mem/reg, segreg [mem/reg] [segreg] Ex: MOV DX, SS In the case of immediate addressing mode, a segment register cannot be des na on register. In other words, direct loading of the segment registers with immediate data is not permi ed. To load the segment registers with immediate data, one will have to load any general-purpose register with the data and then it will have to be moved to that par cular segment register. Ex: Load DS with 5000H 1) MOV DS, 5000H; Not permi ed (invalid) Thus to transfer an immediate data into the segment register, the convert procedure is given below: 2) MOV AX, 5000H MOV DS, AX Both the source and des na on operands cannot be memory loca ons (Except for string instruc ons) Other MOV instruc ons examples are given below with the corresponding addressing modes. MICROPROCESSORS AND MICROCONTROLLERS Page 2 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT 3) MOV AX, 5000H; Immediate 4) MOV AX, BX; Register 5) MOV AX, [SI]; Indirect 6) MOV AX, [2000H]; Direct 7) MOV AX, 50H[BX]; Based rela ve, 50H displacement PUSH: Push to Stack: This instruc on pushes the contents of the speciﬁed register/memory loca on on to the stack. The stack pointer is decremented by 2, a er each execu on of the instruc on. The actual current stack -top is always occupied by the previously pushed data. Hence, the push opera on decrements SP by two and this store the two -byte contents of the operand onto the stack. The higher byte is pushed ﬁrst and then the lower byte. Thus out of the two decremental stack addresses the higher byte occupies the higher address and the lower byte occupies the lower address. Syntax: PUSH reg [SP] [SP]-2 [[S]] [reg] Ex: 1) PUSH AX 2) PUSH DS 3) PUSH [5000H]; content of loca on 5000H & 5001H in DS are pushed onto the stack. POP: Pop from stack: This instruc on when executed, loads the speciﬁed register / memory loca on with the contents of the memory loca on of which address is formed using the current stack segment and stack pointer as usual. The stack pointer is incremented by 2. The POP instruc on serves exactly opposite to the PUSH instruc on. Syntax: i) POP mem [SP] [SP] +2 [mem] [[SP]] ii) POP reg [SP] [SP] + 2 [reg] [[SP]] Ex: 1. POP AX 2. POP DS 3. POP [5000H] XCHG: Exchange: This instruc on exchanges the contents of the speciﬁed source and des na on operands, which may be registers or one of them may be a memory loca on. However, exchange of data contents of two m emory loca ons is not permi ed. Syntax: i) XCHG AX, reg 16 [AX] [reg 16] Ex: XCHG AX, DX ii) XCHG mem, reg [mem] [reg] Ex: XCHG [BX], DX Register and memory can be both 8-bit and 16-bit and memory uses DS as segment register. iii) XCHG reg, reg [reg] [ reg ] MICROPROCESSORS AND MICROCONTROLLERS Page 3 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Ex: XCHG AL, CL XCHG DX, BX Other examples: 1. XCHG [5000H], AX; This instruc on exchanges data between AX and a memory loca on [5000H] in the data segment. 2. XCHG BX; This instruc on exchanges data between AX and BX. I/O Opera ons: IN: Input the port: This instruc on is used for reading an input port. The address of the input port may be speciﬁed in the instruc on directly or indirectly AL and AX are the allowed des na ons for 8 and 16-bit input opera ons. DX is the only register (implicit), which is allowed to carry the port address. Ex: 1. IN AL, DX [AL] [PORT DX] Input AL with the 8-bit contents of the port addressed by DX 2. IN AX, DX [AX] [PORT DX] 3. IN AL, PORT [AL] [PORT] 4. IN AX, PORT [AX] [PORT] 5. IN AL, 0300H; This instruc on reads data from an 8-bit port whose address is 0300H and stores it in AL. 6. IN AX ; This instruc on reads data from a 16-bit port whose address is in DX (implicit) and stores it in AX. OUT: Output to the Port: This instruc on is used for wri ng to an output port.The address of the output port may be speciﬁed in the instruc on directly or implicitly in DX. Contents of AX or AL are transferred to a directly or indirectly addressed port a er execu on of this instruc on. The data to an odd addressed port is transferred on D 8 –D15 while that to an even addressed port is transferred on D 0-D7.The register s AL and AX are the allowed source operands for 8- bit and 16-bit opera ons respec vely. Ex: 1. OUTDX,AL [PORT DX] [AL] 2. OUT DX,AX [PORT DX] [AX] 3. OUT PORT,AL [PORT] [AL] 4. OUT PORT,AX [PORT] [AX] Output the 8-bit or 16-bit contents of AL or AX into an I/O port addressed by the contents of DX or local port. 5. OUT 0300H,AL; This sends data available in AL to a port whose address is 0300H 6. OUT AX; This sends data available in AX to a port whose address is speciﬁed implicitly in DX. 2. Arithme c Instruc ons: ADD ADC SUB SBB MUL IMUL DIV IDIV CMP NEGATE INC DEC DAA DAS AAA AAS AAM AAD CBW CWD These instruc ons usually perform the arithme c opera ons, like addi on, subtra c on, mul plica on and division along with the respec ve ASCII and decimal adjust instruc ons. The increment and decrement opera ons also belong MICROPROCESSORS AND MICROCONTROLLERS Page 4 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT to this type of instruc ons. The arithme c instruc ons aﬀect all the condi onal code ﬂags. The oper ands are either the registers or memory loca ons immediate data depending upon the addressing mode. ADD: Addi on: This instruc on adds an immediate data or contents of a memory loca on speciﬁed in the instruc on or a register (source) to the contents of another register (des na on) or memory loca on. The result is in the des na on operand. However, both the source and des na on operands cannot be memory operands. That means memory to memory addi on is not possible. Also the contents of the segment registers cannot be added using this instruc on. All the condi on code ﬂags are aﬀected depending upon the result. Syntax: i. ADD mem/reg1, mem/reg2 [mem/reg1] [mem/reg2] + [mem/reg2] Ex : ADD BL, [ST] ADD AX, BX ii. ADD mem, data [mem] [mem]+data Ex: ADD Start, 02H ADD [SI], 0712H iii. ADD reg, data [reg] [reg]+data Ex: ADD CL, 05H ADD DX, 0132H iv. ADD A, data [A] [A]+data Ex: ADD AL, 02H ADD AX, 1211H Examples with addressing modes: 1. ADD AX, 0100H Immediate 2. ADD AX, BX Register 3. ADD AX, [SI] Register Indirect 4. ADD AX, [5000H] Direct 5. ADD [5000H], 0100H Immediate 6. ADD 0100H Des na on AX (implicit) ADC: Add with carry: This instruc on performs the same opera on as ADD instruc on, but adds the carry ﬂag bit (which may be set as a result of the previous calcula ons) to the result. All the condi on code ﬂags are aﬀected by th is instruc on. Syntax: i. ADC mem/reg1, mem/reg2 [mem/reg1] [mem/reg1]+[mem/reg2]+CY Ex: ADC BL, [SI] ADC AX, BX ii. ADC mem,data [mem] [mem]+data+CY Ex: ADC start, 02H ADC [SI],0712H iii. ADC reg, data MICROPROCESSORS AND MICROCONTROLLERS Page 5 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT [reg] [reg]+data+CY Ex: ADC AL, 02H ADC AX, 1211H Examples with addressing modes: 1. ADC 0100H Immediate(AX implicit) 2. ADC AX,BX Register 3. ADC AX,[SI] Register indirect 4. ADC AX,[5000H] Direct 5. ADC [5000H],0100H Immediate SUB: Subtract: The subtract instruc on subtracts the source operand from the des na on operand and the result is le in the des na on operand. Source operand may be a register or a memory loca on, but source and des na on operands both must not be memory operands. Des na on opera nd cannot be an immediate data. All the condi on code ﬂags are aﬀected by this instruc on. Syntax: i. Sub mem/reg1, mem/reg2 [mem/reg1] [mem/reg2]-[mem/reg2] Ex: SUB BL,[SI] SUB AX, BX ii. SUB mem/data [mem] [mem]-data Ex: SUB start, 02H SUB [SI],0712H iii. SUB A,data [A] [A]-data Ex: SUB AL, 02H SUB AX, 1211H Examples with addressing modes: 1. SUB 0100H Immediate [des na on AX] 2. SUB AX, BX Register 3. SUB AX,[5000H] Direct 4. SUB [5000H], 0100 Immediate SBB: Subtract with Borrow: The subtract with borrow instruc on subtracts the source operand and the borrow ﬂag (CF)which may reﬂect the result of the previous calcula ons, from the des na on operand.Subtrac on with borrow ,here means subtrac ng 1 from the subtrac on obtained by SUB ,if carry (borrow) ﬂag is set. The result is stored in the des na on operand. All the condi onal code ﬂags are aﬀected by this instruc on. Syntax: i. SBB mem/reg1,mem/reg2 [mem/reg1] [mem/reg1]-[mem/reg2]-CY Ex: SBB BL,[SI] SBB AX,BX ii. SBB mem,data [mem] [mem]-data-CY Ex: SBB Start,02H SBB [SI],0712H iii. SBB reg,data [reg] [reg]-data-CY Ex: SBB CL,05H MICROPROCESSORS AND MICROCONTROLLERS Page 6 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT SBB DX,0132H iv. SBB A,data [A] [A]-data-CY Ex: SBB AL,02H SBB AX,1211H INC: Increment: This instruc on increments the contents of the speciﬁed register or memory loca on by 1. All the condi on ﬂags are aﬀected except the carry ﬂag CF. This instruc on adds a to the content of the operand. Immediate data cannot be operand of this instruc on. Syntax: i. INC reg16 [reg 16] [reg 16]+1 Ex: INC BX ii. INC mem/reg 8 [mem] [mem]+1 [reg 8] [reg 8]+1 Ex: INC BL INC SI Segment register cannot be incremented. This opera on does not aﬀect the carry ﬂag. Examples with addressing modes: 1. INC AX Register 2. INC [BX] Register indirect 3. INC [5000H] Direct DEC: Decrement: The decrement instruc on subtracts 1 from the contents of the speciﬁed register or memory loca on. All the condi on code ﬂags except carry ﬂag are aﬀected depending upon the result. Imme diate data cannot be operand of the instruc on. Syntax: i. DEC reg16 [reg 16] [reg 16]-1 Ex: DEC BX ii. DEC mem/reg8 [mem] [mem-1 [reg 8] [reg 8]-1 Ex: DEC BL Segment register cannot be decremented. Examples with addressing mode: 1. DEC AX Register 2. DEC [5000H] Direct MUL: Unsigned mul plica on Byte or Word: This instruc on mul plies unsigned byte or word by the content of AL. The unsigned byte or word may be in any one of the general-purpose register or memory loca ons. The most signiﬁcant word of result is stored in DX, while the least signiﬁcant word of the result is stored in AX. All the ﬂags are modiﬁed depending upon the result. Immediate operand is not allowed in this instruc on. If the most signiﬁcant byte or word of the result is ‘0’ IF and OF both will be set. Syntax: MUL mem/reg MICROPROCESSORS AND MICROCONTROLLERS Page 7 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT For 8X8 [AX] [AL]*[mem8/reg8] Ex: MUL BL [AX] [AL]*[BL] For 16X16 [DX][AX] [AX]*[mem16/reg16] Ex: MUL BX [DX][AX] [AX]*[BX] higher lower 16-bit 16-bit Ex: 1. MUL BH ; [AX] [AL]*[BH] 2. MUL CX ; [DX][AX] [AX*[CX] 3. MUL WORD PTR[SI];[DX][AX] [AX]*[SI] IMUL: Signed Mul plica on: This instruc on mul plies a signed byte in source operand by a signed byte in AL or signed word in source operand by signed word in AX. The source can be a general purpose register, memory operand, index register or base register, but it cannot be an immediate data. In case of 32 -bit results, the higher order word (MSW) is stored in DX and the lower order word is stored in AX. The AF, PF, SF and ZF ﬂags are undeﬁned a er IMUL. If AH and DH contain parts of 16 and 32-bit result respec vely, CF and OF both will of set. The AL and AX are the implicit operands in case of 8-bit and 16-bit mul plica ons respec vely. The unused higher bits of the result are ﬁlled by sign bit and CF, AF are cleared. Syntax: IMUL mem/reg For 8X8 [AX] [AL]*[mem8/reg8] Ex: IMUL BL [AX] [AL]*[BL] For 16X16 [DX][AX] [AX*[mem16/reg16] Ex: IMUL BX [DX][AX] [AX]*[BX] Memory or register can be 8-bit or 16-bit and this instruc on will aﬀect carry ﬂag & overﬂow ﬂag. Ex: 1. IMUL BH 2. IMUL CX 3. IMUL [SI] DIV: Unsigned division: This instruc on performs unsigned division. It divides an unsigned word or double word by a 16-bit or 8-bit operand. The dividend must be in AX for 16-bit opera on and divisor may be speciﬁed using any one of the addressing modes except immediate. The result will be in AL (quo ent) while AH will contain the remainder. If the result is too big to ﬁt in AL, type 0(divide by zero) interrupt is generated. In case of a double word dividend (32 -bit), the higher word should be in DX and lower word should be in AX. The divisor may be speciﬁed as already explained. The quo ent and the remainder, in this case, will be in AX and DX respec vely. This instruc on does not aﬀect any ﬂag. Syntax: DIV mem/reg Ex: DIV BL (i.e. [AX]/[BX]) [AX] [AH] Remainder For 16 8 ___________ [mem 8/reg 8] [AL] Quo ent MICROPROCESSORS AND MICROCONTROLLERS Page 8 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT [DX] [AX] [DX] Remainder For 32 16 ___________ [mem 16/reg 16] [AX] Quo ent [DX][AX] Ex: DIV BX (i.e. ________ ) [BX] IDIV: Signed Division: This instruc on performs same opera on as the DIV instruc on, but it with signed operands the results are stored similarly as in case of DIV instruc on in both cases of word and double word divisions the results will also be signed numbers. The operands are also speciﬁed in the same way as DIV instruc on. Divide by zero interrupt is generated, if the result is too big to ﬁt in AX (16-bit dividend opera on) or AX and DX (32-bit dividend opera on) all the ﬂags are undeﬁned a er IDIV instruc on. AAA: ASCII Adjust a er addi on: The AAA instruc on is executed a er an ADD instruc on that adds two ASCII coded operands to give a byte of result in AL. The AAA instruc on converts the resul ng contents of AL to unpacked decimal digits. A er the addi on, the AAA instruc on examines the lower 4-bits of AL to check whether it contains a valid BCD number in the range 0 to 9. If it is between 0 to 9 and AF is zero, AAA sets the 4- higher order bits of AL to 0. The AH must be cleared before addi on. If the lower digit of AL is between 0 to 9 and AF is set, 06 is added to AL. The upper 4- bits of AL are cleared and AH is incremented by one. If the value of lower nibble of AL is greater than 9 then the AL is incremented by 06, AH is incremented by 1, the AF and CF ﬂags are set to 1, and the higher4-bits of AL are cleared to 0. The remaining ﬂags are unaﬀected. The AH is modiﬁed as sum of previous contents (usually 00) and the carry from the adjustment, as shown in Fig1.7. This instruc on does not give exact ASCII codes of the sum, but they can be obtained by adding 3030H to AX. 1. AL 57 - Before to AAA AL 07 - A er AAA execu on 2. AL 5 A Previous to AAA AH 0 0 A>9, hence A+6=1010+0110 = 10000 B = 10H AX 0 0 5 A – previous to AAA 01 00 AX - A er AAA execu on Fig1.7 ASCII Adjust A er Addi on Instruc on AAS: ASCII Adjust A er Subtrac on: AAS instruc on corrects the result in AL register a er subtrac ng two unpacked ASCII operands. The result is in unpacked decimal format. If the lower 4-bits of AL register are greater than 9 or if the AF ﬂag is one, the AL is decremented by 6 and AH is decremented by 1, the CF and AF are set to 1. Otherwise, the CF and AF are set to 0, the result needs to no correc on. As a result, the upper nibble of AL is 00 and the lower nibble may be any number from 0 to 9. The procedure similar to the AAA instruc on AH is modiﬁed as diﬀerence of previous contents (usually 0) of AH and the borrow for adjustment. MICROPROCESSORS AND MICROCONTROLLERS Page 9 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT AAM: ASCII Adjust a er Mul plication: This instruc on, a er execu on, converts the product available in AL into unpacked BCD format. This follows a mul plica on instruc on. The lower byte of result (unpacked) remains in AL and the higher byte of result remains in AH. The example given below explains execu on of the instruc on. Suppose, a product is available in AL, say AL=5D. AAM instruc on will form unpacked BCD result in AX. DH is greater than 9, so add of 6(0110) to it D+6=13H. LSD of 13H is the lower unpacked byte for the result. Increment AH by 1, 5+1=6 will be the upper unpacked byte of the result. Thus a er the execu on, AH=06 and AL=03. AAD: ASCII Adjust before Division: Though the names of these two instruc ons (AAM and AAD) appear to be similar, there is a lot of diﬀerence between their func ons. The AAD instruc on converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing number the two unpacked BCD digits in AX by an unpacked BCD byte. PF, SF , ZF are modiﬁed while AF, CF, OF are undeﬁned, a er the execu on of the instruc on AAD. The example explains the execu on of the instruc on. Let AX contain 0508 unpacked BCD for 58 decimal and DH contain 02H. Ex: AX 5 8 AAD result in AL 0 3A 58D=3AH in AL The result of AAD execu on will give the hexadecimal number 3A in AL and 00 in AH. DAA: Decimal Adjust Accumulator: This instruc on is used to convert the result of the addi on of two packed BCD numbers to a valid BCD number. The result has to be only in AL. If the lower nibble is greater than 9, a er addi on or if AF is set, it will add 06 to the lower nibble in AL. A er adding 06 in the lower nibble of AL, if the upper nibble of AL is greater than 9 or if carry ﬂag is set, DAA instruc on adds 60H to AL. The example given below explains the instruc on: i. AL=53 CL=29 ADD AL, CL ; AL (AL) + (CL) ; AL 53+29 ; AL 7C ; AL 7C+06(as C>9) ; AL 82 ii. AL=73 CL=29 ADD AL,CL ; AL AL+CL ; AL 73+29 ; AL 9C ; AL 9C DAA ; AL 02 & CF=1 AL=73 + CL=29 _______ 9C +6 _______ A2 +60 _______ CF=1 02 in AL The instruc on DAA aﬀects AF, CF, PF and ZF ﬂags. The OF ﬂag is undeﬁned. MICROPROCESSORS AND MICROCONTROLLERS Page 10 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT DAS: Decimal Adjust A er Subtrac on: This instruc on converts the results of subtrac on of two packed BCD numbers to a valid BCD number. The subtrac on has to be in AL only. If the lower nibble of AL is greater than 9, this instruc on will subtract 06 from lower nibble of AL. If the result of subtrac ons sets the carry ﬂag or if upper nibble is greater than 9, it subtracts 60H from AL. This instruc on modiﬁer the AF, CF, PF and ZF ﬂags. The OF is undeﬁned a er DAS instruc on. The examples are as follows: Ex: i. AL=75 BH=46 SUB AL,BH ; AL 2F=(AL)-(BH) ; AF=1 DAS ; AL 29 (as F>9,F-6=9) ii. AL=38 CH=61 SUB AL, CH ; AL D7 CF=1(borrow) DAS ; AL 77(as D>9, D-6=7) ; CF=1(borrow) NEG: Negate: The negate instruc on forms 2’s complement of the speciﬁed des na on in the in struc on. For obtaining 2’s complement, it subtracts the contents of des na on from zero. The result is stored back in the des na on operand which may be a register or a memory loca on. If OF is set, it indicates that the opera on could not be completed successfully. This instruc on aﬀects all the condi on code ﬂags. CBW: Convert signed Byte to Word: This instruc on converts a signed byte to a signed word. In other words, it copies the sign bit of a byte to be converted to all the bits in the higher byte of the result word. The byte to be converted must be in AL. The result will be in AX. It does not aﬀect any ﬂag. CWD: Convert Signed Word to double Word: This instruc on copies the sign bit of AX to all the bits of DX register. This opera on is to be done before signed division. It does not aﬀect any other ﬂag. 3. Logical Instruc ons: AND OR NOT XOR TEST These byte of instruc ons are used for carrying out the bit by bit shi , rotate or basic logical opera ons. All the condi onal code ﬂags are aﬀected depending upon the result. Basic logical opera ons available with 8086 instruc on set an AND, OR, NOT and XOR. AND: Logical AND: This instruc on bit by bit ANDs the source operand that may be an immediate, a register, or a memory loca on to the des na on operand that may be a register or a memory loca on. The result is stored in the des na on operand. At least one of the operand should be a register or a memory operand. Both the operands cannot be memory loca ons or immediate operand. The examples of this instruc on are as follows: Syntax: i. AND mem/reg1, mem/reg2 [mem/reg1] [mem/reg1] [mem/reg2] Ex: AND BL, CH ii. AND mem,data [mem] [mem] data Ex: AND start,05H iii. AND reg,data [reg] [reg] data MICROPROCESSORS AND MICROCONTROLLERS Page 11 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Ex: AND AL, FOH iv. AND A,data [A] [A] data A:AL/AX Ex: AND AX,1021H OR: Logical OR: The OR instruc on carries out the OR opera on in the same way as described in case of the AND opera on. The limita ons on source and des na on operands are also the same as in case of AND opera on. Syntax: i. OR mem/reg1, mem/reg2 [mem/reg1] [mem/reg1] [mem/reg2] Ex: OR BL, CH ii. OR mem,data [mem [mem] data Ex: OR start, 05H iii. OR Start,05H [reg] [reg] data Ex: OR AL, FOH iv. OR A, data [A] [A] data Ex: OR AL, 1021H A: AL/AX. NOT: Logical Invert: The NOT instruc on complements (invents) the contents of an operand re gister or a memory loca on bit by bit. Syntax: i. NOT reg [reg] [reg] Ex: NOT AX ii. NOT mem [mem] [mem] Ex: NOT [SI] XOR: Logical Exclusive OR: The XOR opera on is again carried out in a similar way to the AND and OR opera on. The constraints on high output, when the 2 input bits are dissimilar. Otherwise, the output is zero. Syntax: i. XOR mem/reg1, mem/reg2 [mem/reg1] [mem/reg1] [mem/reg2] Ex: XOR BL, CH ii. XOR mem,data [mem] [mem] data Ex: XOR start, 05H iii. XOR reg, data [reg] [reg] data Ex: XOR AL, FOH iv. XOR A, data [A] [A] data MICROPROCESSORS AND MICROCONTROLLERS Page 12 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT A: AL/AX Ex: XOR AX, 1021H CMP: Compare: This instruc on compares the source operand, which may be a register or an immediate data or a memory loca on, with a des na on operand that may be a register or a memory loca on. For comparison, it subtracts the source operand from the des na on operand but does not store the result anywhere. The ﬂags a re aﬀected depending on the result of subtrac on. If both the operands are equal, zero ﬂag is set. If the source operand is greater than the des na on operand, carry ﬂag is set or else, carry ﬂag is reset. Syntax: i. CMP mem/reg1, mem/reg2 [mem/reg1] – [mem/reg2] Ex: CMP CX, BX ii. CMP mem/reg, data [mem/reg] – data Ex: CMP CH, 03H iii. CMP A, data [A]- data A: AL/AX Ex: CMP AX, 1301H TEST: Logical Compare Instruc on: The TEST instruc on performs a bit by bit logical AND opera on on the two operands. Each bit of the result is then set to 1, if the corresponding bits of both operands are1, else the result bit is rest to 0. The result of this and opera on is not available for further use, but ﬂags are aﬀected. The aﬀected ﬂags are OF, CF, ZF and PF. The operands may be register, memory or immediate data. Syntax: i. TEST mem/reg1, mem/reg2 [mem/reg1] [mem/reg2] Ex: Test CX,BX ii. TEST mem/reg, data [mem/reg] data Ex: TEST CH, 03H iii. TEST A, data [A] data A: AL/AX Ex: TEST AX, 1301H 4.Shi Instruc ons: SHL/SAL SHR SAR SHL/SAL: Shi Logical/ Arithme c Le : These instruc ons shi the operand word or byte bit by bit to the le and insert zeros in the newly introduced least signiﬁcant bits. In case of all the SHIFT and ROTATE instruc ons, the count is either 1 or speciﬁed by register CL. The operand may reside in a register or memory loca on but cannot be immed iate data. All ﬂags are aﬀected depending on the result. Ex: BIT POSITIONS: CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OPERAND: 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 __________________________________________________ SHL 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 st RESULT1 _________________________________________________ SHL 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 RESULT 2 nd ___________________________________________________ MICROPROCESSORS AND MICROCONTROLLERS Page 13 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Syntax: i. SAL mem/reg,1 Shi arithme c le once 7 0 CF 0 ii. SAL mem/reg, CL Shi arithme c le a byte or word by shi count in CL register. iii. SHL mem/reg,1 Shi Logical Le Ex: SHL BL, 01H iv. SHL mem/reg, CL Shi Logical Le once a byte or word in mem/reg. SHR: Shi Logical Right: This instruc on performs bit-wise right shi s on the operand word or byte that may reside in a register or a memory loca on, by the speciﬁed count in the instruc on and inserts zeros in the shi ed posi ons. The result is stored in the des na on operand. This instruc on shi s the operand through carry ﬂag. Ex: BIT POSITIONS: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF OPERAND : 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 _____________________________________________ Count=1 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 _____________________________________________ Count=2 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 _____________________________________________ SAR: Shi Arithme c Right: This instruc on performs right shi s on the operand word or byte, that ma y be a register or a memory loca on by the speciﬁed count in the instruc on and inserts the most signiﬁcant bit of the operand the newly inserted posi ons. The result is stored in the des na on operand. All the condi on code ﬂags are aﬀected. Thi s shi opera on shi s the operand through carry ﬂag. Ex: BIT POSITIONS: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF OPERAND: 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 _____________________________________________ Count=1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 _____________________________________________ inserted MSB=1 _____________________________________________ Count=2 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 _____________________________________________ inserted MSB=1 Immediate operand is not allowed in any of the shi instruc ons. Syntax: i. SAR mem/reg,1 ii. SAR mem/reg, CL MICROPROCESSORS AND MICROCONTROLLERS Page 14 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT 5.Rotate Instruc ons: ROR ROL RCR RCL ROR: Rotate Right without Carry: This instruc on rotates the contents of the des na on operand to the right (bit - wise) either by one or by the count speciﬁed in CL, excluding carry. The least signiﬁcant bit is pushed into the carry ﬂag and simultaneously it is transferred into the most signiﬁcant b it posi on at each opera on. The remaining bits are shi ed right by the speciﬁed posi ons. The PF, SF, and ZF ﬂags are le unchanged by the rotate opera on. The operand may be a register or a memory loca on but it can’t be an immediate operand. Th e des na on operand may be a register (except a segment register) or a memory loca on. Syntax: i. mem/reg, 01 Ex: ROR BL, 01 ii. ROR mem/reg, CL Ex: ROR BX, CL Ex: BIT POSITIONS: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF OPERAND: 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 _____________________________________________ Count=1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 _____________________________________________ Count=2 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 _____________________________________________ Execu on of ROR Instruc on. ROL: Rotate Le without Carry: This instruc on rotates the content of the des na on operand to the le by the speciﬁed count (bit-wise) excluding carry. The most signiﬁcant bit is pushed into the carry ﬂag as well as the least signiﬁcant bit posi on at each opera on. The remaining bits are shi ed le subsequently by the speciﬁed count posi ons. The PF, SF and ZF ﬂags are le unchanged by this rotate opera on. The operand may be a register or a memory loca on. Syntax: i. ROL mem/reg, 1 Rotate once le ii. ROL mem/reg, CL Rotate once le a byte or a word in mem/reg. Ex: BIT POSITIONS: CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OPERAND : 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 _____________________________________________ SHL RESULT 1st:1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1 ______________________________________________ SHL RESULT 2nd: 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 _______________________________________________ Execu on of ROL instruc on RCR: Rotate Right Through Carry: This instruc on rotates the contents (bit-wise) of the des na on operand right by the speciﬁed count through carry ﬂag (CF) For each opera on, the carry ﬂag is pushed into the MSB of the operand, and the LSB is pushed into carry ﬂag. The remaining bits are shi ed right by the speciﬁed count posi ons. The SF, PF, ZF are le unchanged. The operand may be a register or memory loca on. MICROPROCESSORS AND MICROCONTROLLERS Page 15 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Syntax: i. RCL mem/reg, 1 Ex: RCL BL, 1 ii. mem/reg, CL Ex: RCL BX, CL Rotate through carry le once a byte or word in mem/reg. Ex: BIT POSITIONS: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF OPERAND : 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 0 _____________________________________________ Count=1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 ______________________________________________ Execu on of RCR Instruc on RCL: Rotate Le through Carry: This instruc on rotates (bit-wise) the contents of the des na on operand le by the speciﬁed count through the carry ﬂag (CF) For each opera on, the carry ﬂag is pushed into LSB, and the MSB of the operand is pushed into carry ﬂag. The remaining bits are shi ed le by the speciﬁed posi ons. The SF, PF, ZF are le unchanged. The operand may be a register or a memory loca on. Ex: BIT POSITIONS :CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OPERAND : 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1 __________________________________________________ Count=1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1 0 __________________________________________________ Execu on of RCL Instruc on The count for rota on or shi ing is either 1 or is speciﬁed using register CL, in case of all the shi and rotate instruc ons. 6.String Manipula on Instruc ons: A series of data bytes or words available in memory at consecu ve loca ons, to be referred to collec vely or individually are called as byte strings or word strings. REP MOVSB/MOVSW CMPSB/CMPSW SCASB/SCASW STOSB/STOSW LODSB/LODSW REP: Repeat Instruc on Preﬁx: This instruc on is used as a preﬁx to other instruc ons. The instruc on to which the REP preﬁx is provided, is executed repeatedly un l the CX register becomes zero (at each itera on CX is automa cally decremented by one) When CX becomes zero, the execu on proceeds to the next instruc on in sequence. There are two more op ons of the REP instruc on. The ﬁrst is REPE/REPZ (i.e. repeat opera on which equal/zero. The second is REPNE/REPNZ allows for repea ng the opera on which not equal/not zero. These op ons ar e used for CMPS, SCAS instruc ons only, as instruc on preﬁxes. MOVSB/MOVSW: Move String Byte or String Word: Suppose a string of bytes, stored in a set of consecu ve memory loca ons is to be moved to another set of des na on loca ons. The star n g byte of the source string is located in the memory loca on whose address may be computed using SI (Source Index) and DS (Data Segment) contents. The star ng address of the des na on loca ons where this string has to be relocated is given by DI (Dest ina on Index) and ES (Extra Segment) contents. The star ng address of the source string is 10H * DS + [SI] while the star ng address of the des na on string is 10H * ES + [DI]. The MOVSB/MOVSW instruc on thus, moves a string of bytes/words pointed to by DS:SI pair (source) to the memory loca on pointed to by ES:DI pair (des na on) A er the MOVS instruc on is executed once, the index registers are automa cally updated and CX is decremented. The incremen ng or decremen ng of the pointers, i.e. SI and DI depend upon the direc on ﬂag DF. If DF is 0, the index registers are incremented, otherwise, they are decremented, in case of all string manipula on instruc ons. Ex: MICROPROCESSORS AND MICROCONTROLLERS Page 16 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT (a) DATA SEGMENT TEST-MESS DB “IT’S TIME FOR A NEW HOME” ;string to move DB 100 DUP(?) ;sta onary block of text NEW-LOC DB 23 DUP(0) ;string des na on. DATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DATA,ES:DATA MOV AX,DATA ;ini alize data segment register MOV DS,AX MOV ES,AX ;ini alize extra segment register LEA SI,TEST-MESS ;point SI at source string LEA DI,NEW-LOC ;point DI at des na on string MOV CS,23 ;use CX register as counter CLD ;clear DF, so pointers auto increment REP MOVSB ;a er each string element is moved ;move string byte un l all moved CODE ENDS END (b) Fig : program for moving a string from one loca on to another in memory (a) Memory map (b) AL program. Here, the REPEAT-UNTIL loop then consists of moving a byte, incremen ng the pointers to point to the source and des na on for next byte, and decremen ng the counter to determine whether all bytes have been moved. The single 8086 instruc on MOVSB will perform all the ac ons in the REPEAT-UNTIL loop. The MOVSB instruc on will copy a byte from the loca on pointed to by the DI register. It will then automa cally increment SI to point to next des na on loca on. The repeat (REP) preﬁx in front of the MOVSB instruc on, the MOVSB instruc on will be repeated and CX decremented un l CX is counted down to zero. In other words, the REP MOVSB instruc on will move the en re string from the source loca on to the des na on loca on if the pointers are properly ini alized. CMPSB/CMPSW: Compare String Byte or String Word: The CMPS instruc on is used to compare two strings of bytes or words. The length of the string must be stored in the register CX. If both the byte or word strings are equal, zero ﬂag is set. The ﬂags are aﬀected in the same way as CMP instruc on. The DS:SI and ES:DI point to the two strings. The REP instruc on preﬁx is used to repeat the opera on ll CX (counter) becomes zero or the condi on speciﬁed by the REP preﬁx is false. The following string of instruc ons explain the instruc on. The comparison of the string starts from ini al or word of the string, a er each comparison the index registers are updated depending on the direc on ﬂag and the counter is decremented. This byte by byte or word by word comparison con nues ll a mismatch is found. When, a mismatch is found, the carry and zero ﬂags are modiﬁed appropriately and the execu on proceeds further. Ex: MOV AX, SEG1 ; Segment address of String1, i.e. SEG1 is moved to AX. MOV DS, AX ; Load it to DS. MOV AX, SEG2 ; segment address of STRING2, i.e. SEG@ is moved to AX. MOV ES, AX ; Load it to ES. MOV SI, OFFSET STRING1 ; Oﬀset of STRING1 Is moved to SI. MOV DI, OFFSET STRING2 ; Oﬀset of string2 is moved to DI. MOV CX, 0110H ; Length of string is moved to CX. CLD ; clear DF, i.e. set auto increment mode. REPE CMPSW ; Compare 010H words of STRING1 And STRING2, while they are equal, IF a mismatch is found, modify the ﬂags and proceed with further execu on. If both strings are completely equal, i.e. CX becomes zero, the ZF is set, otherwise ZF is reset. MICROPROCESSORS AND MICROCONTROLLERS Page 17 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT SCAS: Scan String BYTE or String Word: This instruc on scans a string of bytes or words for an operand byte or word speciﬁed in the register AL or AX. The string is pointed to by ES:DI register pair. The length of the string is stored in CX. The DF controls the mode for scanning of the string as stated in case of MOVSB instruc on. Whenever a match to the speciﬁed operand, is found in the string, execu on stops and the zero ﬂag is set. If no match is found, th e zero ﬂag is reset. The REPNE preﬁx is used with the SCAS instruc on. The pointers and counters are updated automa cally, ll a match is found. Ex: MOV AX, SEG ; Segment address of the string, i.e. SEG is moved to AX. MOV ES, AX ; Load it to ES. MOV DI, OFFSET ; String oﬀset, i.e. OFFSET is moved to DI. MOV CX,010H ; Length of the string is moved to CX. MOV AX, WORD ; The word to be scanned for, i.e. WORD is in AL. CLD ; Clear DF REPNE SCASW ; Scan the 010H bytes of the string, ll a match to WORD is found. This string of instruc ons ﬁnds out, if it contains WORD. IF the WORD is found in the word string, before CX becomes zero, the ZF is set, otherwise the ZF is reset. The scanning will con nue ll a match is found. Once a match is found the execu on of the program proceeds further. LODS: Load string Byte or String word: The LODS instruc on loads the AL/AX register by the content of a string pointed to by DS:SI register pair. The SI is modiﬁed automa cally depending on DF. If it is a byte transfer (LODSB), the SI is modiﬁed bye one and if it is a word transfer (LODSW), the SI is modiﬁed by two. No other ﬂags are aﬀected by this instruc on. STOS: Store String Byte or String Word: The STOS instruc on stores the AL/AX register con tents to a loca on in the string pointed by ES:DI register pair. The DI is modiﬁed Accordingly. No ﬂags are aﬀected by this instruc on. The direc on ﬂag controls the string instruc on execu on. The source index SI and des na on index DI are mod iﬁed a er each itera on automa cally. If DF=1, then the execu on follows auto decrement mode. In this mode, SI and DI are decremented automa cally a er each itera on (by1 or 2 depending on byte or word opera ons) Hence, in auto decremen ng mode, the string are referred to by their ending addresses. If DF=0, then the execu on follows auto increment mode. In this mode, SI and DI are incremented automa cally (by 1 or 2 depending on byte or word opera on) A er each itera on, hence the strings, in this case, are referred to by their star ng addresses. 7.Control Transfer or Branching Instruc on: The control transfer instruc ons transfer the ﬂow of execu on of the program to a new address speciﬁed in the instruc on directly or indirectly. When this type of instruc on is executed, the CS and IP registers get loaded with new values of CS and IP corresponding to the loca on where the ﬂow of execu on is going to be transferred. This type of instruc ons are classiﬁed in two types: i. Uncondi onal control Transfer (Branch) Instruc ons: In case of uncondi onal control transfer instruc ons; the execu on control is transferred to the speciﬁed loca on independent of any status or condi on. The CS and IP are uncondi onally modiﬁed to th e new CS and IP. ii. Condi onal Control Transfer (Branch) Instruc ons: In the condi onal control transfer instruc ons, the control is transferred to the speciﬁed loca on provided the result of the previous opera on sa sﬁes a par cular condi on, oth erwise, the execu on con nues in normal ﬂow sequence. The results of the previous opera ons are replicated by condi on code ﬂags. In other words, using type of instruc on the control will be transferred to a par cular speciﬁed loca on, if a part icular ﬂag sa sﬁes the condi on. Uncondi onal Branch Instruc ons: CALL RET JUMP IRET INT N INT O LOOP MICROPROCESSORS AND MICROCONTROLLERS Page 18 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT CALL: Uncondi onal Call: This instruc on is used to call a subrou ne procedure from a main program. The address of the procedure may specify directly or indirectly depending on the address mode. There are again two types of procedures depending on whether it is available in the same segment (Near CALL, i.e. + 2K displacement) or in another segment (Far CALL, i.e. anywhere outside the segment). The modes for them are respec vely called as intrasegment and intersegment addressing (i.e. address of the next instruc on) and CS onto the stack along with the ﬂags and loads the CS and IP registers, respec vely, with the segment and oﬀset addresses of the procedure to be called. RET: Return from the Procedure: At each CALL instruc on, the IP and CS of the next instruc on is pushed onto stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruc on must be executed. When it is executed, the previously stored content of IP and CS along with ﬂags are retrieved into the CS, IP and ﬂag registers from the stack and the execu on of the main program con nues further. In case of a FAR procedure the current contents of SP points to IP and CS at the me of return. While in case of a NEAR procedure, it points to only IP. Depending on the byte of procedure and the SP contents, the RET instruc on is of four types: i. Return within a segment. ii. Return within a segment adding 16-bit immediate displacement to the SP contents. iii. Return intersegment. iv. Return intersegment adding 16-bit immediate displacement to the SP contents. INT N: Interrupt Type N: In the interrupt structure of 8086/8088, 256 interrupts are deﬁned corresponding to the types from 00H to FFH. When an INT N instruc on is executed, the TYPE byte N is mul plied by 4 and the contents of IP and CS of the interrupt service rou ne will be taken from the hexadecimal mul plica on (N * 4) as oﬀset address and 0000 as segment address. In other words, the mul plica on of type N by 4 (oﬀset) points to a memory block in 0000 segment, which contains the IP and CS values of the interrupt service rou ne. For the execu on of this instruc on, the IP must be enabled. Ex: The INT 20H will ﬁnd out the address of the interrupt service rou ne follows: INT 20H Type * 4 = 20 X 4 = 80H Pointer to IP and CS of the ISR is 0000:0080H The arrangement of CS and IP addresses of the ISR in the interrupt rector table is as follows. INTO: Interrupt on overﬂow: This is executed, when the overﬂow ﬂag OF is set. The new contents of IP an CS are taken from the address 0000:0000 as explained in INT type instruc on. This is equivalent to a type 4 instruc on. JMP: Uncondi onal Jump: This instruc on uncondi onally transfer the control of execu on to the speciﬁed address using an 8-bit or 16-bit displacement (intrasegment rela ve, short or long) or CS:IP (intersegment direct for) No ﬂags are aﬀected by this instruc on. Corresponding to the three methods of specifying jump address, the JUMP instruc on has the following three formats. JUMP DISP 8-bit Intrasegment, rela ve, near jump JUMP DISP 16-bit DISP 16-bit Intrasegment, rela ve, For jump JUMP IP(LB) IP(UB) CS(LB) CS(UB) Intersegment, direct, jump IRET: Return from ISR: When interrupt service rou ne is to be called, before transferring control to it, the IP, CS and ﬂag register are stored on to the stack to indicate the lo ca on from where the execu on is to be con nued, a er the ISR is executed. So, at the end of each ISR, when IRET is executed, the valuesof IP, CS and ﬂags are retrieved from the stack to con nue the execu on of the main program. The stack is modiﬁe d accordingly. MICROPROCESSORS AND MICROCONTROLLERS Page 19 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT LOOP: Loop uncondi onally: This instruc on executes the part of the program from the label or address speciﬁed in the instruc on up to the loop instruc on, CX number of mes. At each itera on, CX is decremented automa cally, in other words, this instruc on implements DECREMENT counter and JUMP IF NOT ZERO structure. Ex: MOV CX,0005H ; Number of mes in CX MOV BX, 0FF7H ; Data to BX Label MOV AX, CODE1 OR BX,AX AND DX,AX LOOP Label The execu on proceeds in sequence, a er the loop is executed, CX number of mes. IF CX is already 00H, the execu on con nues sequen ally. No ﬂags are aﬀected by this instruc on. Condi onal Branch Instruc ons: LOOPE/LOOPZ LOOPNE/LOOPNZ When these instruc ons are executed, they transfer execu on control to the address speciﬁed rela vely in the instruc on, provided the condi on in the opcode is sa sﬁed, otherwise, the execu on con nues sequen ally. The condi ons, here means the status of the condi on code ﬂags. These ty pe of instruc ons don’t aﬀect any ﬂags. The address has to be speciﬁed in the instruc on rela vely in terms of displacement, which must lie within – 80H to 7FH (or –128 to 127) bytes from the address of the branch instruc on. In other words, only sh ort jumps can be implemented using condi onal branch instruc ons. A label may represent the displacement, if it has within the above - speciﬁed range. The diﬀerent 8086/8088 condi onal branch instruc ons and their opera ons are listed in Table1 SL.No Mnemonic Displacement Opera on 1 JZ/JE Label Transfer execu on control to address ‘Label’, if ZF=1 2 JNZ/JNE Label Transfer execu on control to address ‘Label’, if ZF=0 3 JS Label Transfer execu on control to address ‘Label’, if SF=1 4 JNS Label Transfer execu on control to address ‘Label’, if SF=0 5 JO Label Transfer execu on control to address ‘Label’, if OF=1 6 JNO Label Transfer execu on control to address ‘Label’, if OF=0 7 JP/JPE Label Transfer execu on control to address ‘Label’, if P F=1 8 JNP Label Transfer execu on control to address ‘Label’, if PF=0 9 JB/JNAE/JC Label Transfer execu on control to address ‘Label’, if CF=1 10 JNB/JNE/JNC Label Transfer execu on control to address ‘Label’, if CF=0 11 JBE/JNA Label Transfer execu on control to address ‘Label’, if CF=1 or ZF=1 12 JNBE/JA Label Transfer execu on control to address ‘Label’, if CF=0 or ZF=0 13 JL/JNGE Label Transfer execu on control to address ‘Label’, if neither SF=1 nor OF=1 14 JNL/JGE Label Transfer execu on control to address ‘Label’, if neither SF=0 nor OF=0 15 JNE/JNC Label Transfer execu on control to address MICROPROCESSORS AND MICROCONTROLLERS Page 20 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT ‘Label’, if ZF=1or neither SF nor OF is 1 16 JNLE/JE Label Transfer execu on control to address ‘Label’, if ZF=0 or at least any are of SF & OF is 1 Table:1 Condi onal branch instruc ons. 8. Flag Manipula on and Processor Control Instruc ons: These instruc ons control the func oning of the available hardware inside the processor chip. These are categorized into 2 types: a) ﬂag manipula on instruc ons b) Machine control instruc ons. The ﬂag manipula on instruc ons directly modify same of the ﬂags of 8086. The ﬂag manipula on instruc ons and their func ons are as follows: CLC – clear carry ﬂag CMC – Complement carry ﬂag STC – Set carry ﬂag CLD – clear direc on ﬂag STD - Set direc on ﬂag CLI – clear interrupt ﬂag STI – Set interrupt ﬂag These instruc ons modify the carry (CF), Direc on (DF) and interrupt (IF) ﬂags directly. The DF and IF, which may be the processor opera on; like interrupt responses and auto increment or auto -decrement modes. Thus the respec ve instruc ons may also be called as machine or processor control instruc ons. The other ﬂags can be modiﬁed using POPF and SAHF instruc ons, which are termed as data transfer instruc ons. No direct instruc ons are available for modifying the status ﬂags except carry ﬂags. The machine control instruc ons don’t require any opera onal. The machine control instruc ons supported by 8086/8088 are listed as follows along with their func ons: WAIT – Wait for Test input pin to go low HLT – Halt the processor NOP – No opera on ESC – Escape to external device like NDP LOCK – Bus lock instruc on preﬁx. ASSEMBLER DIRECTIVES Assembler direc ves are the commands to the assembler that direct the assembly process. They indicate how an operand is treated by the assembler and how assembler handles the program. They also direct the assembler how program and data should arrange in the memory. ALP’s are composed of two type of statements. (i) The instruc ons which are translated to machine codes by assembler. (ii) The direc ves that direct the assembler during assembly process, for which no machine code is generated. 1. ASSUME: Assume logical segment name. The ASSUME direc ve is used to inform the assembler the names of the logical segments to be assumed for diﬀerent segments used in the program.In the ALP each segment is given name. Syntax: ASSUME segreg:segname,…segreg:segname Ex: ASSUME CS:CODE ASSUME CS:CODE,DS:DATA,SS:STACK MICROPROCESSORS AND MICROCONTROLLERS Page 21 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT 2. DB: Deﬁne Byte The DB direc ve is used to reserve byte or bytes of memory loca ons in the available memory. Syntax: Name of variable DB ini aliza on value. Ex: MARKS DB 35H,30H,35H,40H NAME DB “VARDHAMAN” 3. DW: Deﬁne Word The DW direc ve serves the same puposes as the DB direc ve,but it now makes the assembler reserve the number of memory words(16-bit) instead of bytes. Syntax: variable name DW ini aliza on values. Ex: WORDS DW 1234H,4567H,2367H WDATA DW 5 Dup(522h) (or) Dup(?) 4. DD: Deﬁne Double: The direc ve DD is used to deﬁne a double word (4bytes) variable. Syntax: variablename DD 12345678H Ex: Data1 DD 12345678H 5. DQ: Deﬁne Quad Word This direc ve is used to direct the assembler to reserve 4 words (8 bytes) of memory for the speciﬁed variable and may ini alize it with the speciﬁed values. Syntax: Name of variable DQ ini alize values. Ex: Data1 DQ 123456789ABCDEF2H 6. DT: Deﬁne Ten By tes The DT direc ve directs the assembler to deﬁne the speciﬁed variable requiring 10 bytes for its storage and ini alize the 10-bytes with the speciﬁed values. Syntax: Name of variable DT ini alize values. Ex: Data1 DT 123456789ABCDEF34567H 7. END: End of Program The END direc ve marks the end of an ALP. The statement a er the direc ve END will be ignored by the assembler. 8. ENDP: End of Procedure The ENDP direc ve is used to indicate the end of procedure. In the AL programming the subrou nes ar e called procedures. Ex: Procedure Start : Start ENDP MICROPROCESSORS AND MICROCONTROLLERS Page 22 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT 9. ENDS: End of segment The ENDS direc ve is used to indicate the end of segment. Ex: DATA SEGMENT : DATA ENDS 10.EVEN: Align on Even memory address The EVEN direc ves updates the loca on counter to the next even address. Ex: EVEN Procedure Start : Start ENDP The above structure shows a procedure START that is to be aligned at an even address. 11.EQU: Equate The direc ve EQU is used to assign a label with a value or symbol. Ex: LABEL EQU 0500H ADDITION EQU ADD 12.EXTRN: External and public The direc ve EXTRN informs the assembler that the names, procedures and labels declared a er this direc ve have been already deﬁned in some other AL modules. While in other module, where names, procedures and labels actually appear, they must be declared public using the PUBLIC direc ve. Ex: MODULE1 SEGMENT PUBLIC FACT FAR MODULE1 ENDS MODULE2 SEGMENT EXTRN FACT FAR MODULE2 END 13.GROUP: Group the related segments This direc ve is used to form logical groups of segments with similar purpose or type. Ex: PROGRAM GROUP CODE, DATA, STACK *CODE, DATA and STACK segments lie within a 64KB memory segment that is named as PROGRAM. 14.LABEL: label The label is used to assign name to the current content of the loca on counter. MICROPROCESSORS AND MICROCONTROLLERS Page 23 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Ex: CONTINUE LABEL FAR The label CONTINUE can be used for a FAR jump, if the program contains the above statement. 15.LENGTH: Byte length of a label This is used to refer to the length of a data array or a string Ex : MOV CX, LENGTH ARRAY 16.LOCAL: The labels, variables, constant or procedures are declared LOCAL in a module are to be used only by the par cular module. Ex : LOCAL a, b, Data1, Array, Rou ne 17.NAME: logical name of a module The name direc ve is used to assign a name to an assembly language program module. The module may now be refer to by its declared name. Ex : Name “addi on” 18.OFFSET: oﬀset of a label When the assembler comes across the OFFSET operator along with a label, it ﬁrst compu ng the 16-bit oﬀset address of a par cular label and replace the string ‘OFFSET LABEL’ by the computed oﬀset address. Ex : MOV SI, oﬀset list 19.ORG: origin The ORG direc ve directs the assembler to start the memory allotment for the par cular segment, block or code from the declared address in the ORG statement. Ex: ORG 1000H 20.PROC: Procedure The PROC direc ve marks the start of a named procedure in the statement. Ex: RESULT PROC NEAR ROUTINE PROC FAR 21.PTR: pointer The PTR operator is used to declare the type of a label, variable or memory operator. Ex : MOV AL, BYTE PTR [SI] MOV BX, WORD PTR [2000H] 22.SEG: segment of a label The SEG operator is used to decide the segment address of the label, variable or procedure. Ex : MOV AX, SEG ARRAY MOV DS, AX 23.SEGMENT: logical segment The segment direc ve marks the star ng of a logical segment MICROPROCESSORS AND MICROCONTROLLERS Page 24 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Ex: CODE SEGMENT : CODE ENDS 24.SHORT: The SHORT operator indicates to the assembler that only one byte is required to code the displacement for jump. Ex : JMP SHORT LABEL 25.TYPE: The TYPE operator directs the assembler to decide the data type of the speciﬁed label and replaces the TYPE label by the decided data type. For word variable, the data type is 2. For double word variable, the data type is 4. For byte variable, the data type is 1. Ex : STRING DW 2345H, 4567H MOV AX, TYPE STRING AX=0002H 26.GLOBAL: The labels, variables, constants or procedures declared GLOBAL may be used by other modules of the program. Ex : ROUTINE PROC GLOBAL. 27.FAR PTR: This direc ve indicates the assembler that the label following FAR PTR is not available within the same segment and the address of the label is of 32-bits i.e 2-bytes of oﬀset followed by 2-bytes of segment address. Ex : JMP FAR PTR LABEL 28.NEAR PTR: This direc ve indicates that the label following NEAR PTR is in the same segment and needs only 16-bit i.e 2-byte oﬀset to address it Ex : JMP NEAR PTR LABEL CALL NEAR PTR ROUTINE Procedures and Macros: When we need to use a group of instruc ons several mes throughout a program there are two ways we can avo id having to write the group of instruc ons each me we want to use them. 1. One way is to write the group of instruc ons as a separate procedure. 2. Another way we can use macros. Procedures: The procedure is a group of instruc ons stored as a separate program in the memory and it is called from the main program whenever required using CALL instruc on. For calling the procedure we have to store the return address (next instruc on address followed by CALL) onto the stack. At the end of the procedure RET instruc on used to return the execu on to the next instruc on in the main program by retrieving the address from the top of the stack. MICROPROCESSORS AND MICROCONTROLLERS Page 25 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Machine codes for the procedure instruc ons put only once in memory. The procedure can be deﬁned anywhere in the program using assembly direc ves PROC and ENDP. The four major ways of passing parameters to and from a procedure are: 1. In registers 2. In dedicated memory loca on accessed by name 3.With pointers passed in registers 4. With the stack The type of procedure depends on where the procedure is stored in the memory. If it is in the same code segment where the main program is stored the it is called near procedure otherwise it is referred to as far procedure. For near procedure CALL instruc on pushes only the IP register contents on the stack, since CS register contents remains unchanged for main program. But for Far procedure CALL instruc on pushes both IP and CS on the stack. Syntax: Procedure name PROC near instruc on 1 instruc on 2 RET Procedure name ENDP Example: near procedure: far procedure: ADD2 PROC near Procedures segment ADD AX,BX Assume CS : Procedures RET ADD2 PROC far ADD2 ENDP ADD AX,BX RET ADD2 ENDP Procedures ends MICROPROCESSORS AND MICROCONTROLLERS Page 26 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Depending on the characteris cs the procedures are two types 1. Re-entrant Procedures 2. Recursive Procedures Reentrant Procedures The procedure which can be interrupted, used and “reentered” without losing or wri ng over anything. Recursive Procedure A recursive procedure is procedure which calls itself. ALP for Finding Factorial of number using procedures CODE SEGMENT ASSUME CS:CODE START: MOV AX,7 CALL FACT MOV AH,4CH INT 21H FACT PROC NEAR MOV BX,AX DEC BX BACK: MUL BX DEC BX JNZ BACK RET ENDP CODE ENDS END START MICROPROCESSORS AND MICROCONTROLLERS Page 27 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Macros: A macro is a group of repe ve instruc ons in a program which are codiﬁed only once and can be used as many mes as necessary. A macro can be deﬁned anywhere in program using the direc ves MACRO and ENDM Each me we call the macro in a program, the assembler will insert the deﬁned group of instruc ons in pla ce of the call. The assembler generates machine codes for the group of instruc ons each me the macro is called. Using a macro avoids the overhead me involved in calling and returning from a procedure. Syntax of macro: macroname MACRO instruc on1 instruc on2.. ENDM Example: Read MACRO Display MACRO mov ah,01h mov dl,al int 21h Mov ah,02h ENDM int 21h ENDM ALP for Finding Factorial of number using procedures CODE SEGMENT ASSUME CS:CODE FACT MACRO MOV BX,AX DEC BX BACK: MUL BX DEC BX JNZ BACK ENDM START: MOV AX,7 FACT MOV AH,4CH INT 21H CODE ENDS END START Advantage of Procedure and Macros: Procedures: Advantages The machine codes for the group of instruc ons in the procedure only have to be put once. MICROPROCESSORS AND MICROCONTROLLERS Page 28 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Disadvantages Need for stack Overhead me required to call the procedure and return to the calling program. Macros: Advantages Macro avoids overhead me involving in calling and returning from a procedure. Disadvantages Genera ng in line code each me a macro is called is that this will make the program take up more memory than using a procedure. Diﬀerences between Procedures and Macros: PROCEDURES MACROS Accessed by CALL and RET mechanism during program Accessed by name given to macro when deﬁned during execu on assembly Machine code generated for instruc ons each me Machine code for instruc ons only put in memory once called Parameters are passed in registers, memory loca ons Parameters passed as part of statement which calls or stack macro Procedures uses stack Macro does not u lize stack A procedure can be deﬁned anywhere in program using A macro can be deﬁned anywhere in program using the the direc ves PROC and ENDP direc ves MACRO and ENDM Procedures takes huge memory for CALL (3 bytes each Length of code is very huge if macro’s are called for more me CALL is used) instruc on number of mes 8086 MEMORY INTERFACING: Most the memory ICs are byte oriented i.e., each memory loca on can store only one byte of data. The 8086 is a 16-bit microprocessor, it can transfer 16 -bit data. So in addi on to byte, word (16-bit) has to be stored in the memory. To implement this , the en re memory is divided into two memory banks: Ban k0 and Bank1. Bank0 is selected only when A0 is zero and Bank1 is selected only when BHE’ is zero. A0 is zero for all even addresses, so Bank0 is usually referred as even addressed memory bank. BHE’ is used to access higher order memory bank, referred to as odd addressed memory bank. MICROPROCESSORS AND MICROCONTROLLERS Page 29 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Every microprocessor based system has a memory system. Almost all systems contain two basic types of memory, read only memory (ROM) and random access memory (RAM) or read/write memory. ROM contains system so ware and p ermanent system data such as lookup tables, IVT..etc. RAM contains temporary data and applica on so ware. ROMs/PROMs/EPROMs are mapped to cover the CPU’s reset address, since these are non -vola le. When the 8086 is reset, the next instruc on is fetched from the memory loca on FFFF0H. So in the 8086 system the loca on FFFF0H must be in ROM loca on. Address Decoding Techniques 1. Absolute decoding 2. Linear decoding 3. Block decoding 1. Absolute Decoding: In the absolute decoding technique the memory chip is selected only for the speciﬁed logic level on the address lines: no other logic levels can select the chip. Below ﬁgure the memory interface with absolute decoding. Two 8K EPROMs ( 2764) are used to provide even and odd memory banks. Control signals BHE and A0 are use to enable output of odd and even memory banks respec vely. As each memory chip has 8K memory loca ons, thirteen address lines are required to address each loca ons, independently. MICROPROCESSORS AND MICROCONTROLLERS Page 30 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT All remaining address lines are used to generate an unique chip select signal. This address technique is normally used in large memory systems. Linear Decoding: In small system hardware for the decoding logic can be eliminated by using only required number of addressing lines (not all). Other lines are simple ignored. This technique is referred as linear decoding or par al decoding. Control signals BHE and Ao are used to enable odd and even memory banks, respec vely. Figure shows the addressing of 16K RAM (6264) with linear decoding. The address line A19 is used to select the RAM chips. When A19 is low, chip is selected, otherwise it is disabled. Th e status of A14 to A18 does not aﬀect the chip selec on logic. This gives you mul ple addresses (shadow addresses). This technique reduces the cost of decoding circuit, but it gas drawback of mul ple addresses. Block Decoding: In a microcomputer system the memory array is o en consists of several blocks of memory chips. Each block of memory requires decoding circuit. To avoid separate decoding for each memory block special decoder IC is used to generate chip select signal for each block. MICROPROCESSORS AND MICROCONTROLLERS Page 31 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Figure shows the Block decoding technique using 74138, 3:8 decoder Interfacing RAM, ROM, EPROM to 8086: The general procedure of sta c memory interfacing with 8086 1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is called ‘odd address memory bank’. The lower 8-bit bank is called ‘even address memory bank’. 2. Connect available memory address lines of memory chips with those of the microprocessor and also connect the RD and WR inputs to the corresponding processor control signals. 3. Connect the 16-bit data bus of memory bank with that of the microprocessor 8086. 4. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the required chip select signals for the odd and even memory banks. The CS of memory is derived from the output of the decoding circuit. Problem 1: Interface two 4Kx8 EPROM and two 4Kx8 RAM chips with 8086. Select suitable maps. Solu on: We know that, a er reset, the IP and CS are ini alized to form address FFFF 0H. Hence, this address must lie in the EPROM. The address of RAM may be selected anywhere in the 1MB address space of 8086, but we will select the RAM address such that the address map of the system is con nuous. MICROPROCESSORS AND MICROCONTROLLERS Page 32 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Memory Map Table Addre A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 ss 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H EPROM 8K X 8 FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 H FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 H RAM 8K X 8 FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H Total 8K bytes of EPROM need 13 address lines A0 -A12 (since z13 = 8K). Address lines A13 - A19 are used for decoding to generate the chip select. The 翿翿翿signal goes low when a transfer is at odd address or higher byte of data is to be accessed. Let us assume that the latched address, 翿翿翿and demul plexed data lines are readily available for interfacing. The memory system in this problem contains in total four 4K x 8 memory chips. The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data bus width. If A0 is 0, i.e., the address is even and is in RAM, then the lower RAM chip is selected indica ng 8-bit transfer at an even address. If A0 is i.e., the address is odd and is in RAM, the 翿翿翿goes low, the upper RAM chip is selected, further indica ng that the 8 - bit transfer is at an odd address. If the selected addresses are in ROM, the respec ve ROM chips are selected. If at a time A0 and 翿翿翿both are 0, both the RAM or ROM chips are selected, i.e., the data transfer is of 16 bits. The selec on of chips here takes place as shown in table below. MICROPROCESSORS AND MICROCONTROLLERS Page 33 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Memory Chip Selec on Table: Decoder I/P --> A2 A1 A0 Selec on/ Address/翿翿翿--> A13 A0 翿翿翿 Comment Word transfer on D0 - D15 0 0 0 Even and odd address in RAM Byte transfer on D7 - D0 0 0 1 Only even address in RAM Byte transfer on D8 - D15 0 1 0 Only odd address in RAM Word transfer on D0 - D15 1 0 0 Even and odd address in RAM Byte transfer on D7 - D0 1 0 1 Only even address in RAM Byte transfer on D8 - D15 1 1 0 Only odd address in ROM Problem2: Design an interface between 8086 CPU and two chips of 16K×8 EPROM and two chips of 32K×8 RAM. Select the star ng address of EPROM suitably. The RAM address must start at 00000 H. Solu on: The last address in the map of 8086 is FFFFF H. a er rese ng, the processor starts from FFFF0 H. hence this address must lie in the address range of EPROM. MICROPROCESSORS AND MICROCONTROLLERS Page 34 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT It is be er not to use a decoder to implement the above map because it is not con nuous, i.e. there is some unused address space between the last RAM address (0FFFF H) and the ﬁrst EPROM address (F8000 H). Hence the logic is implemented using logic gates. Problem3: It is required to interface two chips of 32K×8 ROM and four chips of 32K×8 RAM with 8086, according to following map. ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and RAM 2 D0000H - DFFFFH, RAM 3 and RAM 4 E0000H - EFFFFH. Show the implementa on of this memory system. Solu on: MICROPROCESSORS AND MICROCONTROLLERS Page 35 CPE 409: ASSEMBLY LANGUAGE PROGRAMMING CEG DEPARTMENT Methods of Interfacing I/O Devices Memory Mapping IO mapping 1. 20-bit addresses are provided for IO 1. 8-bit or 16-bit address are provided for IO devices. devices 2. The IO ports or peripherals can be treated 2. Only IN and OUT instruc ons can be used for like memory loca ons and so all data transfer between IO device and the instruc ons related to memory can be processor. used for data transfer. 3. In memory mapped ports, the data can be 3. In IO mapped ports, the data transfer can moved from any register to port and vice take only between the accumulator and the versa ports 4. When memory mapping is used for IO 4. When IO mapping is used for IO devices, devices, the full memory address space then the full address space can be used for cannot be used for addressing memory. addressing memory. MICROPROCESSORS AND MICROCONTROLLERS Page 36

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