CHED-Learning Module 05- ECEE0312 Solomon 2021 PDF

NGEC-Logic Circuit & Switching Theory LM05 -ECEE 0312 Learning Module 05 Synchronous Sequential Logic Knowledge...

NGEC-Logic Circuit & Switching Theory LM05 -ECEE 0312 Learning Module 05 Synchronous Sequential Logic Knowledge Area Code : BSEC Course Code : ECEE0312 Learning Module Code : LM05- ECEE0312 264  NGEC-Logic Circuit & Switching Theory Module Overview Introduction Hand-held devices, cell phones, navigation receivers, personal computers, digital cameras, personal media players, and virtually all electronic consumer products have the ability to send, receive, store, retrieve, and process information represented in a binary format. The technology enabling and supporting these devices is critically dependent on electronic components that can store information, i.e., have memory. This Module 05 examines the operation and control of these devices and their use in circuits and enables you to better understand what is happening in these devices when you interact with them. The digital circuits considered thus far have been combinational (Module 04)—their output depends only and immediately on their inputs—they have no memory, i.e., dependence on past values of their inputs. Sequential circuits, however, act as storage elements and have memory. They can store, retain, and then retrieve information when needed at a later time. Our treatment will distinguish sequential logic from combinational logic. A block diagram of a sequential circuit is shown in Fig. 5.1. It consists of a combinational circuit to which storage elements are connected to form a feedback path. Figure 5.1 : Sequential Circuit Block Diagram Source: “Digital Design” 5th ed. By Mano & Ciletti The storage elements are devices capable of storing binary information. The binary information stored in these elements at any given time defines the state of the sequential circuit at that time. The sequential circuit receives binary information from external inputs that, together with the present state of the storage elements, determine the binary value of the outputs. These external inputs also determine the condition for changing the state in the storage elements. The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements. The next state of the storage elements is also a function of external inputs and the present state. Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states. In contrast, the outputs of combinational logic depend only on the present values of the inputs. There are two main types of sequential circuits, and their classification is a function of the timing of their signals. A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time. The behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change. The storage elements commonly used in asynchronous sequential circuits are time-delay devices. The storage capability of a time-delay device varies with the time it takes for the signal to propagate 265  NGEC-Logic Circuit & Switching Theory through the device. In practice, the internal propagation delay of logic gates is of sufficient duration to produce the needed delay, so that actual delay units may not be necessary. In gate-type asynchronous systems, the storage elements consist of logic gates whose propagation delay provides the required storage. Thus, an asynchronous sequential circuit may be regarded as a combinational circuit with feedback. Because of the feedback among logic gates, an asynchronous sequential circuit may become unstable at times. The instability problem imposes many difficulties on the designer. These circuits will not be covered in this module. A synchronous sequential circuit employs signals that affect the storage elements at only discrete instants of time. Synchronization is achieved by a timing device called a clock generator, which provides a clock signal having the form of a periodic train of clock pulses. The clock signal is commonly denoted by the identifiers clock and clk. The clock pulses are distributed throughout the system in such a way that storage elements are affected only with the arrival of each pulse. In practice, the clock pulses determine when computational activity will occur within the circuit, and other signals (external inputs and otherwise) determine what changes will take place affecting the storage elements and the outputs. For example, a circuit that is to add and store two binary numbers would compute their sum from the values of the numbers and store the sum at the occurrence of a clock pulse. Synchronous sequential circuits that use clock pulses to control storage elements are called clocked sequential circuits and are the type most frequently encountered in practice. They are called synchronous circuits because the activity within the circuit and the resulting updating of stored values is synchronized to the occurrence of clock pulses. The design of synchronous circuits is feasible because they seldom manifest instability problems and their timing is easily broken down into independent discrete steps, each of which can be considered separately. (Mano & Ciletti, 2015)  Topic 01: Flipflops  Topic 02: Analysis of Clocked-Sequential Logic Circuit Learning Outcomes Analyze problems related to clocked sequential circuit using flip-flops. Minimum Technical Skills Requirement The learner should have a prior knowledge in simplification of Boolean function as well as don’t care conditions. Familiar also in NAND/NOR Gate implementation. Learning Management System BSEE 3A Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNDUx BSEE 3B Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDU5NzcwNTQz BSEE 3C Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNjQ1 266  NGEC-Logic Circuit & Switching Theory Duration  Topic 01: Flip-flops = 1.5 hours  Topic 02: Analysis of Clocked-Sequential Logic Circuit = 7.5 hours Delivery Mode Online learning (Synchronous) and Offsite learning (Asynchronous) Module Requirement with Rubrics The following criteria and the corresponding percentage shall be used to assess problem solving in quiz and take home activity as assessment tool or task. Criteria Description % Understanding Able to translate the thought of the problem into circuit 15% diagram or any visual drawing that signifies student’s understanding of the problem. Interpretation Able to establish what is asked in the problem and apply 25% appropriate mathematical equation/formula Execution Able to solve the problem through solutions with mathematical 60% strategies and have arrived at the correct answer TOTAL 100% 267  NGEC-Logic Circuit & Switching Theory Pre-Assessment Instruction: Select the best answer. Write the complete answer (do not include the letter) in a separate sheet of paper. Scanned copy or take a picture of your answer sheet and submit it to our google classroom where the pre-assessment is posted. Don’t forget to write your name at the upper left most part of your answer sheet. Use A4 or short bond paper. 1. Memory elements in clocked sequential circuits are called a. latches b. flip-flop c. signals d. gates 2. The state of flip-flop can be switched by changing its a. input signal b. output signal c. momentary signals d. all signals 3. The major difference between various types of flip-flops are a. output that they generate b. input that they posses c. gates d. both a and b 4. The flip-flops can be constructed with two a. NAND gates b. XOR gates c. AND gates d. NOT gates 5. The momentary change in the state of flip-flop is called a. feedback path b. tri state c. signals d. trigger 6. Clocked flip-flops are triggered by a. feedback path b. pulses c. signals d. clear 7. Sequential circuits are 268  NGEC-Logic Circuit & Switching Theory a. Synchronous b. Asynchronous c. signals d. both a and b 8. The behavior of sequential circuits are determined by the state of their a. clock b. pulses c. flip-flops d. trigger 9. JK Master-slave flip-flops are constructed with a. NAND gates b. OR gates c. AND gates d. NOT gates 10. A synchronous sequential circuit is made up of a. combinational gates b. flip-flops c. latches d. both a and b 269  Packet 01 LM05-ECEE NGEC-Logic Circuit & Switching Theory 0312 Learning Module 05 Synchronous Sequential Logic Learning Packet 01 Flip-Flops Knowledge Area Code : BSEC Course Code : ECEE0312 Learning Module Code : LM05-ECEE0312 Learning Packet Code : LM05-ECEE0312-01 270  NGEC-Logic Circuit & Switching Theory Learning Packet 01 Flip-flops Introduction The storage elements (memory) used in clocked sequential circuits are called flipflops. A flip-flop is a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-flop is either 0 or 1. A sequential circuit may use many flip-flops to store as many bits as necessary. The block diagram of a synchronous clocked sequential circuit is shown in Fig. 5.2(a). The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both). The value that is stored in a flip-flop when the clock pulse occurs is also determined by the inputs to the circuit or the values presently stored in the flip-flop (or both). The new value is stored (i.e., the flip-flop is updated) when a pulse of the clock signal occurs. Prior to the occurrence of the clock pulse, the combinational logic forming the next value of the flip-flop must have reached a stable value. Figure 5.2: Block Diagram & Timing Diagram of Synchronous Squential Circuit Source: “Digital Design” 5th ed. By Mano & Ciletti Consequently, the speed at which the combinational logic circuits operate is critical. If the clock (synchronizing) pulses arrive at a regular interval, as shown in the timing diagram in Fig. 5.2 , the combinational logic must respond to a change in the state of the flip-flop in time to be updated before the next pulse arrives. Propagation delays play an important role in determining the minimum interval between clock pulses that will allow the circuit to operate correctly. A change in state of the flip-flops is initiated only by a clock pulse transition—for example, when the value of the clock signals changes from 0 to 1. When a clock pulse is not active, the feedback loop between the value stored in the flip-flop and the value formed at the input to the flip-flop is effectively broken because the flipflop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the transition from one state to the next occurs only at predetermined intervals dictated by the clock pulses. (Mano & Ciletti, 2015) 271  NGEC-Logic Circuit & Switching Theory Objectives At the end of the discussion of the course packet, the students will be able to:  Understand the principle and operation of different types of flip-flops. Learning Management System BSEE 3A Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNDUx BSEE 3B Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDU5NzcwNTQz BSEE 3C Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNjQ1 Duration  Topic 01: Flip-flops = 1.5 hours (1 hour self-directed learning and 0.5 hour assessment) Delivery Mode Offsite learning (Asynchronous) Course Packet Requirement with Rubrics Course Packet Discussion Forum / Virtual Recitation You are required to post your idea or opinion based from the argument posted by the faculty on Google Classroom stream page. This is an open online discussion where students in this class are encourage to participate and post their idea open-mindedly. The following criteria and the corresponding percentage shall be used to evaluate the Course Packet Discussion Forum / Virtual Recitation ONLINE DISCUSSION RUBRICS Criteria SCORE 10 30 60 80 100 Promptness Seldom Sometimes Often respond More often Consistently and initiative respond to respond to to post and respond to post respond to post in (30%) discussion discussion and some posting and all posting less than 12 and late most of the are within 24 are less than 24 hours. posting. posting are hours hours Demonstrate self- late. initiative. Delivery of Utilizes poor Errors in Few Most of the post All post are Post spelling and spelling and grammatical are grammatically grammatically (20%) grammar in grammar and spelling correct with correct with no all post; All evidenced in errors are noted rarely spelling errors. post appear several post. in some post. misspelling. “hasty” Relevance of Rarely post Rarely post Most posts are Frequently posts Consistently Post topics and topics and short in length topic that are posts topics (50%) always offer no and offer slight related to related to the makes further insight insight into the discussion subject matter. irrelevant into the topic topic with quite content and Cites additional 272  NGEC-Logic Circuit & Switching Theory remarks to with relevant to the prompts further references related the topic. occasional off- subject matter. discussion. to topic to clarify topics the idea. Course Packet Problem Solving Exercises The following criteria and the corresponding percentage shall be used to assess the course packet problem solving exercises. Criteria Description % Able to translate the thought of the problem into circuit diagram 15% Understanding or any visual drawing that signifies student’s understanding of the problem. Able to establish what is asked in the problem and apply 25% Interpretation appropriate mathematical equation/formula Able to solve the problem through solutions with mathematical 60% Execution strategies and have arrived at the correct answer 100% TOTAL Readings  Please read the e-book of Digital Design, 5th ed. by Morris Mano and Michael Ciletti at docs.google.com of the topic entitled “Analysis & Design of Combinational Logic Circuit”  Study the supplemental reading at the following website to further understand the lesson. https://www.electronics-course.com https://www.tutorialspoint.com/digital_circuits/digital_circuits_flip_flops.htm Lesson Proper A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states. The major differences among various types of storage elements are in the number of inputs they possess and in the manner in which the inputs affect the binary state. Points to Remember: Two type of storage elements: 1. Latch Storage elements that 2. Flip-flop operate with signal levels (rather than signal Latches are said to be level sensitive devices; flip-flops are edge transitions) are referred -sensitive devices. The two types of storage elements are relatedto as latches ; those because latches are the basic circuits from which all flip-flopscontrolled are by a clock constructed. Although latches are useful for storing binary transition information and for the are flip-flops. design of asynchronous sequential circuits, they are not practical for use as storage elements in synchronous sequential circuits. Because they are the building blocks of flip-flops, however, we will consider the fundamental storage mechanism used in latches before considering flip-flops. SR LATCH The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and two inputs labeled S for set and R for reset. The SR latch constructed with two cross-coupled NOR gates is shown in F ig. 5.3. 273  NGEC-Logic Circuit & Switching Theory Figure 5.3: SR Latch(NOR) Logic Diagram & Function Table Source: “Digital Design” 5th ed by Mano & Ciletti Two useful states of SR Latch: 1. Set State: When output Q = 1 and Q’ = 0, the latch is said to be in the set state. 2. Reset State: When Q = 0 and Q’ = 1, it is in the reset state. Outputs Q and Q’ are normally the complement of each other. However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 (rather than be mutually complementary) occurs. If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1 is forbidden. Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed. The application of a momentary 1 to the S input causes the latch to go to the set state. The S input must go back to 0 before any other changes take place, in order to avoid the occurrence of an undefined next state that results from the forbidden input condition. As shown in the function table of Fig.5.3(b), two input conditions cause the circuit to be in the set state. The first condition (S = 1, R = 0) is the action that must be taken by input S to bring the circuit to the set state. Removing the active input from S leaves the circuit in the same state. After both inputs return to 0, it is then possible to shift to the reset state by momentary applying a 1 to the R input. The 1 can then be removed from R, whereupon the circuit remains in the reset state. Thus, when both inputs S and R is equal to 0, the latch can be in either the set or the reset state, depending on which input was most recently a 1. If a 1 is applied to both the S and R inputs of the latch, both outputs go to 0. This action produces an undefined next state, because the state that results from the input transitions depends on the order in which they return to 0. It also violates the requirement that outputs be the complement of each other. In normal operation, this condition is avoided by making sure that 1’s is not applied to both inputs simultaneously. 274  NGEC-Logic Circuit & Switching Theory Figure 5.4: SR Latch (NAND) Logic Diagram & Function Table Source: “Digital Design” 5th ed by Mano & Ciletti The SR latch with two cross-coupled NAND gates is shown in Fig. 5.4. It operates with both inputs normally at 1, unless the state of the latch has to be changed. The application of 0 to the S input causes output Q to go to 1, putting the latch in the set state. When the S input goes back to 1, the circuit remains in the set state. After both inputs go back to 1, we are allowed to change the state of the latch by placing a 0 in the R input. This action causes the circuit to go to the reset state and stay there even after both inputs return to 1. The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the same time, an input combination that should be avoided In comparing the NAND with the NOR latch, note that the input signals for the NAND require the complement of those values used for the NOR latch. Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an S’R’ latch. The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in their complement form to activate the circuit. An SR latch with a control input is shown in Fig. 5.5. It consists of the basic SR latch (NAND) and two additional NAND gates at the input. Figure 5.5: SR Latch (Control Input) Logic Diagram & Function Table Source: “Digital Design” 5th ed by Mano & Ciletti The control input En acts as an enable signal for the other two inputs. The outputs of the NAND gates stay at the logic-1 level as long as the enable signal remains at 0. This is the quiescent condition for the SR latch. When the enable input goes to 1, information from the S or R input is allowed to affect the latch. The set state is reached with S = 1, R = 0, and En = 1 (active-high enabled). To change to the reset 275  NGEC-Logic Circuit & Switching Theory state, the inputs must be S = 0, R = 1, and En = 1. In either case, when En returns to 0, the circuit remains in its current state. The control input disables the circuit by applying 0 to En, so that the state of the output does not change regardless of the values of S and R. Moreover, when En = 1 and both the S and R inputs are equal to 0, the state of the circuit does not change. These conditions are listed in the function table in Fig 5.5(b). An indeterminate condition occurs when all three inputs are equal to 1. This condition places 0’s on both inputs of the basic SR latch, which puts it in the undefined state. When the enable input goes back to 0, one cannot conclusively determine the next state, because it depends on whether the S or R input goes to 0 first. This indeterminate condition makes this circuit difficult to manage, and it is seldom used in practice. Points to Remember: The SR latch is an important circuit D LATCH (Transparent Latch) because other useful latches and flip-flops are One way to eliminate the undesirable condition of the indeterminate constructedstate frominit. the SR latch is to ensure that inputs S and R is never equal to 1 at the same time. This is done in the D latch, shown in Fig.5.6. Figure 5.6: D Latch Block Diagram & Function Table Source: “Digital Design” 5th ed by Mano & Ciletti This latch has only two inputs: D (data) and En (enable). The D input goes directly to the S input, and its complement is applied to the R input. As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level and the circuit cannot change state regardless of the value of D. The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state. The D latch receives that designation from its ability to hold data in its internal storage. It is suited for use as a temporary storage for binary information between a unit and its environment. The binary information present at the data input of the D latch is transferred to the Q output when the enable input is asserted. The output follows changes in the data input as long as the enable input is asserted. This situation provides a path from input D to the output, and for this reason, the circuit is often called a transparent latch. When the enable input signal is de- 276  NGEC-Logic Circuit & Switching Theory asserted, the binary information that was present at the data input at the time the transition occurred is retained (i.e., stored) at the Q output until the enable input is asserted again. Note that an inverter could be placed at the enable input. Then, depending on the physical circuit, the external enabling signal will be a value of 0 (active low) or 1 (active high). Figure 5.7: Graphic Symbol of Different Latches Source: “Digital Design” 5th ed by Mano & Ciletti The graphic symbols for the various latches are shown in Fig. 5.7 above. A latch is designated by a rectangular block with inputs on the left and outputs on the right. One output designates the normal output, and the other (with the bubble designation) designates the complement output. The graphic symbol for the SR latch has inputs S and R indicated inside the block. In the case of a NAND gate latch, bubbles are added to the inputs to indicate that setting and resetting occur with a logic-0 signal. The graphic symbol for the D latch has inputs D and En indicated inside the block. FLIP-FLOPS The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger, and the transition it causes is said to trigger the flip-flop. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic-1 level. As long as the pulse input remains at this level, any changes in the data input will change the output and the state of the latch. Flip-flop circuits are constructed in such a way as to make them operate properly when they are part of a sequential circuit that employs a common clock. The problem with the latch is that it responds to a change in the level of a clock pulse. Figure 5.8: Clock Response in Latch & Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti As shown in Fig. 5.8(a), a positive level response in the enable input allows changes in the output when the D input changes while the clock pulse stays at logic 1. The key to the proper operation of a flip-flop is to trigger it only during a signal transition. This 277  NGEC-Logic Circuit & Switching Theory can be accomplished by eliminating the feedback path that is inherent in the operation of the sequential circuit using latches. A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0. As shown in F ig.5.8(b) & Fig 5.8(c), the positive transition is defined as the positive edge and the negative transition as the negative edge. There are two ways that a latch can be modified to form a flip-flop. 1. One way is to employ two latches in a special configuration that isolates the output of the flip-flop and prevents it from being affected while the input to the flip-flop is changing. 2. Another way is to produce a flip-flop that triggers only during a signal transition (from 0 to 1 or from 1 to 0) of the synchronizing signal (clock) and is disabled during the rest of the clock pulse. Edge-Triggered D Flip-flop The construction of a D flip-flop with two D latches and an inverter is shown in F ig. 5.9. Figure 5.9: Master-Slave D Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative edge of the synchronizing or controlling clock (designated as Clk). When the clock is 0, the output of the inverter is 1. The slave latch is enabled, and its output Q is equal to the master output Y. The master latch is disabled because Clk = 0. When the input pulse changes to the logic-1 level, the data from the external D input are transferred to the master. The slave, however, is disabled as long as the clock remains at the 1 level, because the enable input is equal to 0. Any change in the input changes the master output at Y, but cannot affect the slave output. When the clock pulse returns to 0, the master is disabled and is isolated from the D input. At the same time, the slave is enabled and the value of Y is transferred to the output of the flip-flop at Q Points to Remember: The behavior of the master–slave flip-flop just described dictates A change in the output of that: the flip-flop can be (1) the output may change only once, triggered only by and (2) a change in the output is triggered by the negative edge of during the transition of the clock from 1 to 0. 278  NGEC-Logic Circuit & Switching Theory the clock, and (3) the change may occur only during the clock’s negative level. It is also possible to design the circuit so that the flip-flop Points to Remember: output changes on the positive edge of the clock. This happens in a flip-flop that has an additional inverter The value that is produced between the Clk terminal and the junction between the other at the output of the flip-flop inverter and input En of the master latch. Such a flip-flop is is the value that was triggered with a negative pulse, so that the negative edge of stored in the master stage the clock affects the master and the positive edge affects the immediately before the slave and the output terminal. negative edge occurred. Figure 5.10: D-Type Positive-edge Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig.5.10. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. This causes the output to remain in its present state. Input D may be equal to 0 or 1. If D = 0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset state, making Q = 0. If there is a change in the D input while Clk = 1, terminal R remains at 0 because Q is 0. Thus, the flip-flop is locked out and is unresponsive to further changes in the input. When the clock returns to 0, R goes to 1, placing the output latch in the quiescent condition without changing the output. Similarly, if D = 1 when Clk goes from 0 to 1, S changes to 0. This causes the circuit to go to the set state, making Q = 1. Any change in D while Clk = 1 does not affect the output. To summarize: 1. When the input clock in the positive-edge-triggered flip-flop makes a positive transition, the value of D is transferred to Q. 2. A negative transition of the clock (i.e., from 1 to 0) does not affect the output, nor is the output affected by changes in D when Clk is in the steady logic-1 level or the logic-0 level. Hence, this type of flip-flop responds to the transition from 0 to 1 and nothing else. Timing response: 1. setup time - a minimum time during which the D input Points to Remember: must be maintained at a constant value prior to the occurrence of the clock transition. The timing of the response of a flip-flop to input data and to the clock must be taken into consideration279 when one is using edge- triggered flip-flops.  NGEC-Logic Circuit & Switching Theory 2. hold time - a minimum time during which the D input must not change after the application of the positive transition of the clock. 3. propagation delay time - is defined as the interval between the trigger edge and the stabilization of the output to a new stat Figure 5.11: Graphic Symbol for Edge-triggered D Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti The graphic symbol for the edge-triggered D flip-flop is shown in Fig.5.11. It is similar to the symbol used for the D latch, except for the arrowhead-like symbol in front of the letter Clk, designating a dynamic input. The dynamic indicator (>) denotes the fact that the flip-flop responds to the edge transition of the clock. A bubble outside the block adjacent to the dynamic indicator designates a negative edge for triggering the circuit. The absence of a bubble designates a positive-edge response. Very large-scale integration circuits contain several thousands of gates within one package. Circuits are constructed by interconnecting the various gates to provide a digital system. Each flip-flop is constructed from an interconnection of gates. The most economical and efficient flip-flop constructed in this manner is the edge-triggered D flipflop, because it requires the smallest number of gates. Other types of flip-flops can be constructed by using the D flip-flop and external logic. Other Flip-flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are 1. JK flip-flops 2. T flip-flops There are three operations that can be performed with a flip-flop: 1. Set it to 1 2. Reset it to 0, or 3. Complement its output. With only a single input, the D flip-flop can set or reset the output, depending on the value of the D input immediately before the clock transition. Synchronized by a clock signal, the JK flip-flop has two inputs and performs all three operations. 280  NGEC-Logic Circuit & Switching Theory Figure 5.12: JK Flip-flop Circuit Diagram and Graphic Symbol Source: “Digital Design” 5th ed by Mano & Ciletti The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates is shown in Fig. 5.12(a). The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. This can be verified by investigating the circuit applied to the D input: D = JQ’ + K’Q When J = 1 and K = 0, D = Q + Q = 1, so the next clock edge sets the output to 1. When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0. When both J = K = 1 and D = Q’, the next clock edge complements the output. When both J = K = 0 and D = Q, the clock edge leaves the output unchanged. The graphic symbol for the JK flip-flop is shown in F ig.5.12(b). It is similar to the graphic symbol of the D flip-flop, except that now the inputs are marked J and K. Figure 5.13: T Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti The T(toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together. This is shown in F ig.5.13(a). When T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a clock edge complements the output. The complementing flip-flop is useful for designing binary counters. The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as shown in Fig.5.13(b). The expression for the D input is D = T ⊕ Q = TQ’ + T’Q When T = 0, D = Q and there is no change in the output. When T = 1, D = Q’ and the output complements. The graphic symbol for this flip-flop has a T symbol in the input as shown in Fig.5.13(c ). Characteristic Table 281  NGEC-Logic Circuit & Switching Theory A characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form. The characteristic tables of three types of flip-flops are presented in Table 5.1. They define the next state (i.e., the state that results from a clock transition) as a function of the inputs and the present state. Where: Q ( t) = refers to the present state (i.e., the state present prior to the application of a clock edge). Q(t + 1) = refers as the next state one clock period later. Note that the clock edge input is not included in the characteristic table, but is implied to occur between times t and (t + 1). Thus, Q(t) denotes the state of the flip-flop immediately before the clock edge, and Q(t + 1) denotes the state that results from the clock transition. Figure 5.13: Flip-flops Characteristic Table Source: “Digital Design” 5th ed by Mano & Ciletti JK Flip-flop Characteristic Table The characteristic table for the JK flip-flop shows that the next state is equal to the present state when inputs J and K are both equal to 0. This condition can be expressed as Q(t + 1) = Q(t), indicating that the clock produces no change of state. When K = 1 and J = 0, the clock resets the flip-flop and Q(t + 1) = 0. With J = 1 and K = 0, the flip- flop sets and Q(t + 1) = 1. When both J and K are equal to 1, the next state changes to the complement of the present state, a transition that can be expressed as Q(t + 1) = Q’(t). D Flip-flop Characteristic Table The next state of a D flip-flop is dependent only on the D input and is independent of the present state. This can be expressed as Q(t + 1) = D. It means that the next-state value is equal to the value of D. Note that the D flip-flop does not have a “no-change” condition. Such a condition can be accomplished either by disabling the clock or by operating the clock by having the output of the flip-flop connected into the D input. 282  NGEC-Logic Circuit & Switching Theory Either method effectively circulates the output of the flip-flop when the state of the flip- flop must remain unchanged. T Flip-flop Characteristic Table The characteristic table of the T flip-flop has only two conditions: When T = 0, the clock edge does not change the state; when T = 1, the clock edge complements the state of the flip-flop. Characteristic Equations The logical properties of a flip-flop, as described in the characteristic table, can be expressed algebraically with a characteristic equation. D Flip-flop Characteristic Equation For the D flip-flop, we have the characteristic equation, Q(t + 1) = D which states that the next state of the output will be equal to the value of input D in the present state. JK Flip-flop Characteristic Equation The characteristic equation for the JK flip-flop can be derived from the characteristic table or from the circuit of Fig.5.12. Q(t + 1) = JQ’ + K’Q where Q is the value of the flip-flop output prior to the application of a clock edge. T Flip-flop Characteristic Equation The characteristic equation for the T flip-flop is obtained from the circuit of Fig.5.1: Q(t + 1) = T ⊕ Q = TQ’ + T’Q Direct Input Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state independently of the clock. The input that sets the flip-flop to 1 is called preset or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. When power is turned on in a digital system, the state of the flip-flops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation. 283  NGEC-Logic Circuit & Switching Theory Figure 5.14: D Flip-flop with Asynchronous Reset Source: “Digital Design” 5th ed by Mano & Ciletti A positive-edge-triggered D flip-flop with active-low asynchronous reset is shown in Fig 5.14. The circuit diagram is the same as the one in Fig.5.10, except for the additional reset input connections to three NAND gates. When the reset input is 0, it forces output Q’ to stay at 1, which, in turn, clears output Q to 0, thus resetting the flip-flop. Two other connections from the reset input ensure that the S input of the third SR latch stays at logic 1 while the reset input is at 0, regardless of the values of D and Clk. The graphic The graphic symbol for the D flip-flop with a direct reset has an additional input marked with R. The bubble along the input indicates that the reset is active at the logic-0 level. Flip-flops with a direct set use the symbol S for the asynchronous set input. The function table specifies the operation of the circuit. When R = 0, the output is reset to 0. This state is independent of the values of D or Clk. Normal clock operation can proceed only after the reset input goes to logic 1. The clock at Clk is shown with an upward arrow to indicate that the flip-flop triggers on the positive edge of the clock. The value in D is transferred to Q with every positive-edge clock signal, provided that R = 1. Course Packet Discussion Forum (Virtual Recitation) Instruction: Post your answer in Google class stream page where this question is posted, on or before the agreed deadline of submission. You may cite additional references to clarify your idea. “Differentiate D Flip-flops, JK Flip-flops and T Flip-flops in terms of its operation based from its respective characteristic table and characteristic equation? “ 284  NGEC-Logic Circuit & Switching Theory Activity Sheet 15 PROBLEM SOLVING EXERCISES Instruction: Show the complete solution and box your final answer. This is a collaborative learning exercises, therefore, submit only one (1) answer per group. Write in your answer sheet all the names of the group members who participated in this activity, scanned copy or take a picture of your answer and submit it to our google classroom classwork where this activity is posted. Submit this on or before the agreed deadline of submission. (Total = 100 points) 1. The D latch of Fig.5.6 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (20 points each) (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Fig.5.6 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output). 2. Show that the characteristic equation for the complement output of a JK flip- flop is Q’(t + 1) = J’Q’ + KQ (40 points) 285  NGEC-Logic Circuit & Switching Theory Learner’s Feedback Form Name of Student: ___________________________________________________ Program : ___________________________________________________ Year Level : ___________ Section : ___________ Faculty : ___________________________________________________ Schedule : ___________________________________________________ Learning Packet : Number : _________ Title : ______________________ How do you feel about the topic or concept presented? □ I completely get it. □ I’m struggling. □ I’ve almost got it. □ I’m lost. In what particular portion of this learning packet, you feel that you are struggling or lost? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ Did you raise your concern to you instructor? □ Yes □ No If Yes, what did he/she do to help you? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ If No, state your reason? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ To further improve this learning packet, what part do you think should be enhanced? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ How do you want it to be enhanced? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ 286  Course Packet LM05-ECEE 02 NGEC-Logic Circuit & Switching Theory 0312 Learning Module 05 Synchronous Sequential Logic Learning Packet 02 Analysis of Clocked- Sequential Circuit Knowledge Area Code : BSEC Course Code : ECEE0312 Learning Module Code : LM05-ECEE0312 Learning Packet Code : LM05-ECEE0312-02 287  NGEC-Logic Circuit & Switching Theory Learning Packet 02 Analysis of Clocked-Sequential Circuit Introduction Introduction Analysis describes what a given circuit will do under certain operating conditions. The behavior of a clocked sequential circuit is determined from the inputs, the outputs, and the state of its flip-flops. The outputs and the next state are both a function of the inputs and the present state. The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe the behavior of the sequential circuit. These expressions must include the necessary time sequence, either directly or indirectly. (Mano & Ciletti, 2015) Objectives At the end of the discussion of the course packet, the students will be able to: 1. Analyze clocked-sequential logic circuits. 2. Solve problems related to clocked-sequential logic circuits Learning Management System BSEE 3A Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNDUx BSEE 3B Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDU5NzcwNTQz BSEE 3C Google Classroom Link: https://classroom.google.com/u/2/c/MzgzMDUzMzYwNjQ1 Duration Topic 02: Analysis of Clocked-Sequential Logic Circuit = 7.5 hours (6 hours combination of real-time online discussion and independent learning and 1.5 hours assessment) Delivery Mode Online Learning (Synchronous) & Offsite Learning (Asynchronous) Course Packet Requirement with Rubrics Course Packet Discussion Forum / Virtual Recitation You are required to post your idea or opinion based from the argument posted by the faculty on Google Classroom stream page. This is an open online discussion where students in this class are encourage to participate and post their idea open-mindedly.  NGEC-Logic Circuit & Switching Theory The following criteria and the corresponding percentage shall be used to assess Course Packet Discussion Forum / Virtual Recitation ONLINE DISCUSSION RUBRICS Criteria SCORE 10 30 60 80 100 Promptness Seldom Sometimes Often respond to More often Consistently and initiative respond to respond to post and some respond to post respond to post (30%) discussion discussion and posting are and all posting in less than 12 and late most of the within 24 hours are less than 24 hours. posting. posting are late. hours Demonstrate self-initiative. Delivery of Utilizes poor Errors in Few Most of the post All post are Post spelling and spelling and grammatical and are grammatically (20%) grammar in grammar spelling errors grammatically correct with no all post; All evidenced in are noted in correct with spelling errors. post appear several post. some post. rarely “hasty” misspelling. Relevance of Rarely post Rarely post Most posts are Frequently posts Consistently Post topics and topics and offer short in length topic that are posts topics (50%) always no further and offer slight related to related to the makes insight into the insight into the discussion subject matter. irrelevant topic with topic with quite content and Cites additional remarks to occasional off- relevant to the prompts further references the topic. topics subject matter. discussion. related to topic to clarify the idea. Course Packet Problem Solving Exercises The following criteria and the corresponding percentage shall be used to assess the course packet problem solving exercises. Criteria Description % Understanding Able to translate the thought of the problem into circuit 15% diagram or any visual drawing that signifies student’s understanding of the problem. Interpretation Able to establish what is asked in the problem and apply 25% appropriate mathematical equation/formula Execution Able to solve the problem through solutions with mathematical 60% strategies and have arrived at the correct answer TOTAL 100% Readings 1. Please read the e-book of Digital Design, 5th ed. by Morris Mano and Micahel Cilletti at docs.google.com of the topic entitled “ Analysis of Clocked-Sequential Logic Circuit” 2. Please study the following supplemental readings on Analysis of Clocked- Sequential Logic Circuit to further understand the lesson. https://www.slideshare.net/NaimKidwai/clocked-sequential-circuit-analysis-and- design http://pami.uwaterloo.ca/~basir/ECE124/Sync_Circuit_Analysis_Design.pdf 3. Watch the video presentation on the analysis of clocked-sequential logic circuit at https://www.youtube.com/watch?v=6jteVyUcAQU Lesson Proper 289  NGEC-Logic Circuit & Switching Theory A logic diagram is recognized as a clocked sequential circuit if it includes flip-flops with clock inputs. The flip-flops may be of any type, and the logic diagram may or may not include combinational logic gates. In this section, we introduce an algebraic representation for specifying the next-state condition in terms of the present state and inputs. A state table and state diagram are then presented to describe the behavior of the sequential circuit. Another algebraic representation is introduced for specifying the logic diagram of sequential circuits. Examples are used to illustrate the various procedures. State Equation The behavior of a clocked sequential circuit can be described algebraically by means of state equations. A state equation (also called a transition equation) specifies the next state as a function of the present state and inputs. Consider the sequential circuit shown in Fig.5.15. Figure 5.15: Sequential Circuit Source: “Digital Design” 5th ed by Mano & Ciletti It consists of two D flip-flops A and B, an input x and an output y. Since the D input of a flip-flop determines the value of the next state (i.e., the state reached after the clock transition), it is possible to write a set of state equations for the circuit: A(t + 1) = A(t)x(t) + B(t)x(t) B(t + 1) = A’(t)x(t) A state equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation, with (t + 1), denotes the next state of the flip-flop one clock edge later. The right side of the equation is a Boolean expression that specifies the present state and input conditions that make the next state equal to 1. Since all the variables in the Boolean expressions are a function of the present state, we can omit the designation (t) after each variable for convenience and can express the state equations in the more compact form A(t + 1) - Ax + Bx B(t + 1) – A’x 290  NGEC-Logic Circuit & Switching Theory The Boolean expressions for the state equations can be derived directly from the gates that form the combinational circuit part of the sequential circuit, since the D values of the combinational circuit determine the next state. Similarly, the present-state value of the output can be expressed algebraically as y(t) = [A(t) + B(t)]x’(t) By removing the symbol (t) for the present state, we obtain the output Boolean equation: y = (A + B)x’ State Table The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called a transition table). The state table for the circuit of Fig.5.15 is shown in Table 5.2. Table 5.2: State Table for the Circuit in Fig 5.15 Source: “Digital Design” 5th ed by Mano & Ciletti The table consists of four sections labeled present state, input, next state, and output. Where:  present-state section = shows the states of flip-flops A and B at any given time t.  input section = gives a value of x for each possible present state.  next-state section = shows the states of the flip-flops one clock cycle later, at time t + 1.  output section = gives the value of y at time t for each present state and input condition. The derivation of a state table requires listing all possible binary combinations of present states and inputs. In this case, we have eight binary combinations from 000 to 111. The next-state values are then determined from the logic diagram or from the state equations. The next state of flip-flop A must satisfy the state equation: A(t + 1) = Ax + Bx The next-state section in the state table under column A has three 1’s where the present state of A and input x are both equal to 1 or the present state of B and input x are both equal to 1. Similarly, the next state of flip-flop B is derived from the state equation B(t + 1) = A’x and is equal to 1 when the present state of A is 0 and input x is equal to 1. The output column is derived from the output equation y = Ax’ + Bx’ The state table of a sequential circuit with D- type flip-flops is obtained by the same procedure outlined in the previous example. Generally, 291  NGEC-Logic Circuit & Switching Theory 1. A sequential circuit with m flipflops and n inputs needs 2m+n rows in the state table. 2. The binary numbers from 0 through 2 m+n - 1 are listed under the present-state and input columns. 3. The next-state section has m columns, one for each flip-flop. 4. The binary values for the next state are derived directly from the state equations. 5. The output section has as many columns as there are output variables. 6. Its binary value is derived from the circuit or from the Boolean function in the same manner as in a truth table. It is sometimes convenient to express the state table in a slightly different form having only three sections:  present state  next state  output The input conditions are enumerated under the next-state and output sections. The state table of Table 5.2 is repeated in Table 5.3 in this second form. Table 5.3: Second Form of State Table for Fig 5.15 Source: “Digital Design” 5th ed by Mano & Ciletti For each present state, there are two possible next states and outputs, depending on the value of the input. One form may be preferable to the other, depending on the application. State Diagram The information available in a state table can be represented graphically in the form of a state diagram. In this type of diagram, a state is represented by a circle, and the (clock- triggered) transitions between states are indicated by directed lines connecting the circles. 292  NGEC-Logic Circuit & Switching Theory Input / Output State State The state diagram of the sequential circuit of Fig. 5.15 is shown in Fig. 5.16. Figure 5.16: State Diagram of the Circuit in Fig 5.15 Source: “Digital Design” 5th ed by Mano & Ciletti The state diagram provides the same information as the state table and is obtained directly from Table 5.2 or Table 5.3. The binary number inside each circle identifies the state of the flip-flops. The directed lines are labeled with two binary numbers separated by a slash. The input value during the present state is labeled first, and the number after the slash gives the output during the present state with the given input. (It is important to remember that the bit value listed for the output along the directed line occurs during the present state and with the indicated input, and has nothing to do with the transition to the next state.) For example, the directed line from state 00 to 01 is labeled 1/0, meaning that when the sequential circuit is in the present state 00 to next state 01, the input is 1, the output is 0. After the next clock cycle, the circuit goes to the next state, 01. If the input changes to 0, then the output becomes 1, but if the input remains at 1, the output stays at 0. This information is obtained from the state diagram along the two directed lines emanating from the circle with state 01. A directed line connecting a circle with itself indicates that no change of state occurs. The steps presented in this example are summarized below: Circuit diagram →State Equations → State Table → State Diagram Comparison between State Table and State Diagram:  There is no difference between a state table and a state diagram, except in the manner of representation.  The state table is easier to derive from a given logic diagram and the state equation.  The state diagram follows directly from the state table.  The state diagram gives a pictorial view of state transitions and is the form more suitable for human interpretation of the circuit’s operation For example, the state diagram of Fig.5.16 clearly shows that, starting from state 00, the output is 0 as long as the input stays at 1. The first 0 input after a string of 293  NGEC-Logic Circuit & Switching Theory 1’s gives an output of 1 and transfers the circuit back to the initial state, 00. The machine represented by this state diagram acts to detect a zero in the bit stream of data. It corresponds to the behavior of the circuit in Fig.5.15. Other circuits that detect a zero in a stream of data may have a simpler circuit diagram and state diagram. Flip-flop Input Equations The logic diagram of a sequential circuit consists of flip-flops and gates. The interconnections among the gates form a combinational circuit and may be specified algebraically with Boolean expressions. The knowledge of the type of flip-flops and a list of the Boolean expressions of the combinational circuit provide the information needed to draw the logic diagram of the sequential circuit. The part of the combinational circuit that generates external outputs is described algebraically by a set of Boolean functions called output equations. The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean functions called flip-flop input equations (or, sometimes, excitation equations). We will adopt the convention of using the flip-flop input symbol to denote the input equation variable and a subscript to designate the name of the flip-flop output. For example, the following input equation specifies an OR gate with inputs x and y connected to the D input of a flip-flop whose output is labeled with the symbol Q: DQ = x + y The sequential circuit of Fig. 5.15 consists of two D flip-flops A and B, an input x, and an output y. The logic diagram of the circuit can be expressed algebraically with two flip-flop input equations and an output equation: DA = Ax + Bx DB = A’x y = (A + B)x’ The three equations provide the necessary information for drawing the logic diagram of the sequential circuit.  The symbol DA specifies a D flip-flop labeled A.  The symbol DB specifies a second D flip-flop labeled B.  The Boolean expressions associated with these two variables and the expression for output y specify the combinational circuit part of the sequential circuit. The flip-flop input equations constitute a convenient algebraic form for specifying the logic diagram of a sequential circuit. They imply the type of flip-flop from the letter symbol, and they fully specify the combinational circuit that drives the flip-flops. Note that the expression for the input equation for a D flip-flop is identical to the expression for the corresponding state equation. This is because of the characteristic equation that equates the next state to the value of the D input: Q(t + 1) = DQ. Analysis Procedure 1. Determine the flip-flop input equations in terms of the present state and input variables. 294  NGEC-Logic Circuit & Switching Theory 2. List the binary values of each input equation. 3. Use the corresponding flip-flop characteristic table to determine the next-state values in the state table 4. Determine the state diagram based from the state table. Analysis with D Flip-flops Example: Draw the logic diagram based from the given flip-flop input equations, then determine the state table and state diagram. DA = A ⊕ (x ⊕ y) Where: DA → symbol implies a D flip-flop with output A x and y → are the input variables to the circuit. Solution: Step 1: Determine the state equation No output equations are given, which implies that the output comes from the output of the flip-flop. The state equation is obtained below: A(t+1) = DA = A ⊕ (x ⊕ y) Step 2: Draw the logic diagram based from the given flip-flop input equation and the obtained state equation. Figure 5.17(a): Circuit Diagram with D Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti Step 2: List the binary values of each input equation. Table 5.4: State Table with Input Binary Values 295  NGEC-Logic Circuit & Switching Theory Present Input Next State State x y A(t) A(t+1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Step 3: Use the corresponding flip-flop characteristic table to determine the next-state values in the state table. The equation of A(t+1) specifies an odd function and is equal to 1 when only one variable is 1 or when all three variables are 1. This is indicated in the column for the next state of A(t+1). Recall: XOR truth table Table 5.5: State Table of Circuit in Fig 5.17(a) Present Input Next State State x y A(t) A(t+1) 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Step 4: Determine the state diagram based from the state table. The state diagram consists of two circles, one for each state as shown in Figure 5.17(c). The present state and the output can be either 0 or 1, as indicated by the number inside the circles. A slash on the directed lines is not needed, because there is no output from a combinational circuit. The two inputs can have four possible combinations for each state. Two input combinations during each state transition are separated by a comma to simplify the notation. Figure 5.17(b): State Diagram of Circuit in Fig 5.17(a) Source: “Digital Design” 5th ed by Mano & Ciletti Analysis with JK Flip-flops 296  NGEC-Logic Circuit & Switching Theory Example: Determine the state equation, state table and state diagram of the given logic diagram in Fig.5.18(a). Figure 5.18(a): Sequential Circuit with JK Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti Solution: Step 1: Determine the flip-flop input equations in terms of the present state and input variables. Consider the sequential circuit with two JK flip-flops A and B and one input x, as shown in Fig. 5.18(a). The circuit has no outputs; therefore, the state table does not need an output column. (The outputs of the flip-flops may be considered as the outputs in this case.) The circuit can be specified by the flip- flop input equation JA = B KB = Bx’ JB = x’ KB = A’x + Ax’ = A ⊕ x The characteristic equations for the flip-flops are obtained by substituting A or B for the name of the flip-flop, instead of Q: A(t + 1) = JA’ + K’A B(t + 1) = JB’ + K’B Substituting the values of JA and KA from the input equations, we obtain the state equation for A: A(t + 1) = BA’ + (Bx’)’ A = A’B + AB’ + Ax The state equation provides the bit values for the column headed “Next State” for A in the state table. Similarly, the state equation for flip-flop B can be derived from the characteristic equation by substituting the values of JB and KB: B(t + 1) = x’B’ + (A ⊕ x)’B = B’x’ + ABx + A’Bx’ The state equation provides the bit values for the column headed “Next State” for B in the state table. Step 2: List the binary values of each input equation. Table 5.6: State Table with Input Binary Values 297  NGEC-Logic Circuit & Switching Theory Present State Input Next State A(t) B(t) x A(t+1) B(t+1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Step 3: Use the corresponding flip-flop characteristic table to determine the next-state values in the state table. The next state of each flip-flop is evaluated from the corresponding J and K inputs and the characteristic table of the JK flip-flop listed in Table 5.1. There are four cases to consider. When J = 1 and K = 0, the next state is 1. When J = 0 and K = 1, the next state is 0. When J = K = 0, there is no change of state and the next-state value is the same as that of the present state. When J = K = 1, the next-state bit is the complement of the present-state bit. Examples of the last two cases occur in the table when the present state AB is 10 and input x is 0. JA and KA are both equal to 0 and the present state of A is 1. Therefore, the next state of A remains the same and is equal to 1. In the same row of the table, JB and KB are both equal to 1. Since the present state of B is 0, the next state of B is complemented and changes to 1. The next-state values can also be obtained by evaluating the state equations from the characteristic equation. Table 5.7: State table of Sequential Circuit in Fig 5.18(a) Present State Input Next State A(t) B(t) x A(t+1) B(t+1) 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 Step 4: Determine the state diagram based from the state table. Note that since the circuit has no outputs, the directed lines out of the circles are marked with one binary number only, to designate the value of input x. 298  NGEC-Logic Circuit & Switching Theory Figure 5.18 (b): State Diagram of Sequential Circuit in Fig 5.18(a) Source: “Digital Design” 5th ed by Mano & Ciletti Analysis with T Flip-flops Example: Determine the state equation, state table and state diagram of the given logic diagram in Fig 5.20(a). Figure 5.20(a): Circuit Diagram with T Flip-flop Source: “Digital Design” 5th ed by Mano & Ciletti Solution: Step 1: Determine the flip-flop input equations in terms of the present state and input variables It has two T flip-flops A and B, one input x, and one output y and can be described algebraically by two input equations and an output equation: TA = Bx TB = x y = AB The state equations can be derived by substituting TA and TB in the characteristic equations, yielding 299  NGEC-Logic Circuit & Switching Theory A(t + 1) = TA ⊕ QA where: QA = A(t) = A =TA’ A + TA A’ QB = B(t) = B =(Bx)’A + (Bx)A’ = (B’ + x’)A + A’Bx A(t+1) = AB’ + Ax’ + A’Bx B(t + 1) = TB ⊕ QB B(t + 1) = x ⊕ B y(t+1) = A(t+1) B(t+1) y(t+1) = (AB’ + Ax’ + A’Bx ) (x ⊕ B) Step 2: List the binary values of each input equation. Table 5.8: State Table with Input Binary Values Present State Input Next State Output A(t) B(t) x A(t+1) B(t+1) y(t+1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Step 3: Use the corresponding flip-flop characteristic table to determine the next-state values in the state table. The next-state values in the state table can be obtained by using either the characteristic table listed in Table 5.1 or the characteristic equation Q(t + 1) = T⊕ Q = T’Q + TQ’ The values for y are obtained from the output equation. The next-state values for A and B in the state table are obtained from the expressions of the two state equations. Table 5.9: State Table of Circuit in Fig 5.20(a) Present State Input Next State Output A(t) B(t) x A(t+1) B(t+1) y(t+1) 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 Step 4: Determine the state diagram based from the state table. 300  NGEC-Logic Circuit & Switching Theory The state diagram of the circuit with T Flip-flop is shown in Fig.5.20(b). As long as input x is equal to 1, the circuit behaves as a binary counter with a sequence of states 00, 01, 10, 11, and back to 00. When x = 0, the circuit remains in the same state. Output y is equal to 1 when the present state is 11. Here, the output depends on the present state only and is independent of the input. The two values inside each circle and separated by a slash are for the present state and output. Figure 5.20(b) : State Diagram of Circuit in Fig 5.20(a) Source: “Digital Design” 5th ed by Mano & Ciletti Course Packet Discussion Forum (Virtual Recitation) Instruction: Comment your answer in Google class stream where this question is posted. You are given 24 hours to express your idea. 24 hours start after the question is posted on the Google classroom stream page. You may cite additional references to clarify your idea. “ What is the difference between combinational and sequential circuit in analyzing logic diagram in terms of its characterisctics? “ 301  NGEC-Logic Circuit & Switching Theory Activity Sheet 16 PROBLEM SOLVING EXERCISES Instruction: Show the complete solution and box your final answer. This is a collaborative learning exercises, therefore, submit only one(1) answer per group. Write in your answer sheet all the names of the group members who participated in this activity, scanned copy or take a picture of your answer and submit it to our google classroom classwork where this activity is posted. Submit this on or before the agreed deadline of submission. (25 points each, a total of 100 points) A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: JA = x KA = B JB = x KB = A’ (a) Derive the state equations A (t + 1) and B (t + 1) by substituting the input equations for the J and K variables. (b) Draw the logic diagram (c ) Tabulate the state table (d) Draw the state diagram. 302  NGEC-Logic Circuit & Switching Theory Learner’s Feedback Form Name of Student: ___________________________________________________ Program : ___________________________________________________ Year Level : ___________ Section : ___________ Faculty : ___________________________________________________ Schedule : ___________________________________________________ Learning Packet : Number : _________ Title : ______________________ How do you feel about the topic or concept presented? □ I completely get it. □ I’m struggling. □ I’ve almost got it. □ I’m lost. In what particular portion of this learning packet, you feel that you are struggling or lost? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ Did you raise your concern to you instructor? □ Yes □ No If Yes, what did he/she do to help you? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ If No, state your reason? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ To further improve this learning packet, what part do you think should be enhanced? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ How do you want it to be enhanced? ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ ________________________________________________________________ 303  NGEC-Logic Circuit & Switching Theory Post-Assessment Instruction: Select the best answer. Write the complete answer (do not include the letter) in a separate sheet of paper. Scanned copy or take a picture of your answer sheet and submit it to our google classroom where the pre-assessment is posted. Don’t forget to write your name at the upper left most part of your answer sheet. Use A4 or short bond paper. 1. Memory elements in clocked sequential circuits are called a. latches b. flip-flop c. signals d. gates 2. The state of flip-flop can be switched by changing its a. input signal b. output signal c. momentary signals d. all signals 3. The major difference between various types of flip-flops are a. output that they generate b. input that they posses c. gates d. both a and b 4. The flip-flops can be constructed with two a. NAND gates b. XOR gates c. AND gates d. NOT gates 5. The momentary change in the state of flip-flop is called a. feedback path b. tri state c. signals d. trigger 6. Clocked flip-flops are triggered by a. feedback path b. pulses c. signals d. clear 7. Sequential circuits are 304  NGEC-Logic Circuit & Switching Theory a. Synchronous b. Asynchronous c. signals d. both a and b 8. The behavior of sequential circuits are determined by the state of their a. clock b. pulses c. flip-flops d. trigger 9. JK Master-slave flip-flops are constructed with a. NAND gates b. OR gates c. AND gates d. NOT gates 10. A synchronous sequential circuit is made up of a. combinational gates b. flip-flops c. latches d. both a and b 305  NGEC-Logic Circuit & Switching Theory Quiz 06 Quiz #05 : Final Period (Topics Covered :LM05) Remember: You are given 12 hours to answer the quiz after this is uploaded to google classroom classwork. This is an individual assessment, therefore, individual submission of answer to google classroom classwork where this is posted. Instructions: Show the complete solutions and box your final answer. Write your answer in an A4 or short bond paper. Write your complete name (First Name, MI, Family Name) in the upper left most of your paper. Scanned copy or take a picture of your answer and submit it on or before the deadline of submission to our google classroom classwork where this quiz is posted. 306  NGEC-Logic Circuit & Switching Theory Assignment 06 Take Home Assignment 06 : Final Period (Topics Covererd: LM05 ) Instructions: Show the complete solutions and box your final answer. Write your answer in an A4 or short bond paper. This is a group assessment. Submit only one (1) assignment per group and write all the names of the group members who participated in this activity. Scanned copy or take a picture of your answer and submit it to our google classroom classwork where this assignment is posted. (50 points each problem, a total of 100 points) 1. Obtain the flip-flop input equation and state equation. Derive the state table and the state diagram of the sequential circuit shown in figure below. Explain the function that the circuit performs. 2. A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip-flop input equations and circuit output equation are: JA = Bx + B’y’ KA = B’xy’ JB = A’x KB = A + xy’ z = Ax’y’ + Bx’y’ (a) Draw the logic diagram of the circuit. (b) Tabulate the state table. (c) Derive the state equations for A and B. 307  NGEC-Logic Circuit & Switching Theory References Mano, M. M., & Ciletti, M. D. (2015). Digital Design. 5th Edition. Singapore: Pearson Education South Asia Pte Ltd. Mano, M. M. (2001). Digital Design. 3rd Edition. ISBN 10: 0130621218 / ISBN 13: 9780130621214. Prentice Hall Publication. Tutorialspoint(2017).Digital Circuits-Flip-flops. Retrieved from https://www.tutorialspoint.com/digital_circuits/ digital_circuits_flip_flops.htm Electronicshub(2020).Introduction to Flip-flop. Retrieved from https://www.electronicshub.org/flip-flops/ Electronics tutorial(2020). Sequential Logic Circuit. Retrieved from https://www.electronics-tutorials.ws/sequential/seq_1.html Thambawita,V(2017). Analysis of Clocked Sequential Circuit. Retrieved from https://www.slideshare.net/vlbthambawita/lec-07-analysis-of-clocked- sequential-circuits 308  NGEC-Logic Circuit & Switching Theory Learner’s Performance Report Name of Student: ___________________________________________________ Program : ___________________________________________________ Year Level : ___________ Section : ___________ Faculty: ___________________________________________________ Schedule : ___________________________________________________ Course Code : ____________ Title: ____________________________ Learning Module Code Learning Module Title Rating Learning Packet Code Learning Packet Title Rating 309  NGEC-Logic Circuit & Switching Theory List of Contributors 1. Faye L. Baret 2. Aida T. Solomon 310