Computer Organization and Architecture PDF

Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 6 Internal Memory Copyright © 2022 Pearson Education, Ltd. All Rights Res...

Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 6 Internal Memory Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.1 Memory Cell Operation Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 6.1 Semiconductor Memory Types Memory Type Category Erasure Write Volatility Mechanism Random-access memory (RAM) Read-write Electrically, Electrically Volatile memory byte-level Read-only memory (ROM) Read-only Masks memory Not possible Programmable ROM (PROM) Erasable PROM (EPROM) UV light, chip-level Nonvolatile Electrically Erasable PROM Read-mostly Electrically, Electrically (EEPROM) memory byte-level Flash memory Electrically, block-level Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Dynamic RAM (DRAM) RAM technology is divided into two technologies: – Dynamic RAM (DRAM) – Static RAM (SRAM) DRAM – Made with cells that store data as charge on capacitors – Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0 – Requires periodic charge refreshing to maintain data storage – The term dynamic refers to tendency of the stored charge to leak away, even with power continuously applied Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.2 Typical Memory Cell Structures Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Static RAM (SRAM) Digital device that uses the same logic elements used in the processor Binary values are stored using traditional flip-flop logic gate configurations Will hold its data as long as power is supplied to it Copyright © 2022 Pearson Education, Ltd. All Rights Reserved SRAM versus DRAM SRAM Both volatile – Power must be continuously supplied to the memory to preserve the bit values Dynamic cell – Simpler to build, smaller – More dense (smaller cells = more cells per unit area) DRAM – Less expensive – Requires the supporting refresh circuitry – Tend to be favored for large memory requirements – Used for main memory Static – Faster – Used for cache memory (both on and off chip) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Read Only Memory (ROM) Contains a permanent pattern of data that cannot be changed or added to No power source is required to maintain the bit values in memory Data or program is permanently in main memory and never needs to be loaded from a secondary storage device Data is actually wired into the chip as part of the fabrication process – Disadvantages of this: ▪ No room for error, if one bit is wrong the whole batch of ROMs must be thrown out ▪ Data insertion step includes a relatively large fixed cost Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Programmable ROM (PROM) Less expensive alternative Nonvolatile and may be written into only once Writing process is performed electrically and may be performed by supplier or customer at a time later than the original chip fabrication Special equipment is required for the writing process Provides flexibility and convenience Attractive for high volume production runs Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Read-Mostly Memory Flash EPROM EEPROM Memory Electrically erasable Intermediate between Erasable programmable read- EPROM and EEPROM in programmable read- only memory both cost and only memory functionality Can be written into at any time without erasing prior contents Uses an electrical Erasure process can be erasing technology, performed repeatedly Combines the does not provide byte- advantage of non- level erasure volatility with the flexibility of being updatable in place More expensive than Microchip is organized PROM but it has the so that a section of advantage of the More expensive than memory cells are multiple update EPROM erased in a single capability action or “flash” Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.3 Typical 16-Mbit DRAM (4M  4) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.4 Typical Memory Package Pins and Signals Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.5 256-KByte Memory Organization Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.6 1-MB Memory Organization Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Composed of a collection of Interleaved Memory DRAM chips Grouped together to form a memory bank Each bank is independently able to service a memory read or write request K banks can service K requests simultaneously, increasing memory read or write rates by a factor of K If consecutive words of memory are stored in different banks, the transfer of a block of memory is speeded up Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Error Correction Hard Failure – Permanent physical defect – Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 – Can be caused by: ▪ Harsh environmental abuse ▪ Manufacturing defects ▪ Wear Soft Error – Random, non-destructive event that alters the contents of one or more memory cells – No permanent damage to memory – Can be caused by: ▪ Power supply problems ▪ Alpha particles Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.7 Error-Correcting Code Function Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.8 Hamming Error-Correcting Code Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 6.2 Increase in Word Length with Error Correction Single-Error Correction/ Single-Error Correction Double-Error Detection Data Bits Check Bits % Increase Check Bits % Increase 8 4 50.0 5 62.5 16 5 31.25 6 37.5 32 6 18.75 7 21.875 64 7 10.94 8 12.5 128 8 6.25 9 7.03 256 9 3.52 10 3.91 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.9 Layout of Data Bits and Check Bits Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.10 Check Bit Calculation Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.11 Hamming SEC-DEC Code Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Advanced DRAM Organization SDRAM One of the most critical system bottlenecks when using high-performance processors is the interface to main internal memory DDR-DRAM The traditional DRAM chip is constrained both by its internal architecture and by its interface to the processor’s memory bus RDRAM A number of enhancements to the basic DRAM architecture have been explored – The schemes that currently dominate the market are SDRAM and DDR-DRAM Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Synchronous DRAM (SDRAM) One of the most widely used forms of DRAM Exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states With synchronous access the DRAM moves data in and out under control of the system clock The processor or other master issues the instruction and address information which is latched by the DRAM The DRAM then responds after a set number of clock cycles Meanwhile the master can safely do other tasks while the SDRAM is processing Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.12 256-Mb Synchronous Dynamic RAM (SDRAM) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 6.3 SDRAM Pin Assignments A0 to A13 Address inputs BA0, BA1 Bank address lines CLK Clock input CKE Clock enable CS Chip select RAS Row address strobe CAS Column address strobe WE Write enable DQ0 to DQ7 Data input/output DQM Data mask Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.13 SDRAM Read Timing (burst length = 4, latency = 2) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Double Data Rate SDRAM (DDR SDRAM) Developed by the JEDEC Solid State Technology Association (Electronic Industries Alliance’s semiconductor-engineering-standardization body) Numerous companies make DDR chips, which are widely used in desktop computers and servers DDR achieves higher data rates in three ways: – First, the data transfer is synchronized to both the rising and falling edge of the clock, rather than just the rising edge – Second, DDR uses higher clock rate on the bus to increase the transfer rate – Third, a buffering scheme is used Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Table 6.4 DDR Characteristics DDR1 DDR2 DDR3 DDR4 Prefetch buffer (bits) 2 4 8 8 Voltage level (V) 2.5 1.8 1.5 1.2 Front side bus data rates (Mbps) 200—400 400—1066 800—2133 2133—4266 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.14 DDR Generations Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Embedded DRAM (eDRAM) eDRAM is a DRAM integrated on the same chip or MCM of an application-specific integrated circuit (ASIC) or microprocessor For a number of metrics, eDRAM is intermediate between on-chip SRAM and off-chip DRAM – For the same surface area, eDRAM provides a larger size memory than SRAM but smaller than off-chip DRAM – eDRAM’s cost-per-bit is higher when compared to equivalent stand-alone DRAM chips used as external memory, but it has a lower cost-per-bit than SRAM – Access time to eDRAM is greater than SRAM but, because of its proximity and the ability to use wider busses, eDRAM provides faster access than DRAM Fundamentally eDRAMs use the same designs and architectures as DRAM Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.15 IBM z13 Storage Control (SC) Chip Layout Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.16 Use of eDRAM in Intel Core Systems Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Flash Memory Used both for internal memory and external memory applications First introduced in the mid-1980’s Is intermediate between EPROM and EEPROM in both cost and functionality Uses an electrical erasing technology like EEPROM It is possible to erase just blocks of memory rather than an entire chip Gets its name because the microchip is organized so that a section of memory cells are erased in a single action Does not provide byte-level erasure Uses only one transistor per bit so it achieves the high density of EPROM Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.17 Flash Memory Operation Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.18 Flash Memory Structures Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.19 Kiviat Graphs for Flash Memory Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.20 Nonvolatile RAM within the Memory Hierarchy Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 6.21 Nonvolatile RAM Technologies Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Internal Summary Memory Chapter 6 Semiconductor main memory DDR DRAM – Organization – Synchronous DRAM – DRAM and SRAM – DDR SDRAM – Types of ROM – Chip logic Flash memory – Chip packaging – Operation – Module organization – NOR and NAND flash – Interleaved memory memory Error correction Newer nonvolatile solid-state eDRAM memory technologies – IBM z13 eDRAM cache – STT-RAM structure – PCRAM – Intel core system cache structure – ReRAM Copyright © 2022 Pearson Education, Ltd. All Rights Reserved