cap6-lecture-notes-117-132-12-16.pdf

Document Details

Uploaded by SelfDeterminationOmaha

ITA

Full Transcript

6 Branch Prediction & Speculative Superscalar Processors Figure 6.7: Extended Tomasulo’s algorithm details. Multiple Issue Superscalar Processors Concept Techniques such as out-of-order and speculative executions aid the CPI to get closer to 1, but not below that number. Therefore, to get CPI less than 1, it is needed to issue multiple instructions simultaneously, i.e., multiple issue. It is possible to issue various instructions in a same clock cycle, as long as the following problems are fixed. It is allowed to issue instruction in parallel but identifying dependencies among instructions in the sequence (decode cycle). In this sense, it is needed to duplicate or even multiplicate the instruction fetch and decode hardware units. Related to the common data bus - CDB usage, it is needed to duplicate or 122 Multiple Issue Superscalar Processors even multiplicate the CDB bandwidth. The parallel instructions issue is done in the same way as previously seen. However, a conditional branch is not issued with another instruction in the same clock cycle. Also, it is checked whether the register written by instruction i+1 is read by instruction i+2. If that was the case, the reservation station or the ROB gets aware of this dependency on the first instruction, i.e., instruction i+1. Example Let’s consider the following code (Listing 6.11) which increments each element of an integer array. Listing 6.11: Code example related to multiple issue processors. 1 Loop : ld x2 ,0( x1 ) // x2 =0; i - -) 2 x [ i ] = x [ i ] + s ; // body of each iteration is independent The RISC-V assembly code, translated from the previous C code is represented in Listing 6.13. Listing 6.13: RISC-V assembly code example. 1 Loop : fld f0 ,0( x1 ) // f0