ARM-CHAPTER_3.pdf
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Chapter 3 ARM Instructions Part I 3.1 Introduction Advanced RISC Machine (ARM) was developed by the Acorn Company. ARM is a leader supplier of microprocessors in the world, ARM develop the core CPU and thousand of suppliers add more functional units to the core. ARM uses two types in- struction ca...
Chapter 3 ARM Instructions Part I 3.1 Introduction Advanced RISC Machine (ARM) was developed by the Acorn Company. ARM is a leader supplier of microprocessors in the world, ARM develop the core CPU and thousand of suppliers add more functional units to the core. ARM uses two types in- struction called Thumb and Thumb-2. Thumb instructions are 16 bits and thumb-2 instructions are 32 bits, currently most ARM processors uses 32 bit instructions. ARM contains 15 registers called R0 through R15, R0 and R12 called general propose registers. ARM able to execute Thumb instructions (16 bit instructions) and Thumb-2 32 bits instruction, Thumb instructions use on R0 through R7 registers. ARM is intended for applications that require power efficient processors, such as Telecommunications, Data Communication (protocol converter), Portable Instru- ment, Portable Computer and Smart Card. ARM is basically a 32-bit RISC proces- sor (32-bit data bus and address bus) with fast interrupt response for use in real time applications. A block diagram of ARM7 processor is shown in Fig. 3.1. Instruction Decoder and Logic Control: The function of instruction decoder and logic control is to decode instructions and generate control signals to other parts of processor for execution of instructions. Address Register: To hold a 32-bit address for address bus. Address Increment: It is used to increment an address by four and place it in address register. Register Bank: Register bank contains thirty-one 32-bit registers and six status registers. Barrel Shifter: It is used for fast shift operation. ALU; 32-bit ALU is used for Arithmetic and Logic Operation. © Springer International Publishing Switzerland 2015 35 A. Elahi, T. Arjeski, ARM Assembly Language with Hardware Experiments, DOI 10.1007/978-3-319-11704-1_3 36 3 ARM Instructions Part I Fig. 3.1 Block diagram of ARM7 architecture Write Data Register: The processor put the data in Write Data Register for write operation. Read Data Register: When processor reads from memory it places the result in this register. ARM Operation Mode: ARM can operates in one of the following mode: 1. User Mode: Use for normal operation. 2. IRQ Mode: This Interrupt mode is designed for handling interrupt operations. 3. Supervisory Mode: Used by operating system. 4. FIQ Mode: Fast Interrupt mode. 3.1 Introduction 37 Fig. 3.2 User mode registers 31 0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) CPSR 31 30 29 28 27 7 6 5 4 3 2 1 0 N Z C V Unused I F T M4 M3 M2 M1 M0 Fig. 3.3 Storage format for CPSR 5. Undefined Mode: When an undefined instruction executed. 6. Abort Mode: This mode indicates that current memory access cannot be com- pleted, such as when data is not in memory and processor require more time to access disk and transfer block of data to memory. ARM Registers: ARM7 has 31 general registers and 6 status registers. At user mode only 16 registers and one Program Status Register (PSR) are available to programmers. The registers are labeled R0 through R15. R15 is used for Program Counter (PC), R14 is used for Link Register and R13 is used for Stack Pointer (SP). Figure 3.2 shows user mode registers. Current Program Status Register (CPSR): Figure 3.3 shows the format of PSR. This register is used to store control bits and flag bits. The flag bits are N, Z, C and V, and the control bits are I, F, and M0 through M4. The flag bits may be changed during a logical, arithmetic and compare operation. Flag Bits N (negative): N = 1 means result of an operation is negative and N = 0 means result of an operation is positive. Z (zero): Z = 1 means result of an operation is zero and Z = 0 result of an operation is not zero. C (carry): C = 1 means result of an operation generated a carry, and C = 0 means result of an operation did not produce a carry. 38 3 ARM Instructions Part I V (overflow): V = 1 means result of an operation generated an overflow and V = 0 means result of an operation did not generate an overflow. Control Bits I (interrupt bit): When this bit set to one, it will disable the interrupt and this means the processor does not accept any software interrupt. F bit is used to disable and enable fast interrupt request mode (FIQ) mode. M4, M3, M2, M1 and M0 are mode bits and they are equal to 10000 for user mode. T (State bit): T = 1 Processor executing thumb instructions, T = 0 processor execut- ing ARM instructions 3.2 Instruction Set Architecture (ISA) Manufacturers of CPUs publish a document that contains information about the processor such as list of registers, function of each register, size of data bus, size of address bus and list of instructions that can be executed by the CPU. Each CPU has a known instruction set that a programmer can use to write assembly language programs. Instruction sets are specific to each type of processor. That being said, Pentium processors use a different instruction set than ARM processors. The In- structions are represented in mnemonic form means abbreviation, for example, the Addition instruction represented by “ADD” Subtraction instruction represent by “SUB” for example, the addition instruction is represented by ADD R1, R2, R3; means add contents of R2 with R3 and store results in R1. R1, R2, and R3 are called operands A. Classification of Instruction base on number of operands No Operand Instructions: The following are some of the instructions that do not require any operands: HLT—Halt the CPU NOP—No operation PUSH operand: Push operand into top of the stack POP operand: Remove the operand from top of the stack One Operand Instructions: The following are some of the instructions that require one operand. 3.3 ARM Instructions 39 Two Operand Instructions: The following are some of the instructions that require two operands: Three Operand Instructions: Most modern processors use instructions with three operands, such ARM, MIPS and Itanium. 3.3 ARM Instructions ARM Architecture support Thumb 16 bit and Thumb-2 32 bit instruction set. Most of the ARM instructions use three operands. These instructions are classified based on their instructions format and are listed as followings: A. Data Processing Instructions B. Single Data Swap C. Shift and Rotate Instructions D. Unconditional Instructions and Conditional Instructions: E. Stack Operations F. Branch G. Multiply Instructions E: Data Transfer 3.3.1 Data Processing Instructions The data processing instructions are as follows: AND, EOR, SUB, RSB, ADD, ADC, SBC, RSB TST, TEQ, CMP, CMN, ORR, MOV, BIC and MNW. Data pro- cessing instructions use register operands and immediate operand. The general for- mat of Data processing instructions is Mnemonic {S}{Condition} Rd, Rn, operand2 Mnemonic: Mnemonic is abbre- viation of an operation such as ADD for addition {}: Commands inside the { } is optional such as S and condition S: When an instruction contains S mean update the Processor Status Register (PSR) flag bits 40 3 ARM Instructions Part I Condition: Condition define the instruction will executed if meet the condition Rd: Rd is destination register Rn: Rn is operand1 Operand2: Operand2 can be register or immediate value A. Registers Operands: The operands are in registers. First register is destination register, second register is operand1 and third register is operand2. Following are Arithmetic and Logic operations Instructions with register oper- ands Example 3.1: Assume contents of R1 is 1111111111011111 and R2 is 1000 0100 1110 0011 after execution of BIC R0,R1, R2 the R0 contains 0111 101100011100 B. Immediate Operand: In immediate operand, operand2 is an immediate value and maximum can be 12 bits 3.3 ARM Instructions 41 Example 3.2: What is contents of R1 after executing following instruction, assume R2 contains 0x12345678 The ADD instruction will add contains of R2 with 0x2345 and store the result in R1, then R1 = 0x123459BD Setting Flag Bits of PSR: The above instructions do not affect the flag bit of PSR because the instructions do not have option S. By adding suffix S to the instruction, the instruction would affect the flag bit. Compare and Test Instructions: ARM processor uses the compare and test instructions to set flag bits of PSR and following are Compare and Test instructions CMP, CMN, TST, and TEQ: These instruction uses two operands for compare and test, the result of their operations do not write to any register CMP Instruction (Compare Instruction): The CMP instruction has following format CMP Operand 1, Operand2: The CMP instruction compares Operand1 with Operand2, this instruction subtract Operand2 from Operand 1 and sets the appropri- ate flag. The flag bit set based on the result of the operation as follow Z flag set if Operand2 equal operand 1 N flag is set if operand1 less than operand2 C flag is set if result of operation generate carry Example 3.4: Assume R1 contains 0x00000024 and R2 contains 0x00000078, the operation CMP R1, R2 will set N flag to 1 CMP Rd, immediate value, the immediate value can be 8 bits such as CMP R1, #0xFF CMN Compare Negate: The CMN has following format CMN Operand1, Operand2: The instruction will add operand1 with operand 2 and set appropriate flag bit 42 3 ARM Instructions Part I Example 3.5: Assume R1 contains 0x00000024 and R2 contains 0x13458978, the operation CMN R1, R2 with result carry and set C flag to 1. TST (Test Instruction): The test instruction has following format TST Oprand1, Operand2: The Test Instruction performs AND operation between operand1 and Operand2 and set appropriate flag bit. The operand to can be immedi- ate value or Register such as If R1 equal to R2 then Z flag set to one 3.4 Register Swap Instructions (MOV and MVN) The register swap instructions has following general formats Example 3.6: What is contents of R1 after Execution of following instruction Assume R2 contains 0X0000FFFF ← ← 3.5 Shift and Rotate Instructions 43 MOV{S}{condition} Rd, immediate value Immediate value is 16 bits, The range of immediate value if from 0x00000000 to 0x0000FFFF Example 3.7: MOV R2, # 0x45, the contents of R2 will be 0x00000045 Conditional MOV 3.5 Shift and Rotate Instructions ARM combined the Rotate and Shift operation with other Instructions, the ARM processor performs following shift operations Logical Shift Left (LSL): In logical shift left operations each bit of register shifted to the left as shown in Fig. 3.4 and a zero will placed in the least significant bit, the logical shift left multiply the contents of register by 2. 44 3 ARM Instructions Part I Fig. 3.4 Logical shift left 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 Carry Flag F ig. 3.5 Logical Shift Left 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 Carry Flag Example 3.8: What is contents of R1 after executing following Instruction, assume R1 contains 0x00000500. LSL R1, R1, 8 R1= 0x00050000 Logical Shift Right (LSR): In logical shift right operations each bit of register shifted to the right as shown in Fig. 3.5 and a zero will placed in the most significant bit, the logical right divides the contents of register by 2. Example 3.9 What is contents of R1 after executing following Instruction, assume R1 contains 0x00000500. Arithmetic Shift Right (ASR): In Arithmetic shift right the most significant bit does not change and each bit shifted to the right as shown in Fig. 3.6. Rotate Right: Figure 3.7 shows an eigth bit rgister and Fig. 3.7 shows the regiter after rotating one times 3.5 Shift and Rotate Instructions 45 Fig. 3.6 Arithmetic shift 1 0 1 0 1 1 0 0 right 1 1 0 1 0 1 1 0 0 Carry Flag Fig. 3.7 Rotate right operation B7 B6 B5 B4 B3 B2 B1 B0 B0 B7 B6 B5 B4 B3 B2 B1 Example 3.10 What is content of R1 after rotating 16 times, assum R1 contains 0x0000FFFF ARM combines data processing instructions and shift operation, shift operation is applied to the second operand of the instruction. Example 3.11: Register R2 containes 0xEEEEFFFF, by executing by rotating 16 times the contains of R1 will be 0xFFFFEEE Also a register can hold number of times the operand2 must be shifted. 46 3 ARM Instructions Part I 3.6 ARM Unconditional Instructions and Conditional Instructions Figure 3.8 shows the general format of an ARM instruction. ARM instruction de- fines two types of instructions, namely: 1. Unconditional Instruction 2. Conditional Instruction Condition code defines the type of conditions. If this field is set to 1110 then the instruction is an unconditional instruction, otherwise the instruction is a conditional instruction. To use an instruction as a conditional instruction, the condition will suf- fix to the instruction. The suffixes are: Condition Code Condition 0000 EQ Equal 0001 NE Not equal 0010 CS Carry set 0111 CC Carry is clear 0100 MI Negative (N flag is set) 0101 PL Positive (N flag is zero) 0110 VS Overflow set 0111 VC Overflow is clear 1000 HI Higher for unsigned number 1001 LS Less than for unsigned number 1010 GT Greater for signed number 1011 LT Signed less than 1100 GT Greater Than 1101 LE Less than or equal 1110 AL Unconditional instructions 1111 Unused code Condition Instruction Code 31 28 27 1 Fig. 3.8 General format of an ARM instruction 3.7 ARM Data Processing Instruction Format 47 Processor checks condition flag before executing the conditional instruction. If it matches with the condition instruction then processor executes the instruction, oth- erwise skips the instruction. Example 3.10:Convert the following HLL to ARM assembly language. ARM assembly language for the above program would be: Example 3.11:Convert the following HLL to ARM assembly language. ARM assembly language for the above program would be: 3.7 ARM Data Processing Instruction Format Figure 3.9 shows data processing instruction format. Condition Code: To determine if the instruction is a conditional or a unconditional instruction 31 28 27 26 25 24 21 20 19 16 15 12 11 0 Cond 00 I Op code S Rn RD Operand 2 Fig. 3.9 Data processing instruction format 48 3 ARM Instructions Part I F ig. 3.10 Operand2’s format 11 7 6 5 4 3 0 when bit 4 is equal to 0 # shift SH 0 Rm I bit I = 0 means the operand2 is a register, I = 1 means the operand 2 is an immedi- ate value. Op Code: To determine types of operation and they are as followings: S bit: S = 0 do not change flag bits of PSR register, S = 1 set condition flags of PSR register Rn: Rn is first operand and it can be any of 16 registers, R0 through R15 Rd: Rd is destination register and it can be any of 16 registers, R0 through R15 Operand2: When I = 0 the operand2 is a register and Fig. 3.10 shows operand2’s format. # Shift: To determine immediate value for number of times Rm must be shifted SH: To determine types of shift operation Rm: Second operand Operation SH value LSL 00 Logical Shift Left LSR 01 Logical Shift Right ASR 10 Arithmetic Shift Right ROR 11 Rotate Right When bit 4 of operand2 is set to 1, the number of times Rm must be shifted is in a register. 3.8 Stack Operation and Instructions 49 Figure 3.11 shows format of operand2 of Fig. 3.9. I = 1 The operand 2 would have following format. 11 0 Immediate value Example 3.12:Convert the following instruction to machine code. Fig. 3.11 Format of Oper- and2 when bit 4 is equal to 1 3.8 Stack Operation and Instructions Part of memory is used for temporary storage is called stack, the stack pointer holds the address of top of the stack as shown in Fig. 3.12 The register R13 assigned as Stack Pointer (SP), the stack uses following in- structions a. Push {condition} Rn: transfer the contains of Rn into stack and add 4 to the stack pointer Example 3.12 Assume contains of R3 is 0x01234567, Fig. 3.13 show the contents of Stack after executing push R3. Example 3.14 Shows contents of stack and SP in Fig. 3.13 after execution of Push R4, assume R4 contains 0x5645321F. POP Instruction: The POP instruction has following format. POP{condition} Rn POP Rn: The pop instruction remove the word from top the stack and store it into register rn and automatically decrement stach pointer by 4. Example 3.15: Show the contents of stack and SP of Fig. 3.14 after execution POP R0, the contents of will be R0 = 0x1FAD7856 and stack will look like as Fig. 3.15.
