AO6I_EDE_manual.pdf

Emerging Trends in Electronics (22636) w.e.f 2022-23 Learning Manual for Emerging Trends in Electronics (22636)...

Emerging Trends in Electronics (22636) w.e.f 2022-23 Learning Manual for Emerging Trends in Electronics (22636) Semester– VI (DE/EJ/ET/EN/EX/EQ/IE/IS/IC/TE) W.E.F. 2022-2023 Maharashtra State Board of Technical Education, Mumbai (Autonomous) (ISO-9001-2015) (ISO/IEC 27001:2013) Maharashtra State Board of Technical Education Emerging Trends in Electronics (22636) w.e.f 2022-23 Maharashtra State Board of Technical Education, Mumbai (Autonomous) (ISO-9001-2015) (ISO/IEC 27001:2013) 4th Floor, Government Polytechnic Building, 49, Kherwadi, Bandra (East), Mumbai – 400051. (Revised and Printed January 2023) Maharashtra State Board of Technical Education Emerging Trends in Electronics (22636) w.e.f 2022-23 Preface The primary focus of any engineering work in the technical education system is to develop the much needed industry relevant competency and skills. With this in view, MSBTE embarked on innovative “I” scheme curricula for engineering diploma programs with outcome based education through continuous inputs from socio economic sectors. The industry experts during the consultation while preparing the Perspective Plan for diploma level technical education categorically mentioned that the curriculum, which is revised and implemented normally further revised after 4-5 years. The technological advancements being envisaged and faced by the industry in the present era are rapid and curriculum needs to be revised by taking care of such advancements and therefore should have a provision of accommodating continual changes. These views of industry experts were well taken and further discussed in the academic committee of MSBTE, wherein it was decided to have a dynamism in curriculum for imparting the latest technological advancements in the respective field of engineering. In order to provide an opportunity to students to learn the technological advancements, a course with a nomenclature of “Emerging Trends in Electronics Engineering” is introduced in the 6th semester of Electronics Engineering Group. The technological advancements to be depicted in the course called emerging trends was a challenging task and therefore it was decided to prepare a learning material with the involvement of industrial and academic experts for its uniformity in the aspect of delivery, implementation and evaluation. In the electronics sector, new applications are coming up and it is mandatory for all technologists to be well versed in these developments to survive and provide satisfactory and quality services to the society and industry. This course aims to prepare the diploma graduates to be conversant with such emerging trends. The main areas in which such developments encompass are Advanced Processors, Electronic System Manufacturing, Smart systems, Digital Factory and Communication. Each unit in the course given an insight to the learner about the latest development in the relevant fields. This learning manual is designed to help all stakeholders, especially the students and teachers and to develop in the student the pre-determined outcomes. It is expected to explore further by both students and teachers, on the various topics mentioned in learning manual to keep updated themselves about the advancements in related technology. MSBTE wishes to thank the Learning Manual development team, specifically Mr. Sudhir Panditrao, Industry Experts, Mr. K.P. Akole, Coordinator, Smt. Vidya Lunge, Co-coordinator of the programs, other Industry Experts and academic experts for their intensive efforts to formulate the learning material on “Emerging Trends in Electronics Engineering”. Being emerging trend and with the provision of dynamism in the curricula, any suggestions towards enrichment of the topic and thereby course will be highly appreciated. (Dr. Vinod M. Mohitkar) Director MSBTE, Mumbai Maharashtra State Board of Technical Education Emerging Trends in Electronics (22636) w.e.f 2022-23 Content Sr. No Name of Topic Page Advance Processors 1 1.1 Advances in processor architecture 1 1.2 ARM 3 1 1.3 Arduino 9 1.4 Arduino IDE 17 1.5 Arduino Interfacing 22 1.6 Graphical Processing Unit (GPU) 25 Electronic System Manufacturing Processes 35 2.1 Surface Mount Devices 35 2 2.2 Modern Electronics Assembly and Manufacturing process 36 2.3 Environmental Standards for Electronic manufacturing. 46 2.4 Battery 48 Next Generation telecom Network 61 3.1 NGN architecture 62 3.2 NGN Wireless Technology 70 3 3.3NGN Core 77 3.4 Fiber to the Home (FTTH) 79 3.5 Next Generation transmission system 81 Digital Factory 86 4.1 Internet of Things 86 4.2 Architectures 92 4 4.3 Applications of IoT in Industries. 97 4.4 I4.0/IIoT/ Smart Manufacturing 103 4.5 Artificial Intelligence/Machine Learning. 116 Smart World 127 5.1 Evolution of smart home. 128 5.2 Basic requirements and components for Smart Home 131 5 5.3 Basic requirements and components for Smart City 135 5.4 IoT/M2M Network architecture 148 5.5 Domains for operation. 149 Appendix A Abbreviations 153 Appendix B Answer Key 158 Appendix C Bibliography 160 Maharashtra State Board of Technical Education Emerging Trends in Electronics (22636) w.e.f 2022-23 Unit 1: Advance Processors Expected Course Outcome: Suggest the relevant computing systems/processor for specific type of application Teaching Hrs. 10 Marks 16 To attain above course outcome candidate must able to: a. Describe the given advancement in the processor architecture. b. Describe the given feature of the ARM7 processors c. Describe the given features of Arduino board. d. Describe the given functions in Arduino IDE. e. Enlist features of GPU. Unit focus on following major points: 1.1 Advances in processor architecture: Introduction, Processor Selection Criteria 1.2 ARM: Introduction, Features of ARM7 and ARM7TDMI, advantages, applications. 1.3 Arduino: Introduction, Compatible R2/R3 Uno board Features. ATmega 328: Introduction, pin description. 1.4 Arduino IDE: Features, Sketch: C, C++ functions setup (), loop (), pinMode (), digitalWrite (), digital Read () and delay () 1.5 Arduino Interfacing: LED, Relay and DC motor. 1.6 Graphical Processing Unit (GPU): Introduction, Features, Basic architecture of GPU, Architectural difference between GPU and CPU, GPU applications. 1.1 Advances in processor architecture: 1.1.1 Introduction Processors have undergone a tremendous evolution throughout their history. A key milestone in this evolution was the introduction of the microprocessor, term that refers to a processor that is implemented in a single chip. The first microprocessor was introduced by Intel under the name of Intel 4004 in 1971. It contained about 2,300 transistors, was clocked at 740 KHz and delivered 92,000 instructions per second while dissipating around 0.5 watts. Since then, practically every year we have witnessed the launch of a new microprocessor, delivering significant performance improvements over previous ones. Some studies have estimated this growth to be exponential, in the order of about 50% per year, which results in a cumulative growth of over three orders of magnitude in a time span of two decades. These improvements have been fueled by advances in the manufacturing process and innovations in processor architecture. The complexity of an integrated circuit is bounded by physical limitations on the number of transistors that can be put onto one chip, the number of package terminations that can connect the processor to other parts of the system, the number of interconnections it is possible to make on the chip, and the heat that the chip can dissipate. 1.1.2 Processor Selection Criteria With numerous kinds of processors, various design philosophies are available for digital systems. Following considerations need to be factored during processor selection for a Digital Systems. 1. Performance Considerations 2. Power considerations 3. Memory 4. Peripheral Set 5. Operating Voltage 6. Specialized Processing Units Maharashtra State Board of Technical Education 1 Emerging Trends in Electronics (22636) w.e.f 2022-23 7. Price 1. Performance: The first and foremost consideration in selecting the processor is its performance. The performance speed of a processor is dependent primarily on its architecture and its silicon design. Evolution of fabrication techniques helped packing more transistors in same area there by reducing the propagation delay. Also presence of cache reduces instruction/data fetch timing. Pipelining and super-scalar architectures further improves the performance of the processor. Branch prediction, speculative execution etc. are some other techniques used for improving the execution rate. Multi-cores are the new direction in improving the performance. Rather than simply stating the clock frequency of the processor which has limited significance to its processing power, it makes more sense to describe the capability in a standard notation. MIPS (Million Instructions per Second) or MIPS/MHz was an earlier notation followed by Dhrystones and latest EEMBC’s Core Mark. Core Mark is one of the best ways to compare the performance of various processors. Processor architectures with support for extra instruction can help improving performance for specific applications. For example, SIMD (Single Instruction/Multiple Data) set and Jazelle – Java acceleration can help in improving multimedia and JVM execution speeds. So size of cache, processor architecture, instruction set etc. has to be taken in to account when comparing the performance. 2. Power: Increasing the logic density and clock speed has adverse impact on power requirement of the processor. A higher clock implies faster charge and discharge cycles leading to more power consumption. More logic leads to higher power density there by making the heat dissipation difficult. Further with more emphasis on greener technologies and many systems becoming battery operated, it is important the design is for optimal power usage. Techniques like frequency scaling – reducing the clock frequency of the processor depending on the load, voltage scaling – varying the voltage based on load can help in achieving lower power usage. Further asymmetric multiprocessors, under near idle conditions, can effectively power off the more powerful core and load the less powerful core for performing the tasks. SoC comes with advanced power gating techniques that can shut down clocks and power to unused modules. 3. Memory: Usually, designers make the decision to use internal or external memory after they define the required amounts of code space and data memory. Internal memory is typically the most cost effective memory type, but it is also the least flexible. For this reason, designers must determine future growth possibilities and whether there is an upgrade path to microcontrollers with larger code space. Since cost is always a factor, the microcontroller with the least amount of memory to fit the application is typically selected. Therefore, care must be taken when predicting code size, since an increase in code size might require a different microcontroller. 4. Peripheral Set: Every system design needs, apart from the processor, many other peripherals for input and output operations. Since in an embedded system, almost all the processors used are SoCs, it is better if the necessary peripherals are available in the chip itself. This offers various benefits compared to peripherals in external IC’s such as optimal power architecture, effective data communication using DMA etc. So it is important to have peripheral set in consideration when selecting the processor. Maharashtra State Board of Technical Education 2 Emerging Trends in Electronics (22636) w.e.f 2022-23 5. Operating Voltages: Each and every processor will have its own operating voltage condition. The operating voltage maximum and minimum ratings will be provided in the respective data sheet or user manual. While higher end processors typically operate with 2 to 5 voltages including 1.8V for Cores/Analogue domains, 3.3V for IO lines, needs specialized PMIC devices, it is a deciding factor in low end micro-controllers based on the input voltage. For example it is cheaper to work with a 5V micro-controller when the input supply is 5V and 3.3 micro-controllers when operated with Li-on batteries. 6. Specialized Processing Units: Apart from the core, presence of various co-processors and specialized processing units can help achieving necessary processing performance. Co- processors execute the instructions fetched by the primary processor thereby reducing the load on the primary. Some of the popular co-processors include Floating Point Co-processor: RISC cores supports primarily integer only instruction set. Hence presence of a FP co-processor can be very helpful in application involving complex mathematical operations including multimedia, imaging, codecs, signal processing etc. Graphic Processing Unit: GPU (Graphic Processing Unit) also called as Visual processing unit is responsible for drawing images on the frame buffer memory to be displayed. Since human visual perception needed at-least 16 Frames per second for a smooth viewing, drawing for HD displays involves a lot of data bandwidth. Also with increasing graphic requirements such as textures, lighting shadesetc, GPU’s have become a mandatory requirements for mobile phones, gaming consoles etc. Various GPU’s like ARM’s MALI, Power, and OpenGLetc are increasing available in higher end processors. Choosing the right co-processor can enable smooth design of the embedded application. Digital Signal Processor: DSP is a processor designed specifically for signal processing applications. Its architecture supports processing of multiple data in parallel. It can manipulate real time signal and convert to other domains for processing. DSP’s are either available as the part of the SoC or separate in an external package. DSP’s are very helpful in multimedia applications. It is possible to use a DSP along with a processor or use the DSP as the main processor itself. 7. Price: Various considerations discussed above can be taken in to account when a processor is being selected for an embedded design. It is better to have some extra buffer in processing capacities to enable enhancements in functionality without going for a major change in the design. While engineers (especially software/firmware engineers) will want to have all the functionalities, price will be the determining factor when designing the system and choosing the right processor. 1.2 ARM 1.2.1 Introduction: Advanced RISC Machine (ARM) designs microprocessor technology that lies at the heart of advanced digital products, from mobile phones and digital cameras to games consoles and automotive systems, and is leading intellectual property (IP) provider of high-performance, low- cost, power-efficient RISC processors, peripherals, and system-on-chip (SoC) designs through Maharashtra State Board of Technical Education 3 Emerging Trends in Electronics (22636) w.e.f 2022-23 involvement with organizations such as the Virtual Socket Interface Alliance (VSIA) and Virtual Component Exchange (VCX). ARM also offers design and software consulting services. ARM's architecture is compatible with all four major platform operating systems: Symbian OS, Palm OS, Windows CE, and Linux. As for software, ARM also works closely with its partners to provide optimized solutions for existing market segments. These benefits are making the ARM company a complete solution provider. With over forty partners licensed to use its architecture, ARM enables Original Equipment Manufacturers (OEM) to realize an accelerated time-to-market through complete product offerings, such as Prime Cell Peripherals, embedded software IP, development tools, training, and support The Company offers a complete solution that is essential to the manufacturing process. Although ARM does not manufacture processors itself, ARM licenses its cores to semi-conductor manufacturers to be integrated into ASIC standards and then the company in using test chips manufactured by its partners to measure and validate the functionality of the core. ARM is able to accelerate OEM time-to-market by capitalizing on its architecture. By providing the IP and supporting services, customers can gain a jump on their design cycle and obtain a competitive edge in their targeted market segment. At that point, the architecture is portable to further product generations or applications as all code creation is directly compatible with any future architecture produced by ARM. ARM's Global Technology Partner Network is the largest in the industry, spanning from Semiconductor manufacturers to distributors. ARM has worked diligently to ensure that the partnerships provide proven solutions in real-time operating systems (RTOS), EDA tools, development systems, applications software, and design consulting, all built around the ARM Architecture. The ARM Company is working to establish standards, not just within the company, but across the industry by taking advantage of leadership opportunities in the creation of standards. ARM is the industry standard embedded microprocessor architecture, and is a leader in low-power high performance cores. ARM also has a large partner network supporting the entire design and development cycle. ARM is a full-solutions provider, supporting a broad range of applications. 1.2.2 Basic of ARM architecture: ARM architecture is not synonymous with the single organization. But there is certain commonality across the different variants. Basic ARM Organization. As shown in Fig 1.1 ARM Organization consists of register bank. It is connected to the ALU by two buses A and B. A is connected directly to ALU and B is connected through Barrel shifter. This Barrel shifter can actually preprocess the data which can come from one of this source registers; and the Barrel shifter can shift to the left, shift to the right or even rotate the data before it is fed to the ALU.Now, since all of these blocks i.e.ALU, Barrel shifter is also combinational circuit. So, the entire, all these operations that is operation that ALU carries out as well as operation that Barrel shifter carries out can take place in one cycle itself and that actually splits up to the operation execution speed. Register bank can generate the address also. In fact the PC address is, PC also is part of the register bank and that can generate the address. As well as the other register banks, can be made use of for generation for manipulation of address. Because registers are in a way symmetric they can have both address as well as the data and they can be operated in a symmetric way. The PC generates the address for the instruction. Maharashtra State Board of Technical Education 4 Emerging Trends in Electronics (22636) w.e.f 2022-23 Other operations can also be done using these registers. Instruction decodes and control provides a control signal. Address bus is 0 to 31 that means it is a 32 bit. Data buses are also 32 bits, so it is basically a 32 bit processor. It can operate on 32 bit operands and the addresses that it generates are also 32 bit. Register bank has a very prominent role. Fig 1.1 ARM7 TDMI Core Diagram All registers are 32 bits because data bus is 32 bit, operating at 32 bit operands as well as addresses are also 32 bits. There are 16 data registers in user mode and 2 data registers are visible. User mode is a common operating mode. Used by user when running program on ARM. Data registers are typically r0 to r15 and in fact in ARM, all registers are refer to by r followed by a number. So, here we are talking about data registers r0 to r15 which are visible in the user mode. Out of these registers, 3 registers perform special function they are r13, r14 and r15. R13 is a stack pointer, so this stack pointer refers to the entry point on the stack and this is critical for implementation of a stack in the memory. R14 is a link register. This link register is a register where return address is put whenever a subroutine is called. Here, we have got a single link register and in the link register the return address is put in. Then r15 is the program counter and obviously the current instruction what is being executed will be pointed to by the content of r15. Now, depending on the context registers r13 and r14 can also be used as general purpose registers. In addition there are 2 status registers. CPSR, (current program status register) and SPSR s (saved program status register). These are basically the status registers which are not data registers. So, here in this registers effectively the status of the current execution is being captured. In fact this status can include status of your program as well as that of the processor. Maharashtra State Board of Technical Education 5 Emerging Trends in Electronics (22636) w.e.f 2022-23 And when it is operating in your 32 bit it is assume that all instructions are word aligned. That means all 32 bit instructions start at 32 bit boundary. And what does that imply, that implies that PC value is stored effectively in bits from 2 to 31, bit numbers 2 to 31, with bits 1, 0 effectively undefined or not really useful for referring to an instruction. Now, obviously this discussion refers to one fact that 32 bit address in ARM refers to byte locations. Each byte with associated with a unique address so, talking about 32 bit boundaries means effectively talking about what blocks of 4 bytes. So, if there is one instruction starting at location 0 then that instruction will occupy location 0, 1, 2 as well as 3. The next instruction would be located at 4 so, therefore these 2 bits, the least significant bits of PC that is r15 or in a way do not care for operations. So, that is why PC value is effectively stored in bits from 2 to 31. Status register CPSR: CPSR is the current program status register; it has got a number of bits. Again it will be a 32 bit register; it is not that all bits are used at the same time. The condition code flags which occupy the higher that MSB that is most significant bits in the status register; they are standard flags which reflect various arithmetic conditions. Negative flag results from ALU which is typically the most significant bit, it is associated with the most significant bit. If it is one then it can be interpreted as a negative result when we are doing signed arithmetic set, Z indicates 0, C is the carry and V is overflow. There is this sticky overflow flag, this is with reference to saturation arithmetic. There are two levels of interrupts. With Interrupt, disable bits. So, user can enable or disable these two levels of interrupts by using these 2 bits. This T- bit indicates whether processor is in thumb mode or not thumb mode because when user have an embedded 16 bit processor into the 32 bit architecture, we shall be making use of this T bit to know whether operating in the thumb mode or ordinary 32 bit mode and rest are mode bits and these mode bits really defined what is called the mode of processors operation. User can use about 16 data registers, in program and normal operation and that is user mode. These modes are specified by these bits. Saturation: Saturation means when we reach the maximum value or the minimum value because of an arithmetic operation which may have overflow or underflow. Processor modes are either privileged or non-privileged mode. In a privileged mode, it is expected to have full read-write access to the CPSR. In a non-privileged mode only read access to the control field of CPSR but read-write access to the condition flags. Implication of these privileged and non- privileged modes: In a privileged mode what can happen actually, in a privileged modes as you can change the control bits that means you can have a full read as well as write access of the control bits. You can actually change the processor mode, you can enable, disable the interrupts. So, this is a privileged operation. In a non- privileged mode, these control fields can be simply read but cannot be changed, but the condition flags which can change because of an arithmetic operation would normally reflect the status of the arithmetic operation and that should be remain write enable even in non-privileged modes. So, typically you will find that when we talk about these kind of operations, a typically user program is expected to run in a non- privileged mode because in user program is normally not expected to change the control bits. In privileged mode typically user will expect the OS or the supervisory cell to run. Since user is targeting for ARM for more sophisticated applications, typically there would be an OS running in an ARM based system under which user programs are expected to execute. The OS is typically expected to be running in privileged mode and user applications running in non- privileged mode. Maharashtra State Board of Technical Education 6 Emerging Trends in Electronics (22636) w.e.f 2022-23 In fact ARM has got 7 modes and these 7 modes can be now classified as privileged and non- privileged. In fact the privileged modes are abort, first interrupt request, supervisor system and another is undefined. Supervisor mode is a state in which processor goes in after reset and generally it is a mode in which the OS kernel is supposed to operate because obviously when the processor is reset, the first thing that its excepted to execute is an operating system code and not user application of program. So, this is a supervisor mode in which the processor goes in when the reset happens. The other two privileged modes are system mode and undefined mode. In a system mode, is a special version of user mode that allows full read-write access of CPSR. It is also targeted for supervisory applications; many of the OS routines can be configured to run in the system mode. The undefined mode, processer enters this undefined mode when it encounters an undefined instruction that means when user is trying to use an illegal op-code for undefined instruction, the instruction undefined for particular processor, and then it goes into an undefined. ARM has got 37 registers in all and typically 20 registers are hidden from program at different times. So, they are not visible registers and they are actually called banked registers and this banked registers becomes available only when processors is in a particular mode. In fact processors modes other than system mode have a set of associated banked registers that are subset of these 16 registers that we have talked about in the user mode. These banked registers have one-to-one mapping with the user mode registers. In the user mode there are the 16 data registers which are available, and the current program which is getting executed, that status would get reflected in the CPSR register. Now, if the processor goes into some other mode, FIQ is first interrupt; IRQ is interrupt request mode. Now, in an FIQ mode, what we will find that have got banked register r8, r9, r10, r11, r12 becoming available as well as r13 and r14. It implies that if programmer is having an interrupt service routine which is operating in FIQ that is which is basically serving in the interrupt, in the first interrupt mode, it can use r8, r9 to r14 without bothering about what happens to the original content of these registers. Fig 1.2 Register organization Maharashtra State Board of Technical Education 7 Emerging Trends in Electronics (22636) w.e.f 2022-23 Register organization: There are 37 total registers divided among seven different processor modes. Figure 1.2 shows the bank of registers visible in each mode. User mode, the only non- privileged mode, has the least number of total registers visible. It has no SPSR and limited access to the CPSR. FIQ and IRQ are the two interrupt modes of the CPU. Supervisor mode is the default mode of the processor on start up or reset. Undefined mode traps unknown or illegal instructions when they are passed through the pipeline. Abort mode traps illegal memory accesses as a result of fetching instructions or accessing data. Finally, system mode, which uses the user mode bank of registers, was introduced to provide an additional privileged mode when dealing with nested interrupts. Each additional mode offers unique registers that are available for use by exception handling routines. These additional registers are the minimum number of registers required to preserve the state of the processor, save the location in code, and switch between modes. FIQ mode, however, has an additional five banked registers to provide more flexibility and higher performance when handling critical interrupts. When the ARM core is in Thumb state, the registers banks are split into low and high register domains. The majority of instructions in Thumb state have a 3-bit register specifier. As a result, these instructions can only access the low registers in Thumb, R0 through R7. The high registers, R8 through R15, have more restricted use. Only a few instructions have access to these registers. TDMI: T-D-M-I stands for Thumb, which is a 16-bit instruction set extension to the 32-bit ARM architecture, referred as states of the processor. "D" and "I" together comprise the on-chip debug facilities offered on all ARM cores. These stand for the Debug signals and Embedded ICE logic, respectively. The “M” signifies the support for 64-bit results and an enhanced multiplier, resulting in higher performance. This multiplier is now standard on all ARMv4 architectures and above. Thumb 16-bit Instructions: With growing code and data size, memory contributes to the system cost. The need to reduce memory cost leads to smaller code size and the use of narrower memory. Therefore ARM developed a modified instruction set to give market-leading code density for compiled standard C language. There is also the problem of performance loss due to using a narrow memory path, such as a 16-bit memory path with a 32-bit processor. The processor must take two memory access cycles to fetch an instruction or read and write data. To address this issue, ARM introduced another set of reduced 16-bit instructions labeled Thumb, based on the standard ARM 32-bit instruction set. For Thumb to be used, the processor must go through a change of state from ARM to Thumb in order to begin executing 16-bit code. This is because the default state of the core is ARM. Therefore, every application must have code at boot up that is written in ARM. If the application code is to be compiled entirely for Thumb, then the segment of ARM boot code must change the state of the processor. Once this is done, 16-bit instructions are fetched seamlessly into the pipeline without any result. It is important to note that the architecture remains the same. The instruction set is actually a reduced set of the ARM instruction set and only the instructions are 16-bit; everything else in the core still operates as 32-bit. An application code compiled in Thumb is 30% smaller on average than the same code compiled in ARM and normally 30% faster when using narrow 16-bit memory systems. Maharashtra State Board of Technical Education 8 Emerging Trends in Electronics (22636) w.e.f 2022-23 1.2.3 ARM7TDMI Processor Core Architecture version 4T: 1 3-stage pipeline 2 Unified bus architecture 3 32-bit ARM ISA plus 16-bit Thumb extension 4 Forward compatible code 5 Embedded ICE on-chip debug 6 Hard Macro cell IP 7 Smallest Die Size: 0.53 mm2 on 0.18 μm process 8 Up to 110 MHz on TSMC standard 0.18 μm 9 Industry leading 0.25 mW/MHz The ARM7TDMI has a core based on the fourth version of the ARM architecture. This implementation uses a three stage pipeline - a standard fetch-decode-execute organization. It features a unified cache, as well as the Thumb extension permitting 32-bit and 16-bit operation. It is completely forward compatible, meaning that any code written for this core will be compatible with any new core releases, such as ARM9 or ARM10. This core also includes the on-chip debug extension discussed in the previous training module. The core is successful mainly because of the extremely small but high performance processor - slightly more than 70,000 transistors in all with extremely low power consumption. The ARM7TDMI family is popular with applications where small die size, high performance, and low power consumption help reduce system costs, especially when the system does not require cache. Applications include cellular phones, MP3 players, and mass storage. ARM7TDMI applications: The standard ARM7TDMI processor core is a 'hard' macrocell, which is to say that it is delivered as a piece of physical layout, customized to the appropriate process technology. The ARM7TDMI- S is a synthesizable version of the ARM7TDMI, delivered as a high-level language module which can be synthesized using any suitable cell library in the target technology. It is therefore easier to port to a new process technology than is the hard macrocell. The synthesis process supports a number of optional variations on the processor core functionality. These include: a. Omitting the Embedded ICE cell; b. Replacing the full 64-bit result multiplier with a smaller and simpler multiplier that supports only the ARM multiply instructions that produce a 32-bit result. Either of these options will result in a smaller synthesized macrocell with reduced functionality. The full version is 50% larger and 50% less power-efficient than the hard macrocell. The ARM7TDMI processor core has found many applications in systems with simple memory configurations, usually including a few kilobytes of simple on-chip RAM. Example is a mobile telephone handset where the same chip usually incorporates sophisticated digital signal processing hardware and associated 1.3 Arduino: 1.3.1 Introduction: Arduino is an open-source hardware and software platform, project and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its products are licensed under the GNU Lesser General Public License (LGPL) or the GNU General Public License (GPL), permitting the manufacture of Maharashtra State Board of Technical Education 9 Emerging Trends in Electronics (22636) w.e.f 2022-23 Arduino boards and software distribution by anyone. Arduino boards are available commercially in preassembled form or as do-it-yourself (DIY) kits. Arduino board designs use a variety of microprocessors and controllers. The boards are equipped with sets of digital and analog input/output (I/O) pins that may be interfaced to various expansion boards or breadboards (shields) and other circuits. The boards feature serial communications interfaces, including Universal Serial Bus (USB) on some models, which are also used for loading programs from personal computers. The microcontrollers can be programmed using C and C++ programming languages. In addition to Using traditional compiler tool chains, The Arduino project provides an integrated development environment (IDE) based on the Processing language project. Arduino UNO R3 board: The Arduino Uno R3 is a microcontroller board based on a removable, dual-inline-package (DIP) ATmega328 AVR microcontroller. Features: 1. 14 Digital IO pins (pins 0–13) these can be inputs or outputs, which is specified by the sketch you create in the IDE. 2. 6 Analogue In pins (pins 0–5) These dedicated analogue input pins take analogue values (i.e., voltage readings from a sensor) and convert them into a number between 0 and 1023. 3. 6 Analogue output pins (pins 3, 5, 6, 9, 10, and 11) these are actually six of the digital pins that can be reprogrammed for analogue output using the sketch user can create in the IDE. 4. The board can be powered from user’s computer’s USB port, most USB chargers, or an AC adapter (9 volts recommended, 2.1mm barrel tip and center positive). If there is no power supply plugged into the power socket, the power will come from the USB board, but as soon as user can plug a power supply, the board will automatically use it. Programs can be loaded on to it from the easy-to-use Arduino computer program. The Arduino has an extensive support community, which makes it a very easy way to get started working with embedded electronics. The R3 is the third, and latest, revision of the Arduino Uno shown in Fig 1.3. Fig 1.3Arduino R3 UNO Board Table 1.1 Atmel chips used in Arduino boards Chip Number On-Chip RAM I/O pins Pin numbers Arduino Board Flash ATmega16 16K 1K 14 28 Nano or Uno ATmega328 32K 2K 14 28 Nano or Uno Maharashtra State Board of Technical Education 10 Emerging Trends in Electronics (22636) w.e.f 2022-23 ATmega328p (p) stands for low (Pico) Power consumption other features same as 328 ATmega2560 256K 4K 54 100 Mega 1.3.2 AVR Overview The AVR is a modified Harvard architecture machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions Basic families: AVRs are generally classified into following: Tiny AVR — The AT tiny series 1 0.5–16 kB program memory 2 6–32-pin package 3 Limited peripheral set MegaAVR — The ATmega series 1 4–256 kB program memory 2 28–100-pin package 3 Extended instruction set (multiply instructions and instructions for handling larger program memories) 4 Extensive peripheral set XMEGA — The ATXmega series 1 16–384 kB program memory 2 44–64–100-pin package (A4, A3, A1) 3 32-pin package : XMEGA-E (XMEGA8E5) 4 Extended performance features, such as DMA, "Event System", and cryptography support. 5 Extensive peripheral set with ADCs Application-specific AVR MegaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN, etc. FPSLIC (AVR with FPGA) 1 FPGA 5K to 40K gates 2 SRAM for the AVR program code, unlike all other AVRs 3 AVR core can run at up to 50 MHz 32-bit AVRs In 2006 Atmel released microcontrollers based on the 32-bit AVR32 architecture. They include SIMD and DSP instructions, along with other audio- and video-processing features. This 32-bit family of devices is intended to compete with the ARM-based processors. The instruction set is similar to other RISC cores, but it is not compatible with the original AVR or any of the various ARM cores. Maharashtra State Board of Technical Education 11 Emerging Trends in Electronics (22636) w.e.f 2022-23 1.2.3 AVR ATmega328 Microcontroller Pin Diagram and High-Level Block Diagram: Fig 1.4 ATmega 328 Pin Diagram Fig 1.5 ATmega 328 block diagram Device architecture: Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips. Maharashtra State Board of Technical Education 12 Emerging Trends in Electronics (22636) w.e.f 2022-23 Program memory Program instructions are stored in non-volatile flash memory. Although the MCUs are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 kB of flash, while the ATmega32x line has 32 kB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips. Internal data memory The data address space consists of the register file, I/O registers, and SRAM. Internal registers The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices. In the tinyAVR and megaAVR variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (000016–001F16), followed by 64 I/O registers (002016–005F16). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as memory-mapped I/O (006016–00FF16). Actual SRAM starts after these register sections, at address 006016 or, in devices with “extended I/O”, at 010016. Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can still be addressed and manipulated as if they were in SRAM. The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 000016, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the LPM instruction is unnecessary and omitted. In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (000016–0FFF16). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (100016–1FFF16). The actual SRAM is located after these ranges, starting at 200016. GPIO ports: Each General Purpose Input Output (GPIO) port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDRx, PORTx and PINx, where x is the port identifier. 1. DDRx: Data Direction Register configures the pins as either inputs or outputs. Maharashtra State Board of Technical Education 13 Emerging Trends in Electronics (22636) w.e.f 2022-23 2. PORTx: Output port register. Sets the output value on pins configured as outputs. Enables or disables the pull-up resistor on pins configured as inputs. 3. PINx: Input register, used to read an input signal. On some devices (but not all, check the datasheet), this register can be used for pin toggling: writing a logic one to a PINx bit toggles the corresponding bit in PORTx, irrespective of the setting of the DDRx bit. AVRXmega have additional registers for push/pull, totem-pole and pull-up configurations. EEPROM: Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions, which makes EEPROM access much slower than other internal RAM. However, some devices in the Secure AVR (AT90SC) family use a special EEPROM mapping to the data or program memory, depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space. Since the number of writes to EEPROM is not unlimited — Atmel specifies 100,000 write cycles in their datasheets — a well-designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed. Note that erase and write can be performed separately in many cases, byte-by-byte, which may also help prolong life when bits only need to be set to all 1s (erase) or selectively cleared to 0s (write). Program execution: Atmel's AVRs have a two-stage, single-level pipeline design. This means the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among eight-bit microcontrollers. The AVR processors were designed clock speed to be optimized with the efficient execution of compiled C code in mind and have several built-in pointers for the task. MCU speed: The AVR line can normally support clock speeds from 0 to 20 MHz, with some devices reaching 32 MHz Lower-powered operation usually requires a reduced clock speed. All recent (Tiny, Mega, and XMega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Some AVRs also have a system clock prescaler that can divide down the system clock by up to 1024. This prescaler can be reconfigured by software during run-time, allowing the. Since all operations (excluding multiplication and 16-bit add/subtract) on registers R0–R31 are single-cycle, the AVR can achieve up to 1 MIPS per MHz, i.e. an 8 MHz processor can achieve up to 8 MIPS. Loads and stores to/from memory take two cycles, branching takes two cycles. Branches in the latest "3-byte PC" parts such as ATmega2560 are one cycle slower than on previous devices. Maharashtra State Board of Technical Education 14 Emerging Trends in Electronics (22636) w.e.f 2022-23 Development: AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core, but with different peripheral and memory combinations. Compatibility between chips in each family is fairly good, although I/O controller features may vary. Features: Current AVRs offer a wide range of features: 1. Multifunction, bi-directional general-purpose I/O ports with configurable, built-in pull-up resistors 2. Multiple internal oscillators, including RC oscillator without external parts 3. Internal, self-programmable instruction flash memory up to 256 kB (384 kB on XMega) 4. In-system programmable using serial/parallel low-voltage proprietary interfaces or JTAG 5. Optional boot code section with independent lock bits for protection 6. On-chip debugging (OCD) support through JTAG or debug WIRE on most devices 7. The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP. By default, AVRs with JTAG come with the JTAG interface enabled. 8. Debug WIRE uses the /RESET pin as a bi-directional communication channel to access on- chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin. 9. Internal data EEPROM up to 4 kB 10. Internal SRAM up to 16 kB (32 kB on XMega) 11. External 64 kB little endian data space on certain models, including the Mega8515 and Mega162. 12. The external data space is overlaid with the internal data space, such that the full 64 kB address space does not appear on the external bus and accesses to e.g. address 010016 will access internal RAM, not the external bus. 13. In certain members of the XMega series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16 MB of data memory to be directly addressed. 14. AVRs generally do not support executing code from external memory. Some ASSPs using the AVR core do support external program memory. 15. 8-bit and 16-bit timers 16. PWM output (some devices have an enhanced PWM peripheral which includes a dead-time generator) 17. Input capture that record a time stamp triggered by a signal edge 18. Analog comparator 19. 10 or 12-bit A/D converters, with multiplex of up to 16 channels 20. 12-bit D/A converters 21. A variety of serial interfaces, including 22. I²C compatible Two-Wire Interface (TWI) 23. Synchronous/asynchronous serial peripherals (UART/USART) (used with RS-232, RS-485, and more) 24. Serial Peripheral Interface Bus (SPI) 25. Universal Serial Interface (USI): a multi-purpose hardware communication module that can be used to implement an SPI, I2C or UART interface. 26. Brownout detection 27. Watchdog timer (WDT) Maharashtra State Board of Technical Education 15 Emerging Trends in Electronics (22636) w.e.f 2022-23 28. Multiple power-saving sleep modes 29. Lighting and motor control (PWM-specific) controller models 30. CAN controller support 31. USB controller support 32. Proper full-speed (12 Mbit/s) hardware & Hub controller with embedded AVR. 33. Also freely available low-speed (1.5 Mbit/s) (HID) bit banging software emulations 34. Ethernet controller support 35. LCD controller support 36. Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DC–DC up converter) 37. Pico Power devices 38. DMA controllers and "event system" peripheral communication. 39. Fast cryptography support for AES and DES 1.3.4 Programming interfaces: There are many means to load program code into an AVR chip. The method to program AVR chips varies from AVR family to family. Most of the methods described below use the RESET line to enter programming mode. In order to avoid the chip accidentally entering such mode, it is advised to connect a pull-up resistor between the RESET pin and the positive power supply. ISP: The in-system programming (ISP) programming method is functionally performed through SPI, plus some twiddling of the Reset line. As long as the SPI pins of the AVR are not connected to anything disruptive, the AVR chip can stay soldered on a PCB while reprogramming. All that is needed is a 6-pin connector as shown in Fig 1.6 (a) and programming adapter. This is the most common way to develop with an AVR. Also sometimes 10 pin connector is used as shown in Fig 1.6(b) (a) 6 Pin (b) 10 pin Fig 1.6 ISP header The Atmel AVRISP MKII device connects to a computer's USB port and performs in-system programming using Atmel's software. AVRDUDE (AVR Downloader/UploadEr) runs on Linux, FreeBSD, Windows, and Mac OS X, and supports a variety of in-system programming hardware, including Atmel AVRISP MKII, Atmel JTAG ICE, older Atmel serial-port based programmers, and various third-party and "do-it- yourself" programmers. Bootloader: Microcontrollers are usually programmed through a programmer unless you have a piece of firmware in your microcontroller that allows installing new firmware without the need of an external programmer. This is called a boot loader. Maharashtra State Board of Technical Education 16 Emerging Trends in Electronics (22636) w.e.f 2022-23 Most AVR models can reserve a boot loader region, 256 Byte to 4 KB, where re-programming code can reside. At reset, the bootloader runs first and does some user-programmed determination whether to re-program or to jump to the main application. The code can re-program through any interface available, or it could read an encrypted binary through an Ethernet adapter like PXE. OptibootBootloader is a Small and Fast Bootloader used for Arduino and other Atmel AVR chips. ROM: AVRs are available with a factory mask-ROM rather than flash for program memory. Because of the large up-front cost and minimum order quantity, a mask-ROM is only cost-effective for high- production runs. Debugging interfaces: The AVR offers several options for debugging, mostly involving on-chip debugging while the chip is in the target system. Debug WIRE: Debug WIRE is Atmel's solution for providing on-chip debug capabilities via a single microcontroller pin. It is particularly useful for lower pin count parts which cannot provide the four "spare" pins needed for JTAG. The JTAGICE MKII and the AVR Dragon support debug WIRE. Debug WIRE was developed after the original JTAGICE release, and now clones support it. JTAG: The Joint Test Action Group (JTAG) feature provides access to on-chip debugging functionality while the chip is running in the target system. JTAG allows accessing internal memory and registers, setting breakpoints on code, and single-stepping execution to observe system behavior. 1.4 Arduino IDE: 1.4.1 Arduino IDE: Arduino IDE, the piece of software you run on your computer. You use the IDE to create a sketch (a little computer program) that you upload to the Arduino board. The sketch tells the board what to do. Features: 1. Cross-platform - The Arduino Software (IDE) runs on Windows, Macintosh OSX, and Linux operating systems. Most microcontroller systems are limited to Windows. 2. Simple, clear programming environment - The Arduino Software (IDE) is easy-to-use for beginners, yet flexible enough for advanced users to take advantage of as well. For teachers, it's conveniently based on the Processing programming environment, so students learning to program in that environment will be familiar with how the Arduino IDE works. 3. Open source and extensible software - The Arduino software is published as open source tools, available for extension by experienced programmers. The language can be expanded through C++ libraries, and people wanting to understand the technical details can make the leap from Arduino to the AVR C programming language on which it's based. Similarly, you can add AVR-C code directly into your Arduino programs if you want to. Maharashtra State Board of Technical Education 17 Emerging Trends in Electronics (22636) w.e.f 2022-23 Sketch: A sketch is a program written with the Arduino IDE. Sketches are saved on the development computer as text files with the file extension.ino. Arduino Software (IDE) pre-1.0 saved sketches with the extension.pde. The programming cycle on Arduino is basically as follows: » Plug your board into a USB port on your computer. » Write a sketch that will bring the board to life. » Upload this sketch to the board through the USB connection and wait a couple of seconds for the board to restart. » The board executes the sketch that you wrote. 1.4.2 Arduino C/C++ program functions:  setup() : This function is called once when a sketch starts after power-up or reset. It is used to initialize variables, input and output pin modes, and other libraries needed in the sketch. It is analogous to the function main ().  loop() : After setup() function exits (ends), the loop() function is executed repeatedly in the main program. It controls the board until the board is powered off or is reset. It is analogous to the function while(1) Special symbols Arduino includes a number of symbols to delineate lines of code, comments, and blocks of code. ; (semicolon) every instruction (line of code) is terminated by a semicolon. This syntax lets you format the code freely. You could even put two instructions on the same line, as long as you separate them with a semicolon. (However, this would make the code harder to read.) Example: delay (100); {} (curly braces) This is used to mark blocks of code. For example, when you write code for the loop() function, you have to use curly braces before and after the code. Example: void loop() { Serial.println("MSBTE"); } C/Arduino: These are portions of text ignored by the Arduino processor, but are extremely useful to remind yourself (or others) of what a piece of code does. There are two styles of comments in Arduino: // single-line: this text is ignored until the end of the line Constants: Arduino includes a set of predefined keywords with special values. HIGH and LOW are used, for example, when you want to turn on or off an Arduino pin. INPUT and OUTPUT are used to set a specific pin to be either and input or an output true and false indicate exactly what their names suggest: the truth or false hood of a condition or expression. Maharashtra State Board of Technical Education 18 Emerging Trends in Electronics (22636) w.e.f 2022-23 Variables: Variables are named areas of the Arduino’s memory where you cans tore data that you can use and manipulate in your sketch. As the name suggests, they can be changed as many times as you like. Because Arduino is a very simple processor, when you declare a variable you have to specify its type. This means telling the processor the size of the value you want to store. Here are the datatype that are available: Boolean Can has one of two values: true or false. Char holds a single character, such as A. Like any computer, Arduino stores it as a number, even though you see text. When chars are used to store numbers, they can hold values from –128 to 127. Control Structures: Arduino includes keywords for controlling the logical flow of your sketch. if... else This structure makes decisions in your program. If must be followed by a question specified as an expression contained in parentheses. If the expression is true, whatever follows will be executed. If it’s false, the block of code following else will be executed. It’s possible to use just if without providing an else clause. Example: if (val == 1) { digitalWrite(LED,HIGH); } for Lets you repeat a block of code a specified number of times. Example: for (int i = 0; i < 10; i++) { Serial.print("MSBTE"); } switch case The if statement is like a fork in the road for your program. switch case is like a massive roundabout. It lets your program take a variety of directions depending on the value of a variable. It’s quite useful to keep your code tidy as it replaces long lists of if statements. Example: switch (sensorValue) { case 23: digitalWrite(13,HIGH); break; case 46: digitalWrite(12,HIGH); break; default: // if nothing matches this is executed digitalWrite(12,LOW); digitalWrite(13,LOW); } while Similar to if, this executes a block of code while a certain condition is true. Example: // blink LED while sensor is below 512 sensorValue = analogRead(1); Maharashtra State Board of Technical Education 19 Emerging Trends in Electronics (22636) w.e.f 2022-23 while (sensorValue< 512) { digitalWrite(13,HIGH); delay(100); digitalWrite(13,HIGH); delay(100); sensorValue = analogRead(1); } do... while Just like while, except that the code is run just before the the condition is evaluated. This structure is used when you want the code inside your block to run at least once before you check the condition. Example: do { digitalWrite(13,HIGH); delay(100); digitalWrite(13,HIGH); delay(100); sensorValue = analogRead(1); } while (sensorValue< 512); Arithmetic and formulas: You can use Arduino to make complex calculations using a special syntax.+ and – work like you’ve learned in school, and multiplication is represented with an * and division with a /. There is an additional operator called “modulo” (%), which returns the remainder of an integer division. You can use as many levels of parentheses as necessary to group expressions. Contrary to what you might have learned in school, square brackets and curly brackets are reserved for other purposes (array indexes and blocks, respectively). Examples: a = 2 + 2; light = ((12 * sensorValue) - 5 ) / 2; remainder = 3 % 2; // returns 2 because 3 / 2 has remainder 1 Comparison Operators: When you specify conditions or tests for if, while, and for statements, these are the operators you can use: == equal to != not equal to greater than = greater than or equal to Boolean Operators: These are used when you want to combine multiple conditions. For example, if you want to check whether the value coming from a sensor is between 5and 10, you would write: if ((sensor => 5) && (sensor