COME321: Computer Organization Lecture Notes (Fall 2024) PDF

Electrical Engineering Dept. COME321: Computer Organization (Fall 2024) Dr. Eng. Ghada Abozaid Assistant Professor in Computer Engineering...

Electrical Engineering Dept. COME321: Computer Organization (Fall 2024) Dr. Eng. Ghada Abozaid Assistant Professor in Computer Engineering [email protected]  Chapter 7 Microprogrammed Control 2  Control Unit Implementation Hardwired Memory Instruction code Combinational. Control Sequence Counter Logic Circuits. signals Microprogrammed CAR: Control Address Register Memory Instruction code CDR: Control Data Register Next Address. Control Control CDR Decoding Generator CAR. Memory Circuit signals (sequencer) 3  Microprogrammed Control Unit Control signals – Group of bits used to select paths in multiplexers, decoders, arithmetic logic units Control variables – Binary variables specify microoperations Certain microoperations initiated while others idle Control word – String of 1’s and 0’s represent control variables 4  Microprogrammed Control Unit Control memory – Memory contains control words Microinstructions – Control words stored in control memory – Specify control signals for execution of microoperations Microprogram – Sequence of microinstructions 5  Control Memory Read-only memory (ROM) Content of word in ROM at given address specifies microinstruction Each computer instruction initiates series of microinstructions (microprogram) in control memory These microinstructions generate microoperations to – Fetch instruction from main memory – Evaluate effective address – Execute operation specified by instruction – Return control to fetch phase for next instruction Control Address Control word memory (microinstruction) (ROM) 6 Microprogrammed Control Organization External Next Address Control input Control Generator CAR Memory CDR word (sequencer) (ROM) Control memory – Contains microprograms (set of microinstructions) – Microinstruction contains Bits initiate microoperations Bits determining address sequence for control memory Control address register (CAR) – Specifies address of microinstruction 7 Microprogrammed Control Organization Next address generator (microprogram sequencer) – Determines address sequence for control memory Typical Microprogram sequencer functions – Increment CAR by one – Loads an address from control memory to CAR – Load initial address into CAR to start control operations 8  Microprogrammed Control Organization Control data register (CDR)- or pipeline register – Holds microinstruction read from control memory – Allows execution of microoperations specified by control word simultaneously with generation of next microinstruction 9  Microprogram Routines Routine – Group of microinstructions stored in control memory Each computer instruction has its own microprogram routine to generate microoperations that execute the instruction 1 0  Microprogram Routines Fetch routine – Routine to determine effective address (branch microinstruction conditioned on status bit – Microoperations to execute the fetched instruction Each instruction has its own microprogram routine stored in a given location of control memory. The transformation from instruction code bits to an address in control memory where routine is located is called mapping. 10  Microprogram Routines Subroutine – Sequence of microinstructions used by other routines to accomplish particular task Example – Subroutine to generate effective address of operand for memory reference instruction Subroutine register (SBR) – Stores return address during subroutine call 12  Address Sequencing Address sequencing capabilities required in control memory – Incrementing CAR – Unconditional or conditional branch, depending on status bit conditions – Mapping from bits of instruction to address for control memory – Facility for subroutine call and return 13  Address Sequencing Instruction code Mapping logic Status Branch MUX Multiplexers bits logic select Subroutine Control Address Register Register (SBR) (CAR) Incrementer Control memory (ROM) select a status bit Microoperations 13 Branch address  Conditional Branching Branching from one routine to another depends on status bit conditions Status bits provide parameter info such as – Carry-out of adder – Sign bit of number – Mode bits of instruction Info in status bits can be tested and actions initiated based on their conditions: 1 or 0 Unconditional branch – Fix value of status bit to 1 15  Mapping of Instruction Each computer instruction has its own microprogram routine stored in a given location of the control memory Mapping – Transformation from instruction code bits to address in control memory where routine is located 16  Mapping of Instruction Example – Mapping 4-bit operation code to 7-bit address OP-codes of Instructions ADD 0000 AND 0001 LDA 0010 Control memory Mapping bits 0 xxxx 00 Address 0 0000 00 ADD Routine 0 0001 00 AND Routine 0 0010 00 LDA Routine 17  Microprogram Example MUX 10 0 Computer AR Configuration Address Memory 2048 x 16 10 0 PC MUX 15 0 6 0 6 0 DR SBR CAR Control memory Arithmetic 128 x 20 logic and shift unit Control unit 15 0 AC 17  Microprogram Example Computer instruction format 15 14 11 10 0 I Opcode Address Four computer instructions Symbol OP-code Description ADD 0000 AC  AC + M[EA] EA is the effective address BRANCH 0001 if (AC < 0) then (PC  EA) STORE 0010 M[EA]  AC EXCHANGE 0011 AC  M[EA], M[EA]  AC Microinstruction Format 3 3 3 2 2 7 F1 F2 F3 CD BR AD F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field 19  Microinstruction Fields F1 Microoperation Symbol F2 Microoperation Symbol 000 None NOP 000 None NOP 001 AC  AC + DR ADD 001 AC  AC - DR SUB 010 AC  0 CLRAC 010 AC  AC  DR OR 011 AC  AC + 1 INCAC 011 AC  AC  DR AND 100 AC  DR DRTAC 100 DR  M[AR] READ 101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR 110 AR  PC PCTAR 110 DR  DR + 1 INCDR 111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR F3 Microoperation Symbol 000 None NOP 001 AC  AC  DR XOR 010 AC  AC’ COM 011 AC  shl AC SHL 100 AC  shr AC SHR 101 PC  PC + 1 INCPC 110 PC  AR ARTPC 111 Reserved 20  Microinstruction Fields CD Condition Symbol Comments 00 Always = 1 U Unconditional branch 01 DR(15) I Indirect address bit 10 AC(15) S Sign bit of AC 11 AC = 0 Z Zero value in AC BR Symbol Function 00 JMP CAR  AD if condition = 1 CAR  CAR + 1 if condition = 0 01 CALL CAR  AD, SBR  CAR + 1 if condition = 1 CAR  CAR + 1 if condition = 0 10 RET CAR  SBR (Return from subroutine) 11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0 21  Symbolic Microinstruction  Sample Format Label: Micro-ops CD BR AD  Label may be empty or may specify symbolic address terminated with colon  Micro-ops consists of 1, 2, or 3 symbols separated by commas NOP for no microoperation (nine 0s)  CD one of {U, I, S, Z} U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC  BR one of {JMP, CALL, RET, MAP}  AD one of {Symbolic address (label), NEXT, empty (seven 0s)} 21  Fetch Routine  Fetch routine - Read instruction from memory - Decode instruction and update PC Microinstructions for fetch routine: AR  PC DR  M[AR], PC  PC + 1 AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0 Symbolic microprogram for fetch routine: ORG 64 FETCH: PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP Binary microporgram for fetch routine: Binary address F1 F2 F3 CD BR AD 1000000 110 000 000 00 00 1000001 1000001 000 100 101 00 00 1000010 23 1000010 101 000 000 00 11 0000000  Symbolic Microprogram Control memory: 128 20-bit words First 64 words: Routines for 16 machine instructions Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20,..., 60 Partial Symbolic Microprogram Label Microops CD BR AD ORG 0 ADD: NOP I CALL INDRCT READ U JMP NEXT ADD U JMP FETCH ORG 4 BRANCH: NOP S JMP OVER NOP U JMP FETCH OVER: NOP I CALL INDRCT ARTPC U JMP FETCH ORG 8 STORE: NOP I CALL INDRCT ACTDR U JMP NEXT WRITE U JMP FETCH ORG 12 EXCHANGE: NOP I CALL INDRCT READ U JMP NEXT ACTDR, DRTAC U JMP NEXT WRITE U JMP FETCH ORG 64 FETCH: PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP INDRCT: READ U JMP NEXT 24 DRTAR U RET Design of Control Unit microoperation fields F1 F2 F3 3 x 8 decoder 3 x 8 decoder 3 x 8 decoder 76 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0 AND ADD AC Arithmetic logic and DR DRTAC shift unit PCTAR From From DRTAR PC DR(0-10) Load AC Select 0 1 Multiplexers Load Clock AR 25  Microprogram Sequencer External (MAP) L I 3 2 1 0 Input Load I0 logic S1 MUX1 SBR T1 S0 Incrementer 1 I MUX2 Test S Z Select Clock CAR Control memory Microops CD BR AD...... 26 Input Logic for Microprogram Sequencer 1 L L(load SBR with PC) From I MUX2 Test CPU S T Input for subroutine Call Z Select BR field I0 logic S0 for next address of CS I S1 selection 1 CD Field of CS Input Logic I1I0T Meaning Source of Address S1 S0 L 000 In-Line CAR+1 00 0 001 JMP CS(AD) 01 0 010 In-Line CAR+1 00 0 011 CALL CS(AD) and SBR