1-Intro (compSysArch).pdf

CYS 408 : Architecture of Secure Operating System Topic: Intro to Computer System Architecture [email protected] Nazar Abbas Saqib , PhD 1 Agenda ▪ Inside computer ▪ Pipelining ▪ Processes and Threads ▪ Multitasking and Mutli -processing 2 Microprocessor vs Microcontroller General -...

CYS 408 : Architecture of Secure Operating System Topic: Intro to Computer System Architecture [email protected] Nazar Abbas Saqib , PhD 1 Agenda ▪ Inside computer ▪ Pipelining ▪ Processes and Threads ▪ Multitasking and Mutli -processing 2 Microprocessor vs Microcontroller General - purpose Microprocessors ➢ Must add RAM, ROM, I/O ports, and timers externally to make them functional ➢ Have the advantage of versatility on the amount of RAM, ROM, and I/O ports 3 ❑ General - purpose Microprocessors contains ➢ CPU ➢ No RAM ➢ No ROM ➢ No I/O ports 1. CPU ON CHIP 2. First µP – Intel 4004 Microprocessor vs Microcontroller Microcontroller ➢ The fixed amount of on -chip ROM, RAM, and number of I/O ports makes them ideal for many applications in which cost and space are critical ➢ In many applications, the space it takes, the power it consumes, and the price per unit are much more critical considerations than the computing power 4 ❑ Microcontroller has ➢ CPU (microprocessor) ➢ RAM ➢ ROM ➢ I/O ports ➢ Timer ➢ ADC and other peripherals 1. COMPUTER ON CHIP 2. FIRST µC – Intel 8048 What is an Embedded System? Embedded System ➢ An embedded system is combination of software and hardware that performs a specific task ➢ An embedded product uses a microprocessor (or microcontroller) to do one task and one task only ➢ There is only one application software that is typically burned into ROM ➢ Not controlled by external but its own controller ➢ e.g. Like printer, get the data and print it 5 https://www.arcweb.com/blog/embedded -systems -trends -technologies What is an Embedded System? PC (Personal Computer) ➢ A PC, in contrast with the embedded system, can be used for any number of applications ➢ It has RAM memory and an operating system that loads a variety of applications into RAM and lets the CPU run them ➢ A PC contains or is connected to various embedded products ➢ Each one peripheral has a microcontroller inside it that performs only one task 6 A Computer Model • Internal Organization of Computers can be divided into three parts: • CPU (Central Processing Unit) • I/O (Input/Output) Devices • Memory (RAM, long term storage) • CPU is a hardware in your PC and OS is the software 7 Inside the Computer CPU Connection with Peripherals and Memory Via Buses (System Bus) There are 3 types of buses: control bus , address bus, data bus 8 Keyboard, Monitor Inside the Computer Control Unit & Instruction Decoder Arithmetic/Logic Unit Registers To synchronize and control the overall operation of the P system To decode instruction and pass the necessary control signals to CU The C entral P rocessing U nit (or  P) - 3 main components To perform the arithmetic and logical operations within the CPU A set of internal storage locations within the CPU 9 Performs Arithmetic and Logic Instructions 10 Points to the address of next instruction to be executed Stores the address of the instruction under execution Decodes the instruction for execution 11 Inside the Computer Instruction Cycle (Fetch - Decode - Execute) 12 The Central Processing Unit (CPU) ■ Fetch & Execute — CPU fetches machine language instructions (such as add 1+1) and execute them ▪ The fetch and execute (also called as Fetch, Decode and Execute or FDX) process actually takes four steps ▪ Fetch Instruction 1 ▪ Decode Instruction 1 ▪ Execute Instruction 1 ▪ Write (save) result 1 ▪ The four steps take one clock cycle 13 Example: How CPU performs the following operation: Z = X + Y Suppose the following are the CPU instructions Load 10 --- Load data from memory location 10 Add 11 ---- fetch data from location 11 and add Store 12 --- store the result at memory location 12 14 Simple Microprocessor Memory Electronic Clock Arithmetic Logic Unit Accumulator Control Unit Memory Address Register Current Instruction Register Memory Data Register Program Counter Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 15 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR CIR MDR PC Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 LOAD 10 ADD 11 STORE 12 (2) (3) (R) 16 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR CIR MDR PC 100 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000000 Load 10 ADD 11 STORE 12 (2) (3) (R) PC stores the next instruction to be fetched 17 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 100 CIR MDR PC 100 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000000 Load 10 ADD 11 STORE 12 (2) (3) (R) Instruction is loaded to MAR 18 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 100 CIR MDR PC 100 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000000 Load 10 ADD 11 STORE 12 (2) (3) (R) Instruction is fetched and loaded to MDR Load 10 19 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 100 CIR MDR PC 100 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 Load 10 ADD 11 STORE 12 (2) (3) (R) Instruction is loaded to CIR from MDR & decoded Load 10 Load 10 20 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 100 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 Load 10 ADD 11 STORE 12 (2) (3) (R) PC is incremented Load 10 Load 10 21 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 100 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 Load 10 ADD 11 STORE 12 (2) (3) (R) CU starts executing the instruction Load 10 Load 10 Load 10 22 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 10 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 Load 10 ADD 11 STORE 12 (2) (3) (R) MAR is loaded with the address 10 to fetch data from his location Load 10 Load 10 Load 10 23 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 10 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000010 ADD 11 STORE 12 (2) (3) (R) Data from location is fetched and placed at MDR Load 10 Load 10 Load 10 24 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 10 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000010 ADD 11 STORE 12 (2) (3) (R) Data from MDR to Accumulator. That completes the execution of first instruction Load 10 Load 10 Load 10 00000010 25 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 00000010 ADD 11 STORE 12 (2) (3) (R) Address of next instruction is placed at MAR Load 10 Load 10 Load 10 00000010 26 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) New instruction is fetched and loaded to MDR Load 10 Load 10 Load 10 00000010 ADD 11 27 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 101 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) New instruction is loaded to CIR and decoded Load 10 Load 10 00000010 ADD 11 ADD 11 28 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) PC is incremented Load 10 Load 10 00000010 ADD 11 ADD 11 29 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) CU starts execution of the new instruction Load 10 00000010 ADD 11 ADD 11 ADD 11 30 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 101 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Data from ALU is shifted to Accumulator Load 10 ADD 11 ADD 11 ADD 11 00000010 31 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 11 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Address is placed in MAR Load 10 ADD 11 ADD 11 ADD 11 00000010 32 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 11 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Data from location 11 is fetched and placed at MDR Load 10 ADD 11 ADD 11 00000010 00000011 33 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 11 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) CPU loads data from MDR to Accumulator Load 10 ADD 11 00000010 00000011 00000011 34 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 11 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) CPU performs the addition of two numbers in ALU and store the result back to Accumulator. That completes the execution of 2 nd instruction. Load 10 ADD 11 00000011 00000101 00000101 35 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 102 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) For the 3 rd instruction, address is loaded to MAR Load 10 ADD 11 00000011 00000101 00000101 36 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 102 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) CPU brings the data from location 102 and stores at MDR Load 10 ADD 11 00000101 00000101 STORE 12 37 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 102 CIR MDR PC 102 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Instruction from MDR is loaded to CIR Load 10 00000101 00000101 STORE 12 STORE 12 38 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 102 CIR MDR PC 103 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) PC is incremented Load 10 00000101 00000101 STORE 12 STORE 12 39 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 102 CIR MDR PC 103 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Instruction is decoded and CU starts its execution Load 10 00000101 00000101 STORE 12 STORE 12 STORE 12 40 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 12 CIR MDR PC 103 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Address 12 is placed at MAR Load 10 00000101 00000101 STORE 12 STORE 12 STORE 12 41 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 12 CIR MDR PC 103 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Data from Accumulator is placed at MDR Load 10 00000101 00000101 STORE 12 STORE 12 00000101 42 Simple Microprocessor Memory Electronic Clock ALU Accumulator Control Unit MAR 12 CIR MDR PC 103 Internal Bus Special Internal Bus Structure Data Bus Data Bus Data Bus Data Bus Internal Bus Address Bus Data bus 10 11 12 … 100 101 102 00000010 00000011 ADD 11 STORE 12 (2) (3) (R) Data MDR is finally stored at location 12. That completes the execution of 3 rd instruction. Load 10 00000101 00000101 STORE 12 STORE 12 00000101 00000101 43 Pipelined vs Non - pipelined processor Non -pipelined: only a single step of a process is executed at a time. Pipelined: Pipeline combines multiple steps into one combined process, allowing simultaneously fetch, decode, execute and write steps. Each par t is called a pipelined stage; the pipeline depth is the number of simultaneous stages which may be completed at once (here 4). 44 How many instructions executed? How many clock cycles consumed? How many instructions executed? How many clock cycles consumed? 5 8 Fetch1 Fetch 2 Decode 1 Fetch1 Fetch 3 Decode 2 Execute 1 Fetch 4 Decode 3 Execute 2 Write 1 Fetch 5 Decode 4 Execute 3 Write 2 Decode 5 Execute 4 Write 3 Decode 1 Execute 1 Write 1 Fetch 2 Decode 2 Execute 2 Write 2 Write 4 Execute 5 Write 5 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 2 8 Process and Threads Process is an executable program and associated data loaded and running in a memory 45 Program Data Process Process Process may exist in multiple states: New: a process being created Ready: Processing waiting to be executed by the CPU Running: Instructions are being executed Waiting: waiting for I/O Terminate: a completed process 46 Process and Threads Process States Threads ▪ A thread is a stream of instructions within a process. ▪ Subsets of a process ▪ Threads are able to share memory ▪ Each thread has its own instruction pointer, set of registers and stack memory 47 Process and Threads •For example, in a word processor, a background thread may check spelling and grammar while a foreground thread processes user input ( keystrokes ), while yet a third thread loads images from the hard drive, and a fourth does periodic automatic backups of the file being edited. Processes and Threads in OS 48 Interrupts ▪ An interrupt indicate that an asynchronous event has occurred ▪ CPU to stop the processing its current task, save the state, and begin processing a new request ▪ When the new task is complete, CPU will complete the prior task There are software as well as hardware interrupts 49 ▪ Hardware interrupts are used by devices to communicate that they require attention from the operating system -For example, pressing a key on the keyboard or moving the mouse triggers hardware interrupts ▪ A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed -For example, a divide -by -zero exception will be thrown if the processor's arithmetic logic unit is commanded to divide a number by zero as this instruction is an error and impossible. The operating system will catch this exception, and can choose to abort the instruction Multiprogramming 50 ▪ In the image below, program A runs for some time and then goes to waiting state. In the mean time program B begins its execution. So the CPU does not waste its resources and gives program B an opportunity to run. ▪ Multiprogramming – A computer running more than one program at a time (like running Excel and Firefox simultaneously). https://www.geeksforgeeks.org/difference -between -multitasking -multithreading -and -multiprocessing/ Multiprocessing ▪ Multiprocessor OS refers to the use of two or more CPUs within a single computer system. These multiple CPUs are in a close communication sharing the computer bus, memory are other peripheral devices ▪ Two types: a) Asymmetric Multiprocessing (AMP) ▪ one operating system image per CPU acting as independent systems b) Symmetric Multiprocessing (SMP) ▪ one operating system to manage all CPUs 51 Multiprocessing occurs by means of parallel processing whereas Multi programming occurs by switching from one process to other (phenomenon called as context switching). Multitasking • Multitasking allows multiple tasks to run simultaneously on one CPU (time sharing) • Operating system such as ‘MS DOS’ are no multitasking – run one process at a time • Modern operating systems such as Linux and Windows, support multitasking • Multitasking is a logical extension of multiprogramming: for multitasking to take place firstly there should be multiprogramming – presence of multiple programs. • Pipelining is an example of multitasking 52 As depicted in the image, At any time the CPU is executing only one task while other tasks are waiting for their turn. The illusion of parallelism is achieved when the CPU is reassigned to another task. i.e all the three tasks A, B and C are appearing to occur simultaneously because of time sharing. Multithreading • Multi threading is an execution model that allows a single process to have multiple code segments (i.e., threads) running concurrently within the “context” of that process • Multi threading is the ability of a process to manage its use by more than one user at a time and to manage multiple requests by the same user without having to have multiple copies of the program. • OS makes use of complex time management multitasking algorithms – only single thread will be running at any point. • e.g. VLC media player, where one thread is used for opening the VLC media player, one thread for playing a particular song and another thread for adding new songs to the playlist. 53