VHDL Memory: Register File Design

What is the primary purpose of Register Files in digital design?

In VHDL, each flop in a register file is assumed to be a 1-bit register.

What type of logic is the 'Register File' considered to be?

In the context of memory in VHDL, memories are a common ______ in most digital design systems.

Match the signal names in a Register File with their descriptions:

What triggers the storage of inputs in a 3-bit register composed of flip-flops?

In the above-mirror display example, the 'load' signal is used to select which register's data is displayed.

In the context of the above-mirror display, what component is used to select one of the four registers based on the address inputs?

In the above-mirror display example, the component that is labeled as 1x oy will be ______ later.

Match the inputs in the above-mirror display with their likely sources or functions:

In the provided VHDL code for a register file, what is the purpose of the Dwidth generic?

The rising_edge(clk) condition in the VHDL code indicates that the register file updates only on the falling edge of the clock signal.

In the VHDL code for the register file, what signal is used to enable writing data into the register file?

In the VHDL code provided for the register file, to read a specific register, the rdata is assigned the value from the array_reg at the index given by the ______ of the raddr.

Associate each signal in the provided register file VHDL code with its data type:

In the provided VHDL code for RAM, what is the purpose of the impure function read_file?

In the RAM VHDL code, the we signal, when asserted, prevents writing to the RAM.

In the RAM VHDL code, what process is responsible for updating the data_reg signal with the data from the RAM?

In the RAM VHDL code, the size of the RAM is determined by the generic parameter A_Width, which defines the number of ______, making the RAM have 2**A_Width addressable locations.

Match the signals from the RAM VHDL code with their functions:

In the ROM VHDL code, what does the generic parameter A_Width represent?

In the ROM VHDL code, the addr signal is used to select which memory location's data is outputted.

What is the name of the process in the provided ROM VHDL code that assigns values to the rom_d signal based on the input address?

In the ROM VHDL code, the data signal is assigned the value of data_reg, which in turn gets the value from the internal signal ______.

Match each address input to its corresponding data output in the ROM VHDL code's lookup_proc:

How many 1-bit flip-flops are required to build a 3-bit register?

In synchronous logic, operations are typically triggered by a clock signal.

What does VHDL stand for?

A 2x4 decoder has two input lines and ______ output lines.

Match the memory types with their typical usage:

In the example above-mirror display using registers, what is the purpose of the registers?

The std_logic_vector data type in VHDL is used to represent a single bit value.

In VHDL, what keyword is used to define the interface of a module?

In the RAM VHDL code, the read_file function utilizes open read_mode is ______ statement.

Match the VHDL keywords with their purpose:

What will be the output (data) of the provided ROM code if addr input is "111"?

In the given ROM VHDL code, if the input addr does not match any case statement, the output rom_d will be "11111111".

In the provided RAM VHDL code, what signal directly holds the result of reading data from the RAM at a given address?

In the 3-bit register using flip-flops, the input d2 is connected to the ______ input of the first D flip-flop.

Match the given signal assignments from the ROM VHDL code with descriptions.

Referring to the Activity description for 'Above-mirror display using registers', and given the conditions a1a0 = 01, load = 1, and C = 00000111, and xy = 10, what is the value of D?

A register file can only be implemented using D flip-flops.

When using a 2x4 decoder, what is the maximum number of outputs that can be active simultaneously?

In ROM, once data is written, it is typically ______, whereas data in RAM can be easily modified.

Match the data/address widths to the corresponding memory capacity, assuming byte-addressable memory:

How many wires are needed to connect the car's computer to the above-mirror display, considering 8 data bits, 2 address bits and 1 load bit?