Verilog Operators

Verilog Operators

• Operators are pre-defined in the Verilog standard
• Operators are defined to work on specific data types
• Not all operators are synthesizable

Bitwise Logic Operators

• Perform logic functions on individual bits
• Single bit inputs result in a single bit output
• When inputs are vectors, each bit in the first vector is operated on by the bit in the same position from the second vector
• Shorter vectors are padded with leading zeros to match lengths if vectors aren't the same length

Reduction Logic Operators

• Each bit of a vector is used as an individual input into a logic operation
• Produces a single bit output
• Examples of syntax & operations
• & is for AND all bits in the vector together (1-bit result)
• ~& is for NAND all bits in the vector together (1-bit result)
• | is for OR all bits in the vector together (1-bit result)
• ~| is for NOR all bits in the vector together (1-bit result)
• ^ is for XOR all bits in the vector together (1-bit result)
• ^ or ^ is for XNOR all bits in the vector together (1-bit result)

Boolean Logic Operators

• Returns a value of TRUE (1) or FALSE (0)
• Based on a logic operation of the input operations
• Used in decision statements
• Examples
• !X is TRUE if all values in X are 0, FALSE otherwise
• X && Y is TRUE if the bitwise AND of X and Y results in all ones, FALSE otherwise
• X || Y is TRUE if the bitwise OR of X and Y results in all ones, FALSE otherwise

Relational Operators

• Returns a value of TRUE (1) or FALSE (0)
• Based on a comparison of two inputs
• Examples
• X == Y is TRUE if X is equal to Y, FALSE otherwise
• X != Y is TRUE if X is not equal to Y, FALSE otherwise
• X < Y is TRUE if X is less than Y, FALSE otherwise
• X > Y is TRUE if X is greater than Y, FALSE otherwise
• X <= Y is TRUE if X is less than or equal to Y, FALSE otherwise
• X >= Y is TRUE if X is greater than or equal to Y, FALSE otherwise

Conditional Operators

• Provides a more intuitive approach to modeling logic statements
• The keyword for the conditional operator is ?
• Syntax: = ? : ;
• Specifies a Boolean condition
• If evaluated TRUE, the true_assignment is assigned to the target
• If evaluated FALSE, the false_assignment portion of the operator is assigned to the target
• Values in this assignment can be signals or logic values
• Nested conditional operators can be implemented by inserting subsequent conditional operators in place of the false_value

Concatenation Operator

• Curly brackets (i.e., {}) are used to concatenate multiple signals
• The target must be the same size as the sum of the sizes of the input arguments

Replication Operator

• Allows vector concatenation with itself through the replication operator
• Uses double curly brackets (i.e., {{}})
• Integer indicates the number of replications to be performed
• Replication syntax is {<number_of_replications>{<vector_name_to_be_replicated>}}

Numerical Operators

• Verilog provides a set of numerical operators
• • is for Addition
• - is for Subtraction (in between arguments) or 2's complement negation (in front of arguments)
• * is for Multiplication
• / is for Division
• % is for Modulus
• ** is Raise to the power
• <<< is Shift Left (fill with zeros)
• >>> is Shift Right (fill with sign bit)
• Verilog allows the use of these operators on arguments of different sizes, types, and signs

Operator Usage Rules

• Smaller vectors are expanded to the size of the larger vector if two vectors are of different sizes
• Smaller vectors are padded with zeros if unsigned, or with the sign bit if signed
• If one of the arguments is real, arithmetic takes place using real number
• If one of the arguments is unsigned, then all arguments will be treated as unsigned

Operator Precedence

• The order of precedence for Verilog operators are listed from highest to lowest:
• Bitwise/Unary: !~+-
• Concatenation/Replication: {} {{}}
• No operation, just parenthesis: ()
• Power: **
• Binary Multiply/Divide/Modulo: */%
• Binary Addition/Subtraction: +-
• Shift Operations: << >> <<< >>>
• Greater/Less than comparison: < <= > >=
• Equality/Inequality comparison: == !=
• AND/NAND operators: & ~&
• XOR/XNOR operators: ^ ~^
• OR/NOT operators: | ~|
• Boolean AND: &&
• Boolean OR: ||
• Conditional operator: ?:

Modeling Concurrent Functionality

• Verilog is a hardware description language
• Assignments are executed concurrently unless specifically noted otherwise

Continuous Assignment with Logical Operators

• Each logical operator can be used in conjunction with concurrent signal assignments
• Used to create individual combinational logic circuits
• assign An = ~A is NOT
• assign m0 = An & Bn & Cn is AND
• assign F = m0 | m2 | m6 is OR

Continuous Assignment with Conditional Operators

• The conditional operator allows description of a continuous assignment
• Uses the Boolean conditions to affect the values of the result
• Conditional operator (?) is used in conjunction with the continuous assignment keyword assign

Continuous Assignment with Delay

• Ability to model gate delays when using a continuous assignment
• '#' is used to indicate a delayed assignment
• Delay can be specified for all transitions, for rising and falling transitions separately, and for transitions to the value off separately for combinational logic circuits
• A transition to off refers to a transition to Z
• If only one delay parameter is specified, it is used to model all delays
• If two delay parameters are specified, the first parameter is used for the rise time delay, while the second is used to model the fall time delay
• If three parameters are specified, the third parameter is used to model the transition to off
• When using delay, include the `timescale directive to provide the units of the delay being specified