ISE 250 Ch 1

• Study notes on how a program runs

Translating C to Machine Code

• The goal is to create an executable machine program
• A compiler creates the executable file
• Executables are platform-dependent and non-portable
• An executable that is compiled for one processor cannot run on a different microprocessor
• Executable file modifications may be required when switching platforms

Compiler

• Two steps in the process of compiling: Analysis and Synthesis
• Analysis, the goal is to create an Intermediate Representation (IR) that represents the original program in a simplified way
• IR aka low-level representation
• Analysis for C is assembly language
• Synthesis is the process of generating the executable from IR
• Synthesis involves performing transformations and optimizations
• Synthesis improves program execution speed or reduces program size

Executable File Format (ELF)

• The machine programs support a standard binary file specification
• Abbreviated as ELF for executable and linkable format
• ARM processors support ELF
• Two views: linking and execution

Views of ELF

• Linking: used at static link time to merge multiple files during compilation
• Execution: employed at runtime to create a process image in memory when a program is loaded and executed
• When a compiler constructs an executable file, Section Header Table can locate the content of a specific section in the ELF file by referencing: the section header table
• Text segment is binary machine code
• Read-Only segment (RO) contains the value of variables unalterable at runtime
• Read-Write (RW) segment is the initial values of statically allocated and modifiable variables
• Zero Initialised segment (Z) holds all uninitialised variables

Loading a Program into Memory

• Executable is saved to flash memory, typically several MBs
• Flash memory allows the processor to restart
• When running, the program is copied to primary memory, aka static memory, or SRAM
• Static memory (SRAM) typically has hundreds of KBs

Arrangement of Memory

• Memory is arranged serially in locations
• Each location has a unique address with 32 bits for a typical 32 bit processor
• Each location holds a byte
• It is byte-addressable
• The memory location stores a value that can represent program data or instructions

Memory Capacity

• The total addressable space is bytes, i.e., 4 GB for a 32 bit processor
• Memory is measured in KB (kilobytes), MB (megabytes), GB (gigabytes), and TB (terabytes)
• One kilobyte is 1,024 bytes
• One megabyte is 1,048,576 bytes
• One gigabyte = 1,073,741,824 bytes
• One terabyte = 1,099, 511,627,776 bytes

Computer Architecture

• Von Neumann computer architecture includes instructions and data that is stored in the same memory using 1 data bus.
• The Harvard computer architecture separates data and instructions into separate memories using 2 data buses and is employed in most microcontrollers.

Von Neumann architecture

• The processor cannot fetch an instruction and access data simultaneously
• All segments are loaded into the main memory
• Memory bandwidth is shared
• Inexpensive and straightforward

Harvard architecture

• There are dual sets of data buses
• Simultaneous fetch of instructions and data is possible
• Segments of Z and RW, are copied into the data memory
• Enhanced memory bandwidth = high/ speed performance
• More efficient

Harvard ARM Microcontrollers

• Instruction and data memory are small enough to fit within the same address space and share the same memory address bus
• 4KB for instructional memory with Flash Memory and 256 KB for data memory with SRAM
• Starting addresses of microcontrollers using Harvard Architecture: flash has 0x0800_0000 and SRAM has 0x2000_0000

Program loading in memory

• When the processor loads a program, all initialised, uninitialised global, and local variables are kept in data memory
• When the processor boots, it loads the first instruction of the program from the instruction memory, and the program starts to run.
• At runtime, there are 4 segments: Initialized data, uninitialized or zero-initialized data aka block starting symbol (BSS), heap, and stack.
• The size and location of initialised and uninitialised data remain unchanged. Heap and stack changes dynamically.
• The Stack is mandatory and follows the first-in-last-out (FILO) protocol
• The Heap is used only if dynamic assignemnt via malloc is used

Cortex M Memory Map

• No overlap between SRAM, Flash Memory and Peripherals allowing for a convenient peripheral interface
• Peripheral devices are a computer component and are separate from the computer's core architecture.

Peripheral Memory

• A set of registers that include: data registers for data exchange between the peripheral and the processor, control registers that configure or control the peripheral, and status registers that indicate the operation state of the peripheral.
• Peripheral Memory may also contain a small memory
• Memory access instructions are predefined for each peripheral.

Registers

• Also known as Processor Registers
• This is the fastest data storage using digital values
• General sizes are 16 bit, 32 bit and 64 bit
• Cortez -M registers are 32 bits
• The Processor reads or writes all bits of a register together
• There are 2 register types: General purpose (GP), used to store any instruction (temporary storage), and special purpose (SP), which has predetermined usage and has restricted access
• Registers are made of a series of flip-flops that operate in parallel to store binary bits
• CPUs are limited to only 32 registers
• Improves thermal behaviour due to highest temperature
• The rules to follow in assembly for register allocation are: Inspect the live range of a variable and the registers; most frequently used variables should be mapped to registers, the rest to data memory

Types Of Registers

• Stack pointer (SP), which is R13, holds the memory address of the top the stack.
• Memory add of inst after subroutine occurs in the link register (LR) which is R14
• The next instruction mem add occurs at the program counter PC
• Program status register (xPSR) - is for status bit flags, containing info if the are negative, zero, carry, and overflow errors.
• Base priority mask register (BASEPRI) - this is the priority threshold; lower values are a higher priority.
• The control register (CONTROL) controls the choice of MSP or PSP
• Priority mask register (PRIMASK) disables all interrupts, excluding hard and non-maskable interrupts (NMI)
• Fault mask register (FAUL TMASK) can disable all interrupts, excluding non-maskable interrupts (NMI).
• Cortex M general registers are R0-R12 for general purposes
• Link register (LR) and Program counter are R14 and R15, respectively.

Program Counter

• Plays a major role for Program execution
• Holds the memory address of the next instruction
• Processor fetches instructions consecutively from the instruction memory and automatically increments the program counter to where the next instruction is to be fetched

Program Execution Steps

• The program counter (PC) is a register that holds the memory address of the next instruction is to be fetched from the memory
• Steps 1: fetch instructions at the PC address
• Step 2: decode the instruction
• Step 3: execute the instruction in the CPU
• Pipelining allows hardware resources to be fully utilized
• One 32-bit instruction or two 16-bit instructions can be fetched at a time

Size specifications

• Each memory address in byte based addressing is equivalent to only 1 byte.
• The program counter is only incremented by one when addressing this way and the Microchip PIC series are examples.
• Each memory address in word based addressing is the same an 2 bytes and also a single work, and the memory program counter is incremented by 2.
• In DWord based memory addressing each address adds 4 bytes, and can be expressed as 32 bits or 1 DWord. The program counter is increased by 4 using Cortex M or Intel x86.
• A Qword is the size equivalent to 8 bytes with 64 bits, and each increment of the program counter is increased by 4, and has a fetch size of 8, and is seen on Intel x86 64 or ARM 64 bit processors.

Incrementing on ARM Cortex M

• The program counter always increments by 4.
• If bit [15-11] = 11101, 11110, or 11111, then, it is the first half-word of a 32-bit instruction.
• Otherwise, it is a 16-bit instruction.