Semiconductor Memory Quiz

Static RAM uses on/off switches to store data, needs no refreshing, and has a complex structure compared to DRAM.

Dynamic RAM uses capacitors to store bits, requires refreshing, and has a simpler structure.

Electronic circuits needed to constantly update the data in DRAM.

Read-Only Memory (ROM) has permanent storage, and its data is built into the chip during manufacturing.

SRAM is faster and uses less power than DRAM, but SRAM is more expensive and larger per bit.

DRAM memory sizes are in the gigabytes, while SRAM sizes are in the megabytes.

ROM holds permanent, non-changeable data essential for microprogramming, library subroutines, and system programs (e.g., BIOS).

ROM data is directly wired into the chip during its manufacturing process, permanently fixing the data.

Basic building block of semiconductor memory, having two stable states representing binary 1 and 0.

Memory chips readable and writable by the processor, temporary storage for data.

A type of Random Access Memory where memory states are held continuously (no refreshing needed) by using flip-flops.

A type of Random Access Memory where memory states are held as charges in capacitors and need to be refreshed periodically to prevent charge leakage.

Memory that loses stored data when power is removed.

Memory that retains stored data even when power is off.

Memory that can both store and retrieve data.

Memory that can only be read and not rewritten.

Process of reading or writing data in a memory cell.

The gradual loss of charge in capacitors used in DRAM memory, requiring periodic refresh cycles.

Categories of Read-Only Memory chips, programmed during manufacture or through special processes.

A type of ROM that can be programmed only once after manufacture.

ROM that can be erased using ultraviolet light and reprogrammed.

ROM that can be erased and reprogrammed electrically.

Non-volatile memory that can be erased and reprogrammed electrically in blocks.

The process of periodically reading and writing back data in Dynamic RAM to prevent data loss.

A memory technique that groups DRAM chips into banks to handle multiple read/write requests simultaneously.

Faults in memory leading to incorrect data, categorized as hard (permanent) and soft (temporary).

A method for detecting and correcting errors in data transmission using parity bits.

A process of identifying and fixing data errors during transmission.

Extra bit added to data to ensure an even number of 1s.

Checking for mistakes in transmitted data.

Improved DRAM design incorporating SRAM for faster data access.

A larger component within a memory system that uses SRAM technology. It acts as a temporary storage area for frequently accessed data, speeding up data retrieval.

Comparing the speed and efficiency of various DRAM types, including Cache DRAM and SDRAM, based on factors like access time, data transfer rates, and power consumption.

A type of DRAM that synchronizes data access with an external clock signal. This allows the CPU to predict data availability, leading to faster processing.

A feature in SDRAM that allows data to be transferred in blocks, significantly improving data transfer rates.

A type of SDRAM that doubles the data transfer rate by sending data twice per clock cycle.

Rambus is a type of memory technology that was adopted by Intel for its Pentium and Itanium processors. It is a main competitor to SDRAM and utilizes a vertical package with all pins on one side. It allows data exchange over 28 wires and can address up to 320 RDRAM chips.

Double-data-rate SDRAM (DDR SDRAM) is an advancement upon standard SDRAM that can send data twice per clock cycle, utilizing both the rising and falling edges of the clock signal.

Cache DRAM integrates a small SRAM cache onto a generic DRAM chip to act as a true cache, improving performance for random access and serial access of data blocks. It can prefetch data into the SRAM buffer for faster subsequent accesses.

An asynchronous block protocol allows the transmission of data in blocks without needing a fixed clock signal, allowing for more flexible data transfer.

DDR SDRAM can send data twice per clock cycle, effectively doubling the data transfer rate compared to traditional SDRAM.