S-R Latch Fundamentals

Latches

• A latch serves as temporary storage with two stable states, functioning as a basic memory form.
• The S-R (Set-Reset) latch is fundamental, built using NOR or NAND gates.
• With NOR gates, it needs active-HIGH inputs.
• With NAND gates, it operates with active-LOW inputs.
• An active-HIGH S-R latch remains stable (latched) when both inputs are LOW.
• Initially, the latch is in a RESET state (Q = 0) with inactive inputs (0).
• To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while R stays LOW.
• To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while S stays LOW.
• The active-LOW S-R latch maintains stability when both inputs are HIGH.
• With the latch initially RESET (Q = 0) and inputs inactive (1), a momentary LOW signal on S inputs sets the latch (Q = 1) while R remains HIGH.
• Applying a momentary LOW signal to the R input resets the latch (Q = 0), with S staying HIGH.
• Avoid applying an active set and reset at the same time because it is invalid.
• The active-LOW S-R latch is available as the 74LS279A IC.
• It features four internal latches, with two having two S inputs.
• To SET any of the latches, the S line is pulsed low.
• It is available in several packages.
• The latch is used for switch debounce circuits.
• A gated latch is a basic latch variation.
• Gated latches include an enable (EN) input, which must be HIGH for the latch to respond to S and R inputs.
• S and R are active only when EN is HIGH
• The D latch is a variation of the S-R latch, combining the S and R inputs into a single D input.
• Q follows D when the Enable is active.
• The D latch's operation is summarized in a truth table: when EN is LOW, the output doesn't change; it remains latched.

Flip-Flops

• A flip-flop differs from a latch in how it changes states.
• A flip-flop is a clocked device where the clock edge determines when a new bit gets entered.
• The active edge is either positive or negative.
• The truth table for a positive-edge triggered D flip-flop is sensitive to its D input only on the rising edge of the clock; otherwise, it is latched.
• The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow.
• The J-K flip-flop is more versatile than the D flip flop.
• The clock input has two inputs, labeled J and K.
• When both J and K = 1, the output changes states or toggles on the active clock edge,.
• D flip-flops lack a toggle mode found in J-K flip-flops, but toggle mode can be achieved by wiring Q back to D.
• If Q is LOW and Q is HIGH, the flip-flop toggles on the next clock edge.
• The flip-flop only changes on the active edge, and the output changes only once per clock pulse.
• Synchronous inputs transfer on the clock's triggering edge (e.g., D or J-K inputs).
• Flip-flops often have asynchronous inputs, like preset (PRE) and clear (CLR), which affect output independently of the clock.
• PRE and CLR inputs are active LOW.

Flip-Flop Characteristics

• Propagation delay time specifies for rising and falling outputs and measures from the 50% level of the clock to the 50% level of the output transition.
• The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.
• Faster logic is available for specialized applications.
• Another propagation delay time specification is the time required for an asynchronous input to cause an output change, measured from the 50% levels.
• The 74AHC family has specified delay times under 5 ns.
• Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop.
• Setup time is the minimum time for the data to be present before the clock signal.
• Hold time is the minimum time for the data to remain after the clock signal.

Race Condition

• A race condition occurs when two values should change simultaneously, but one changes faster.
• If both S-R flip-flop inputs change from logic 1 to logic 0 at the same time, the outputs become unpredictable, creating a race condition.
• Logic circuit design avoids this by preventing simultaneous application of 1's to both inputs.

Flip-Flop Applications and Specifications

• Specifications include maximum clock frequency, minimum pulse widths for various inputs, and power dissipation.
• Power dissipation is the product of supply voltage and average current.
• The speed-power product is a useful comparison between logic families, using average propagation delay and power dissipation; its unit is energy.
• Principal flip-flop applications include temporary data storage, frequency dividers, and counters.
• Data storage applications connect flip-flops to parallel data lines and clock them together, storing data until the next clock pulse.
• For frequency division, use a flip-flop in toggle mode or chain toggle flip-flops to divide by two.
• A side benefit of frequency division is that the output has an exact 50% duty cycle.

One-Shots

• A one-shot or monostable multivibrator has one stable state.
• When triggered, it enters an unstable state for a set time, then returns to its stable state.
• The length of time in the unstable state (tw) relies on an external RC circuit.
• Nonretriggerable one-shots ignore triggers during the unstable state.
• Retriggerable one-shots respond to triggers, even during the unstable state, extending the state by an amount equal to the pulse width.
• A retriggerable one-shot is a power failure detection circuit.
• Triggers from the AC power source retrigger the one-shot.
• A power failure stops triggering, and an alarm is initiated.
• The 555 timer can be set up in different ways, including as a one-shot.
• The pulse width is determined by R₁C₁ and is approximately tw = 1.1R1C1.
• The trigger is a negative-going pulse.
• The components can be used to read the frequency from the chart.
• The components can be picked for a desired frequency.
• The 555 can be configured as a basic astable multivibrator.
• In this circuit C₁ charges through R₁and R₂ and discharges through only R₂.
• The output frequency is
• = 1.44/((R₁+2R₂)C₁)
• The frequency and duty cycle are set by these components.

Definitions

• Latch: A bistable digital circuit for storing a bit.
• Bistable: Having two stable states; latches and flip-flops are bistable multivibrators.
• Clock: A triggering input of a flip-flop.
• D flip-flop: A bistable multivibrator where the output assumes the D input state at the clock pulse's triggering edge.
• J-K flip-flop: Operates in SET, RESET, no-change, and toggle modes.
• Propagation delay time: The interval required after an input signal has been applied for the resulting output signal to change.
• Set-up time: The time for input levels to be steady on a digital circuit.
• Hold time: The time for input levels to remain steady after the triggering edge for reliable device activation.
• Timer: A circuit functioning as a one-shot or oscillator.