Processor Design and Implementation

Design Overview

• Includes instruction memory and data memory
• Program Counter (PC) supplies the address to instruction memory
• Instruction memory outputs an instruction back to register file
• Register file outputs data to Data memory based on Reg# read from the Instruction memory
• Data memory provides/receives data to/from the register file and back to itself

Generic Implementation of Processor Design

• Program counter (PC) supplies instruction address
• Get the instruction from memory- Read instructions
• Use the instruction to decide exactly what to do
• ALU executes instructions, then stores the result

Division into Data Path and Control

• Data path contains the operands in the working area, and the results are stored here
• Controller instructs ALU about action to be performed and takes in control signals

Basic LEGV8 Implementation

• Arithmetic and logic instructions: ADD, SUB, AND, ORR
• Memory reference instructions: LDUR, STUR
• Control flow instructions: CBZ, B

Logic Design Conventions

• Two types of functional units: combinational element and sequential/state element
• Combinational elements operate on data values, output a function of the current input, and has no memory
• Sequential/state elements contain state, output a function of the current and previous inputs, and remember the previous state

Combinational Circuit Examples

• Gates: and, or, nand, nor, xor, invertor
• Multiplexer
• Decoder
• Adder, subtractor, comparator
• ALU
• Array multipliers

Sequential Circuit Examples

• Flip-flops
• Counters
• Registers
• Register files
• Memories

Clocking Methodology

• A single electronic pulse of CPU
• During each clock cycle, a computer can perform a basic operation of the instruction cycle like fetch or decode
• Asserted signals are logically high or true
• Deasserted signals are logically low or false

Computer Clock

• Clocks run at a constant rate and determine when events take place in hardware
• Clock cycle time is the amount of time for one clock period to elapse
• The frequency of a processor is also known as processor clock speed or clock rate
• Clock rate is the inverse of clock cycle time
• If a computer has a clock cycle time of 5 ns, the clock rate is 200 MHZ

How Clock Cycle Time is Decided

• The figure shows the two state elements surrounding a block of combinational logic, all signals must propagate from state element 1, through the combinational logic, and to state element 2 in the time of one clock cycle
• The time necessary for the signals to reach state element 2 defines the length of the clock cycle

Edge Triggered Clocking

• Any values stored in a sequential logic element are updated only on a clock edge, which is a quick transition from low to high or vice versa
• The inputs are values that were written in a previous clock cycle, while the outputs are values that can be used in a following clock cycle

Data Path Elements

• Instruction Memory: Stores the instruction
• Program Counter: Stores the address of the next instruction
• Adder: Used to increment the PC
• Registers: Store data and addresses
• ALU: Performs arithmetic and logical operations
• Data Memory: Stores data
• Sign Extension Unit: Extends the sign bit of a number to a larger size

R-FORMAT Instruction Fields

• Instruction fields: opcode (operation code), Rm (the second register source operand), shamt (shift amount, 00000 for now), Rn (first register source operand), and Rd (register destination)
• ADD X9, X20, X21 is an example

D-FORMAT

• D-Format is used for data transfer instructions and has has opcode, address, op2, Rn, and Rt fields
• LDUR X9,[X10,#32] loads a register
• STUR X9,[X10,32] stores a register
• Load/store instructions
• Rn: base register
• Address: constant offset from contents of base register (+/- 32 doublewords)
• Rt: destination (load) or source (store) register number

CB-TYPE

• OpCode: 8 Bits
• Offset: 19 bits
• Register: 5 bits

ALU control lines and functions

• 0000: AND
• 0001: OR
• 0010: add
• 0110: subtract
• 0111: pass input b
• 1100: NOR
• Depending on the instruction class, ALU decides which operation should be done

How ALU Control Bits Are Set Depending on Opcode and ALUop

• LDUR (00 ALUop): Adding for load register
• STUR (00 ALUop): Adding for store register
• CBZ (01 ALUop): Passing input B for compare and branching on zero
• R-type (10 ALUop): Operations such as ADD, SUB, AND, ORR

Final Steps for R-Format Instruction

• Fetching is done and the PC is incremented
• Two registers (X2 and X3) are read from register file and the main control unit computes the settings of the control lines at the same time
• The ALU operates on data that is read from the register file, then generating the ALU function using portions of opcode
• The result from ALU is written into the destination register (X1) in the register file

Final Steps for LDUR

• A instruction is fetched from the instruction memory and the PC is incremented
• A register (X2) value is read from the register file
• ALU computes the sum of value read from the register file and the sign-extended 9 bits of the instruction (offset)
• The sum from the ALU is used as address for the data memory
• Data from the memory unit is written into the register file (X1)

Control signals for STUR

• Reg21/oc: set to 1
• ALUsr/c: Set to 1
• Mem to reg: Set to X
• Reg write: Set to 0
• Mem read: Set to 0
• Mem write: Set to 1
• Branch: Set to 0
• ALUo p1: Set to 0
• ALUo p0: Set to 0