Parity Bit and Parity Checking Quiz

Parity Bit

• Utilized for detecting single-bit errors in data transmission.
• Two types of parity checking: even parity and odd parity.
• Parity bit set automatically by USART hardware for error detection.
• Parity is checked by the receiver to verify data integrity.

Odd Parity

• The parity bit is configured to ensure the total number of 1s, including the parity bit, remains odd.
• Example:
  • For data 1100 1100, which has 4 ones, the parity bit is set to 1 (total becomes 5).
  • For data 1000 1100, which has 3 ones, the parity bit is set to 0 (total remains 3).

Even Parity

• The parity bit is configured to ensure the total number of 1s, including the parity bit, stays even.
• Example:
  • For data 1100 1100, with 4 ones, the parity bit is set to 0 (total remains 4).
  • For data 1000 1100, with 3 ones, the parity bit is set to 1 (total becomes 4).

USART in the AT90

• Supports full duplex operation with independent transmit and receive registers.
• Capable of asynchronous or synchronous operation.
• Configurable master or slave clocked synchronous operation.
• High-resolution baud rate generator available.
• Supports serial frames with 5 to 9 data bits and 1 or 2 stop bits.
• Odd or even parity generation and checking performed by hardware.
• Features data overrun detection, framing error detection, and noise filtering.
• Includes detection for false start bits and a digital low pass filter.
• Three separate interrupts for TX complete, TX data register empty, and RX complete.
• Incorporates a multi-processor communication mode and double-speed asynchronous communication mode.

AT90 USART Block Diagram Components

• Clock Generation: Manages the timing for data transmission.
• Transmitter: Sends data; the UDR (USART Data Register) facilitates data write.
• Receiver: Collects incoming bits via a receive shift register, with data moved to UDR when a frame is fully received.
• Queue mechanism in UDR allows for FIFO (first in, first out) data processing.

USART Registers

• Only one USART available, named USART1.
• Key registers include:
  • Control and Status Register (UCSR): Manages the USART operation settings.
  • USART I/O Data Register (UDR1): Facilitates data transmission and receipt.

USART Control and Status Register A

• Contains flags such as RXC (Receive Complete), TXC (Transmit Complete), UDRE (Data Register Empty), FE (Frame Error), DOR (Data Overrun), and UPE (Underrun Parity Error).
• RXC indicates unread data in the receive buffer.

USART Control and Status Register B

• Manages interrupt settings and enabling for the receiver and transmitter.
• RXCIE enables an interrupt when new data is received.
• TXCIE enables an interrupt when the transmitter is ready to send more data.
• RXEN turns on the USART receiver, overriding normal port operation.
• TXEN turns on the USART transmitter for outgoing data.
• UCSZ2, in conjunction with UCSZ1:0, determines the number of data bits in a transmitted or received frame.