Operating System Memory Management
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What is a primary purpose of memory management in an operating system?

  • To improve disk access speed
  • To maximize CPU processing power
  • To ensure a process can only access its specific address space (correct)
  • To decrease the number of CPU registers
  • Which system component directly interfaces with memory and registers?

  • Disk management unit
  • CPU (correct)
  • Cache memory
  • Input/Output controllers
  • In memory architecture, what is the role of cache memory?

  • To act as a replacement for main memory
  • To reduce the number of clock cycles needed for access (correct)
  • To store unused programs until needed
  • To directly load data from the disk into the CPU
  • What is one of the challenges posed by the use of main memory?

    <p>Accessing it can take many cycles, potentially causing a stall</p> Signup and view all the answers

    What does the term 'contiguous memory allocation' refer to?

    <p>Allocating a single block of memory for a process without fragmentation</p> Signup and view all the answers

    What is the calculation for internal fragmentation when a process size is 72,766 bytes and uses a page size of 2,048 bytes?

    <p>962 bytes</p> Signup and view all the answers

    Why are smaller frame sizes generally considered desirable?

    <p>They lead to less internal fragmentation.</p> Signup and view all the answers

    What does the page-table length register (PTLR) indicate?

    <p>The size of the page table.</p> Signup and view all the answers

    What is the role of the translation lookaside buffer (TLB) in a paging system?

    <p>To speed up the retrieval of page table entries.</p> Signup and view all the answers

    What is the worst-case fragmentation scenario in a paging system?

    <p>One frame minus one byte wasted.</p> Signup and view all the answers

    What is the primary function of the Memory-Management Unit (MMU)?

    <p>To map virtual addresses to physical addresses at runtime</p> Signup and view all the answers

    How does the logical address differ from the physical address during execution-time binding?

    <p>Logical addresses are generated by the CPU, whereas physical addresses are viewed by the memory unit.</p> Signup and view all the answers

    What happens when a user process generates an address?

    <p>The logical address is modified by the relocation register before use.</p> Signup and view all the answers

    In which address-binding scheme are logical and physical addresses equivalent?

    <p>Compile-time binding</p> Signup and view all the answers

    Which statement is true about logical address space?

    <p>It refers to addresses that are visible to user processes.</p> Signup and view all the answers

    What is the role of the relocation register in memory management?

    <p>To add a base address to user-generated logical addresses before accessing memory</p> Signup and view all the answers

    Which of the following best describes the physical address space?

    <p>The set of all physical addresses that can be utilized by a program</p> Signup and view all the answers

    Which statement best describes logical addresses?

    <p>They represent an abstract view of memory for user processes.</p> Signup and view all the answers

    What is the purpose of the relocation register in a computer system?

    <p>To add a constant value to user-generated addresses before accessing memory</p> Signup and view all the answers

    What advantage does dynamic loading provide in memory management?

    <p>It optimizes memory usage by only loading routines when needed.</p> Signup and view all the answers

    Which characteristic defines dynamic linking as opposed to static linking?

    <p>Dynamic linking allows libraries to be linked during execution.</p> Signup and view all the answers

    In contiguous allocation, what is the role of the limit register?

    <p>To restrict logical addresses to a set range for safety.</p> Signup and view all the answers

    How does the operating system maintain efficient memory allocation in a variable partition system?

    <p>By tracking both allocated and free partitions carefully.</p> Signup and view all the answers

    What is a characteristic of a hole in the context of variable partition allocation?

    <p>It is a block of available memory varying in size throughout memory.</p> Signup and view all the answers

    What occurs when a process exits in a variable-partition system?

    <p>The freed partition may be combined with adjacent free partitions.</p> Signup and view all the answers

    Which of the following statements about dynamic storage-allocation problem is true?

    <p>It addresses how to allocate a size $n$ from free holes efficiently.</p> Signup and view all the answers

    What role does the stub play in the dynamic linking process?

    <p>It locates the appropriate memory-resident library routine during execution.</p> Signup and view all the answers

    Which of the following is true about memory management through contiguous allocation?

    <p>User processes require contiguous sections of memory for efficient execution.</p> Signup and view all the answers

    What is the purpose of the TLB in the context of virtual memory management?

    <p>To hold translation table entries for fast hardware lookups.</p> Signup and view all the answers

    Which statement accurately describes the functionality of the hash tables in the inverted page table architecture?

    <p>They represent contiguous areas of mapped virtual memory.</p> Signup and view all the answers

    What happens when a virtual address reference results in a TLB miss?

    <p>The kernel is interrupted to search the hash table.</p> Signup and view all the answers

    What structural components make up the inverted page table architecture in the Oracle SPARC Solaris?

    <p>Two hash tables: one for the kernel and one for user processes.</p> Signup and view all the answers

    What role does the translation storage buffer (TSB) play in the memory address translation process?

    <p>It is a cache that includes entries for recently accessed pages.</p> Signup and view all the answers

    What does an entry in the hash table for virtual memory translate to?

    <p>A base address and span indicating the number of pages.</p> Signup and view all the answers

    What is the main goal of the architecture used in modern, tightly integrated hardware operating systems?

    <p>Achieving efficiency with low overhead.</p> Signup and view all the answers

    In the case of a TLB hit, what is the result of the lookup?

    <p>The CPU retrieves the physical memory address directly.</p> Signup and view all the answers

    What is a condition that typically triggers the process of swapping in an operating system?

    <p>When free memory is extremely low.</p> Signup and view all the answers

    How can context switch time be affected by swapping?

    <p>It can become very high if processes are not in memory.</p> Signup and view all the answers

    Which of the following methods do mobile operating systems typically use to manage low memory instead of swapping?

    <p>Voluntary memory relinquishment by apps.</p> Signup and view all the answers

    What can happen if a process is swapped out while pending I/O operations are occurring?

    <p>I/O would trigger on the wrong process.</p> Signup and view all the answers

    What does Intel's Page Address Extension (PAE) allow 32-bit applications to do?

    <p>Access more than 4GB of memory space.</p> Signup and view all the answers

    What is a common memory management method supported by both iOS and Android?

    <p>Paging.</p> Signup and view all the answers

    In the Intel IA-32 architecture, how many segments can a process have?

    <p>Up to 16K segments.</p> Signup and view all the answers

    Which component primarily handles the translation of logical addresses to physical addresses in the IA-32 architecture?

    <p>Memory Management Unit (MMU).</p> Signup and view all the answers

    What is a characteristic of modern operating systems regarding standard swapping?

    <p>Standard swapping is rarely used, and modified versions are common.</p> Signup and view all the answers

    In the context of context switch time, what is one method to potentially reduce the swapping component time?

    <p>Reduce the size of memory that is swapped.</p> Signup and view all the answers

    What is the practical limit of addressing implemented in contemporary Intel x86-64 systems?

    <p>48 bits for virtual addresses.</p> Signup and view all the answers

    What major advantage does a two-level translation lookaside buffer (TLB) provide in the ARM architecture?

    <p>Faster address translation.</p> Signup and view all the answers

    What is the primary storage problem for mobile systems that limits their use of swapping?

    <p>Limited write cycles in flash memory.</p> Signup and view all the answers

    Study Notes

    Main Memory

    • Main memory supports both operating system and user processes
    • Memory is a limited resource, so efficient allocation is crucial
    • Contiguous allocation is one early approach
    • Memory is divided into partitions: resident OS (low memory, interrupt vector), user processes (high memory)
    • Each process is in its own contiguous section

    Protection

    • Processes need protection from each other and the OS
    • Base and limit registers define a process' logical address space
    • The CPU checks every memory access to ensure it's within the base/limit range
    • Instructions to load those registers are usually privileged

    Address Binding

    • Programs can be bound to memory addresses at different stages: compile time, load time, or execution time
      • Compile time: Addresses known at compile time.
      • Load time: Addresses known at load time.
      • Execution time: Addresses are determined at run time.
    • Binding methods map symbolic addresses to absolute addresses

    Multistep Processing

    • Source program/code is first compiled, or assembled
    • Then object modules are written
    • Object modules are linked together
    • The resulting executable load module is loaded by the loader

    Logical vs Physical Address Space

    • Logical (virtual) address is generated by the CPU
    • Physical address is used by the memory unit
    • In compile-time and load-time, the logical and physical addresses are the same.
    • They differ in execution time.
    • Logical address space is the set of all logical addresses generated by a program.
    • Physical address space is the set of all physical addresses generated by a program

    Memory-Management Unit (MMU)

    • Hardware that maps logical to physical addresses at runtime
    • This is a generalization of the base-register scheme (the relocation register)
    • Used to protect user processes from each other

    Dynamic Loading

    • The entire program isn't loaded into memory at once
    • Routines loaded only when needed
    • Improves memory usage

    Dynamic Linking

    • Linking of libraries is postponed until execution time
    • Uses stubs to locate routines
    • Implementation of shared libraries

    Contiguous Allocation (cont.)

    • Relocation registers needed to protect user processes from each other and from changing operating system code/data
    • Base register contains smallest physical address
    • Limit register contains the range of logical addresses
    • Allows for dynamic mapping of logical to physical addresses

    Variable Partition

    • Multiple partitions of variable sizes
    • Holds OS and user programs
    • Free memory areas (holes)
    • The OS maintains a record of free blocks of memory

    Dynamic Storage Allocation

    • Methods (First-fit, best-fit, worst-fit) to satisfy requests for memory allocation sized 'n' bytes
    • First-fit: fastest, but doesn't necessarily minimize leftover space
    • Best-fit: minimizes leftover space, but slowest.
    • Worst-fit: allocates the largest hole, producing the largest leftover hole.

    Fragmentation

    • External fragmentation: Memory space exists, but it is not contiguous.
    • Internal fragmentation: Assigned memory is larger than needed.
    • Compaction: Attempts to reduce external fragmentation by moving memory blocks

    Paging

    • Physical address space of a process can be noncontiguous
    • Improves external fragmentation
    • Divides physical memory into fixed-sized blocks
    • Divides logical memory into blocks of same size

    Address Translation

    • CPU-generated address divided into page number and page offset
    • Page number is used as an index to a page table
    • Page offset is combined with the base address to define the physical memory address

    Paging Hardware

    • Logical to physical address mapping
    • Page table hardware

    Paging Model

    • Logical memory and physical memory are divided into pages
    • Logical page number corresponds to a specific physical frame

    Paging Example

    • Showcases logical and physical address mapping with page table lookup

    Paging - Calculating internal fragmentation

    • Calculates internal memory wasted due to paging.

    Free Frames

    • Free frames stored in a free-frame list
    • Allocation occurs using the free-frame list
    • Free frames are added back to free-frame list upon deallocation

    Implementation of Page Table

    • Page table kept in main memory
    • Page-table base register (PTBR) and length register (PTLR)

    Translation Look-Aside Buffer (TLB)

    • Special fast-lookup hardware cache
    • Maps logical to physical addresses

    Hardware

    • Associative memory is used for parallel search
    • Address translation uses page number and the associative register
    • Page number in register, frame number returned
    • Otherwise, search in memory page table

    Paging Hardware with TLB

    • A diagram showing the steps involved in the TLB lookup

    Effective Access Time

    • Calculating effective access time considering hit ratio.

    Memory Protection

    • Mechanisms used for memory protection
    • Valid-invalid bit in the page table

    Valid or Invalid Bit

    • Valid: indicates the page is in the process' logical address space
    • Invalid: indicates the page isn't in process' logical address space

    Shared Pages

    • One copy of read-only code shared amongst multiple processes
    • Improves efficiency and reduces memory usage
    • Multiple processes can access the shared memory

    Shared Pages Example

    • Example of how page tables for shared code/data are organized

    Structure of the Page Table

    • Memory structures for paging
    • Dividing page tables into smaller units
    • Hierarchical paging, hashed page tables, inverted page tables

    Two-Level Paging

    • Dividing a 32-bit logical address into two page numbers and an offset
    • Mapping to page tables

    64-bit Logical Address Space

    • When 64-bit logical addresses are involved

    Three-Level Paging

    • A variant of multilevel page table structure
    • Addresses are broken down into three page numbers

    Hashed Page Tables

    • Hashing virtual page numbers to virtual page entries in a hash table.

    Inverted Page Table

    • Only one entry per physical page instead of per virtual page for a process.

    Oracle SPARC Solaris

    • Example of a modern 64-bit operating system

    Swapping

    • Moving processes between memory and a backing store.
    • Total physical memory space needed for processes may exceed physical memory.
    • Methods to accommodate processes

    Swapping (cont.)

    • Swapping issues (address binding).
    • Swapping variants found in operating systems like UNIX, Linux, and Windows

    Context Switch Time

    • Time for switching a process to another.
    • Including the swap in/out times if necessary
    • Increased context switching time

    Context Switch time and Swapping (cont.)

    • Constraints on swapping
    • Considerations for pending I/O
    • Use of double buffering

    Swapping on Mobile Systems

    • Differences in memory management to accommodate flash-based memory, limited cycles, low throughput

    Swapping with Paging

    • Swapping processes that require paging.

    Example: The Intel 32 and 64-bit Architectures

    • Dominant processors used in modern computing.
    • Typical architectures used for 32-bit and 64-bit systems

    Example: The Intel IA-32 Architecture

    • Supports both segmentation and segmentation with paging.
    • Details about how segments are handled in the architecture

    Example: The Intel IA-32 Architecture (cont.)

    • CPU generating logical addresses.

    Logical To Physical Address Translation

    • The transformation steps from a logical address to a physical address in IA-32 architecture.

    Intel IA-32 Segmentation

    • The segmentation unit in a 32-bit Intel processor.

    Intel IA-32 Paging Architecture

    • Page directory, page table layout.

    Intel IA-32 Page Address Extensions (PAE)

    • Increasing address space.

    Intel x86-64

    • Typical architecture for the 64-bit systems.

    Example: ARM Architecture

    • Describes the mobile platform chip architecture.
    • Methods for paging, TLBs, and memory allocations.

    End of Chapter 9

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