Operating system concepts
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Questions and Answers

What is the term for a situation where the data required for an operation is unavailable?

  • Stock
  • Data hazard (correct)
  • Deadlock
  • Structural hazard

How are fetch and execution cycles interleaved in a processor?

  • Special unit (correct)
  • Modification in processor architecture
  • Control unit
  • Clock

Which page replacement algorithm replaces the block that has not been referenced for the longest time?

  • Both LRU and ORF
  • ORF
  • LRU (correct)
  • Direct

Which page replacement algorithm removes the most recently used page first?

<p>MRU (A)</p> Signup and view all the answers

In the LRU algorithm, when a block is referenced (a hit occurs), how is its counter and the counters of other blocks updated?

<p>The referenced block's counter is set to '0,' and the counters of the previous blocks are incremented by one; others remain the same. (C)</p> Signup and view all the answers

A CPU is fetching data from memory. Which register is primarily responsible for holding the memory address being accessed?

<p>Memory Address Register (MAR) (D)</p> Signup and view all the answers

In the context of CPU operation, what is the significance of a 'flag bit' within the status register?

<p>It indicates specific conditions that arise during program execution, such as overflow or zero results. (D)</p> Signup and view all the answers

Which of the following registers directly facilitates the transfer of data between the CPU and secondary storage devices like hard drives?

<p>Memory Data Register (MDR) (A)</p> Signup and view all the answers

Among the options provided, which is least likely to be categorized as a peripheral device connected to a computer system?

<p>Central Processing Unit (CPU) (D)</p> Signup and view all the answers

Which data transfer technique allows devices to directly access system memory without involving the CPU, thus improving data transfer rates?

<p>DMA (Direct Memory Access) (A)</p> Signup and view all the answers

What distinguishes John Von Neumann's contribution to computer architecture from earlier designs?

<p>He introduced the concept of stored-program architecture. (C)</p> Signup and view all the answers

Which of the following components is least directly involved in the immediate processing of data within a computer system?

<p>Keyboard (C)</p> Signup and view all the answers

A program exhibits slow performance due to frequent data access. Which memory type upgrade would most effectively address this issue?

<p>Adding Cache memory (A)</p> Signup and view all the answers

What distinguishes the Arithmetic Logic Unit (ALU) from other computer components?

<p>It performs mathematical and logical operations. (A)</p> Signup and view all the answers

Why might a programmer choose to represent data in hexadecimal format rather than decimal format?

<p>Hexadecimal directly represents binary data more compactly. (B)</p> Signup and view all the answers

How does cache memory improve overall system performance?

<p>By temporarily storing frequently accessed data for faster retrieval. (C)</p> Signup and view all the answers

Why is the address bus unidirectional?

<p>To ensure only the CPU can specify the memory location. (D)</p> Signup and view all the answers

A system requires a component to retain a single bit of information. Which logic circuit is most appropriate for this purpose?

<p>Flip-Flop (D)</p> Signup and view all the answers

In memory-mapped I/O, how do I/O devices interact with the system's memory?

<p>I/O devices and memory share the same address space. (A)</p> Signup and view all the answers

What is the most common BUS structure used for connecting I/O devices to a computer system?

<p>Single BUS structure, where all devices share a single communication pathway. (B)</p> Signup and view all the answers

How does a system typically signal a read or write operation involving I/O devices on a shared BUS?

<p>By sending a special control signal along the BUS, distinct from address and data lines, to initiate the process. (D)</p> Signup and view all the answers

Which I/O access method requires the processor to continuously check the status flags of I/O devices?

<p>Program-controlled I/O (C)</p> Signup and view all the answers

Which mechanism allows an I/O device to alert the processor when it is ready for data transfer?

<p>Interrupts (A)</p> Signup and view all the answers

Which I/O transfer method typically offers the highest data transfer speeds?

<p>DMA (C)</p> Signup and view all the answers

In the IEEE 754 32-bit floating-point standard, how many bits are allocated for the mantissa (also known as significand) of the fractional part?

<p>23 (D)</p> Signup and view all the answers

What term describes the component of a floating-point number that consists of the sign followed by the string of significant digits?

<p>Mantissa (D)</p> Signup and view all the answers

Which component is NOT typically involved in the design of a basic multiplier?

<p>Flip flops (A)</p> Signup and view all the answers

In a typical multiplication operation within a computer's arithmetic logic unit (ALU), where is the multiplier primarily stored during the calculation?

<p>Shift register (A)</p> Signup and view all the answers

Which unit is responsible for orchestrating the step-by-step operations within a multiplier circuit?

<p>Controller (B)</p> Signup and view all the answers

Which digital component is employed to selectively pass the multiplicand and control signals to the n-bit adder in a multiplier circuit?

<p>MUX (B)</p> Signup and view all the answers

In the context of bit-pair recording, how are the bits '1 & 1' typically recorded?

<p>+1 (B)</p> Signup and view all the answers

What does the acronym CSA stand for in computer architecture?

<p>Carry Save Addition (A)</p> Signup and view all the answers

Which computer architecture paradigm is characterized by its focus on reducing the number of clock cycles per instruction, thereby decreasing overall execution time?

<p>RISC (D)</p> Signup and view all the answers

What is the primary goal both CISC and RISC architectures aim to minimize?

<p>Time delay (B)</p> Signup and view all the answers

A newly loaded instruction that is the destination of a branch or jump is known as a:

<p>Branch target (B)</p> Signup and view all the answers

The condition flag 'Z' is set to 1 to indicate:

<p>The result is zero. (B)</p> Signup and view all the answers

The stack frame for each subroutine is typically present in the:

<p>Processor Stack (A)</p> Signup and view all the answers

The primary advantage of using a single bus structure in a computer system is:

<p>Cost-effective connectivity and ease of attaching peripheral devices (A)</p> Signup and view all the answers

Which of the following are most commonly used to address differences in data transfer speeds among various devices?

<p>Buffer registers (C)</p> Signup and view all the answers

Which bus is commonly used to connect a monitor to the CPU in a computer system?

<p>PCI bus (D)</p> Signup and view all the answers

In a multiple bus organization, where are registers typically placed?

<p>Register file (B)</p> Signup and view all the answers

What is the primary advantage of a multiple bus organization compared to a single bus?

<p>Reduction in the number of cycles for execution (A)</p> Signup and view all the answers

Flashcards

John Von Neumann

Considered the father of modern computer architecture, he conceptualized the stored-program computer.

CPU

The central processing unit, which executes instructions.

Register

Fastest type of memory, directly accessible to the CPU.

ALU

Arithmetic Logic Unit; performs arithmetic and logical operations.

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Cache memory

A small, fast memory that stores frequently accessed data for quicker retrieval.

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Unidirectional Bus

Transmits data in one direction only.

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Flip-Flop

Stores a single bit of data.

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Physical Address

Actual memory location in the main memory.

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Status Bit

Also known as 'flag bit'. Indicates the result of an operation (e.g., overflow, zero).

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DMA (Direct Memory Access)

Direct Memory Access. A data transfer technique allowing peripherals to access system memory independently of the CPU.

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RISC

Reduced Instruction Set Computer. A CPU design philosophy favoring a smaller set of simpler instructions for faster execution.

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Hit Ratio (Cache)

The ratio of successful data requests to the cache memory to total data requests.

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Data Hazard

A delay in instruction execution because data needed is not immediately available.

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Interleaved Cycles

A technique where fetch and execute operations overlap, improving processing speed.

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LRU Algorithm

Replaces the block that has been least recently used.

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Zero-Address Instruction

A method using a stack to store operands, requiring no explicit addresses in instructions.

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Indirect Addressing Mode

Accesses memory indirectly through a pointer stored in another location.

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Memory-Mapped I/O

I/O devices and memory share the same address space.

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Single BUS Structure

A single communication pathway connects I/O devices.

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Interrupt Signal

Signals a read/write operation.

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Program-Controlled I/O

Repeatedly checking status flags to access I/O devices.

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Interrupts

Device sends a signal when ready.

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Mantissa

Sign followed by digits representing a number.

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Normalized Number

Decimal point to the right of the first significant digit.

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Forward Target

A new instruction loaded, representing a target to jump to.

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Condition Flag Z

Condition flag set to 1 indicating the result of an operation is zero.

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Stack Frame

Region of memory dedicated to storing information about active subroutines.

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Single Bus Virtue

Cost-effective connectivity and ease of attaching peripheral devices.

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Buffer Registers

Used to compensate for speed differences between devices.

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PCI Bus

The bus commonly used to connect a monitor to the CPU.

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Register File

Registers are grouped together and called...

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Multiple Bus Advantage

Faster execution due to parallel data transfer.

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Multiplier Register

Stores the multiplier value during multiplication.

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Multiplier Controller

Coordinates the operation of the multiplier.

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Multiplexer (MUX)

Passes multiplicand and control signals to the n-bit adder.

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CSA (Carry Save Addition)

Carry Save Adder; speeds up addition by saving carry bits.

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RISC architecture

Reduces execution time of instructions by simplifying them.

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CISC and RISC Aim

Reduces the gap between high-level languages and machine instructions.

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Power Efficient architecture?

Typically more power-efficient due to simpler instructions.

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ROM's role

Stores essential software that starts the computer.

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